JP2002100732A - Method for forming capacitive element - Google Patents
Method for forming capacitive elementInfo
- Publication number
- JP2002100732A JP2002100732A JP2000290847A JP2000290847A JP2002100732A JP 2002100732 A JP2002100732 A JP 2002100732A JP 2000290847 A JP2000290847 A JP 2000290847A JP 2000290847 A JP2000290847 A JP 2000290847A JP 2002100732 A JP2002100732 A JP 2002100732A
- Authority
- JP
- Japan
- Prior art keywords
- forming
- capacitance
- capacitive element
- parallel
- wirings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体集積回路に係
り、特に回路中に容量を形成する際の容量素子形成方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and, more particularly, to a method for forming a capacitance element when forming a capacitance in a circuit.
【０００２】[0002]
【従来の技術】従来より、半導体集積回路では、トラン
ジスタなどの能動素子の他に抵抗素子や容量素子等が形
成されている。例えば半導体集積回路中の特定の配線に
容量が必要になった場合、出力端子を結線していないト
ランジスタを作成し、その入力端子を上記配線に接続す
ることによって、トランジスタの入力端子の入力容量を
配線に付加する方法で対応していた。2. Description of the Related Art Conventionally, in a semiconductor integrated circuit, a resistance element, a capacitance element, and the like are formed in addition to an active element such as a transistor. For example, when capacitance is required for a specific wiring in a semiconductor integrated circuit, a transistor whose output terminal is not connected is created, and its input terminal is connected to the wiring, so that the input capacitance of the input terminal of the transistor is reduced. The method was added to the wiring.
【０００３】図７は特定の配線に容量が必要になった場
合の従来の容量付加方法を説明する図である。配線１１
にインバータ１２の入力端子を接続して、容量を配線１
１に付加している。FIG. 7 is a view for explaining a conventional capacitance adding method when a capacitance is required for a specific wiring. Wiring 11
To the input terminal of the inverter 12 and
1 is added.
【０００４】[0004]
【発明が解決しようとする課題】上記のように従来で
は、配線に容量を付加する場合には必ずトランジスタの
作成が必要であるため、その分回路が複雑になるという
問題があった。As described above, in the prior art, when a capacitance is added to a wiring, a transistor must be formed without fail, so that there has been a problem that the circuit becomes complicated accordingly.
【０００５】また、図８に示すように、Ｘ，Ｙ座標が同
一座標で、Ｚ座標が異なる配線層に異なる配線Ａ、Ｂを
形成することにより、異なる配線層間に並行平板コンデ
ンサを作成し、これにより特定の配線間に容量素子を作
成する方法もある。この場合、異なる配線層間に発生す
る容量を抑えるために、層間膜を厚くした製造プロセス
では、容量を作成するために大きな面積が必要になり、
面積効率が悪いという問題があった。また、従来の技術
では配線と配線との間に所定の容量を持たせるような設
計を行うことはできなかった。Further, as shown in FIG. 8, by forming different wirings A and B in wiring layers having the same X and Y coordinates and different Z coordinates, parallel plate capacitors are formed between different wiring layers. Thus, there is a method of forming a capacitor between specific wirings. In this case, in order to suppress the capacitance generated between different wiring layers, in a manufacturing process in which the interlayer film is thickened, a large area is required to create the capacitance.
There was a problem that area efficiency was poor. Further, in the prior art, it was not possible to design such that a predetermined capacitance was provided between wirings.
【０００６】本発明は、上述の如き従来の課題を解決す
るためになされたもので、その目的は、トランジスタを
用いることなく、面積効率が良好で、且つ配線と配線と
の間にも所定の容量を形成することができる半導体集積
回路の容量素子形成方法を提供することである。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. It is an object of the present invention to achieve a good area efficiency without using a transistor and a predetermined space between wirings. An object of the present invention is to provide a method for forming a capacitor of a semiconductor integrated circuit capable of forming a capacitor.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に、第１の発明の特徴は、半導体集積回路に容量素子を
形成する容量素子形成方法において、同一配線層に配線
されている少なくとも２本の配線を近接配置することに
より生じる線間容量を、容量素子とすることにある。In order to achieve the above object, a first aspect of the present invention is a method of forming a capacitor in a semiconductor integrated circuit, comprising a method of forming a capacitor in a semiconductor integrated circuit. The capacitance between lines generated by arranging these wirings in close proximity to each other is to be used as a capacitor.
【０００８】第２の発明の特徴は、半導体集積回路に容
量素子を形成する容量素子形成方法において、同一配線
層に平行して配線されている２本の主配線からそれぞれ
直交する方向に延びる同層の分岐線が順に平行になるよ
うに近接配置することにより生じる線間容量を、容量素
子とすることにある。According to a second aspect of the present invention, there is provided a method of forming a capacitor in a semiconductor integrated circuit, wherein the two main wirings extending in parallel to the same wiring layer extend in directions orthogonal to each other. An inter-line capacitance generated by arranging the branch lines of a layer close to each other so as to be parallel in order is to be used as a capacitor.
【０００９】第３の発明の特徴は、半導体集積回路に容
量素子を形成する容量素子形成方法において、同一配線
層に平行して配線されている２本の主配線からそれぞれ
直交する方向に延びる同層の分岐線が順に平行になるよ
うに近接配置し、且つ異なる２層間以上において主配線
からそれぞれ直交する方向に延びる同層の分岐線が順に
平行になるように近接配線することにより生じる線間容
量を、容量素子とすることにある。According to a third aspect of the present invention, in a method of forming a capacitive element in a semiconductor integrated circuit, two main wirings extending in parallel to the same wiring layer extend in directions orthogonal to each other. Lines formed by adjacently arranging branch lines of layers so that the branch lines of the same layer are arranged in parallel so that the branch lines of the same layer extending in the direction orthogonal to the main wiring in two or more different layers become parallel in order. The capacitor is used as a capacitor.
【００１０】[0010]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて説明する。図１は、本発明の半導体集積回路
の容量素子形成方法の第１の実施形態を説明する説明図
である。同一配線層にある配線１と配線２を平行に近接
配置して配線間容量を形成し、等価的な容量素子３を作
成する。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory diagram illustrating a first embodiment of a method for forming a capacitor of a semiconductor integrated circuit according to the present invention. Wiring 1 and wiring 2 in the same wiring layer are arranged in parallel and close to each other to form an inter-wiring capacitance, thereby forming an equivalent capacitive element 3.
【００１１】本実施形態によれば、近年の半導体製造プ
ロセスの微細化の進展で配線間の距離が縮小しているた
め、配線間容量が増大化し、異層間に並行平板コンデン
サを形成する従来例に比べて、同一配線層での線間容量
を利用して、所定の容量の並行平板型のコンデンサを形
成することができ、しかも、同一層間で、且つ近接配線
により形成されるため、面積効率を良好とすることがで
きる。According to the present embodiment, since the distance between the wirings has been reduced due to the recent progress in miniaturization of the semiconductor manufacturing process, the capacitance between the wirings has been increased, and a parallel plate capacitor is formed between different layers. As compared with the above, a parallel plate type capacitor having a predetermined capacitance can be formed by utilizing the line capacitance in the same wiring layer, and furthermore, since it is formed between the same layer and by adjacent wiring, the area efficiency is improved. Can be made favorable.
【００１２】図２は、本発明の半導体集積回路の容量素
子形成方法の第２の実施形態を説明する図である。同一
配線層にある配線４と配線５は、それぞれ平行な主配線
４ａ，配線５ａの部分に櫛形に配列された複数の分岐線
４ｂ，５ｂが形成され、これら分岐線４ｂ，５ｂが互い
に平行で近接するように、且つ配線４ａ，５ａが平行に
なるように、配線４と配線５が同一層に配置され、並行
平板型のコンデンサを形成している。FIG. 2 is a diagram for explaining a second embodiment of the method for forming a capacitance element of a semiconductor integrated circuit according to the present invention. A plurality of branch lines 4b and 5b arranged in a comb shape are formed at the portions of the main wiring 4a and the wiring 5a which are in parallel with each other in the wirings 4 and 5 in the same wiring layer, and these branch lines 4b and 5b are parallel to each other. The wiring 4 and the wiring 5 are arranged in the same layer so that they are close to each other and the wirings 4a and 5a are parallel, thereby forming a parallel plate type capacitor.
【００１３】本実施形態によれば、配線４と配線５が平
行になる部分が長いため、大きな容量素子を同一層に容
易且つ面積効率良好に形成することができる。According to this embodiment, since the portion where the wiring 4 and the wiring 5 are parallel to each other is long, a large capacitance element can be easily formed on the same layer with good area efficiency.
【００１４】図３は、本発明の半導体集積回路の容量素
子形成方法の第３の実施形態を説明する図である。本例
は、図２に示した第２の実施形態の構成を同一層だけで
なく、複数層間に構成したものである。配線Ａ，配線Ｂ
は同一層で横方向に互い違いに配置され、配線Ａと配線
Ｂは異なる層間で縦方向に互い違いに配置されて、並行
平板コンデンサを形成している。FIG. 3 is a view for explaining a third embodiment of the method for forming a capacitor element of a semiconductor integrated circuit according to the present invention. In this example, the configuration of the second embodiment shown in FIG. 2 is configured not only in the same layer but also in a plurality of layers. Wiring A, Wiring B
Are arranged alternately in the horizontal direction in the same layer, and the wirings A and B are alternately arranged in the vertical direction between the different layers to form a parallel plate capacitor.
【００１５】本実施形態によれば、同一層だけでなく、
複数層間を用いて配線Ａ，ＢをＸ，Ｙ方向及びＺ方向に
互い違いになるように平行配置しているため、図２に示
した構成よりも、更に大容量の容量素子を面積効率良好
に形成することができる。According to this embodiment, not only the same layer,
Since the wirings A and B are arranged in parallel so as to be staggered in the X, Y and Z directions using a plurality of layers, a capacitive element having a larger capacity can be provided with better area efficiency than the configuration shown in FIG. Can be formed.
【００１６】図４は本発明の半導体集積回路の容量素子
形成方法を実際の回路に適用して容量を形成した構成例
である。同一層の正電源配線ＶＤＤと負電源配線ＶＳＳ
を近接配置して、両配線間に電源間のバィパスコンデン
サ（容量素子）６を形成した例である。FIG. 4 shows an example of a structure in which a capacitance is formed by applying the method of forming a capacitance element of a semiconductor integrated circuit according to the present invention to an actual circuit. Positive power supply line VDD and negative power supply line VSS in the same layer
Are arranged close to each other, and a bypass capacitor (capacitance element) 6 between power supplies is formed between both wirings.
【００１７】図５は本発明の半導体集積回路の容量素子
形成方法を実際の回路に適用して容量を形成した例であ
る。同一層の配線Ａと正電源配線ＶＤＤを近接配置し
て、特定の配線Ａと正電源との間に容量素子７を形成し
た例である。FIG. 5 shows an example in which a capacitance is formed by applying the method of forming a capacitor of a semiconductor integrated circuit according to the present invention to an actual circuit. In this example, a wiring A in the same layer and a positive power supply wiring VDD are arranged close to each other, and a capacitor 7 is formed between a specific wiring A and a positive power supply.
【００１８】図６は本発明の半導体集積回路の容量素子
形成方法を実際の回路に適用して容量を形成した例であ
る。同一層の配線Ａと負電源配線ＶＳＳを近接配置し
て、特定の配線Ａと正電源との間に容量素子８を形成し
た例である。FIG. 6 shows an example in which a capacitance is formed by applying the method of forming a capacitor of a semiconductor integrated circuit according to the present invention to an actual circuit. This is an example in which a wiring A and a negative power supply wiring VSS of the same layer are arranged close to each other, and a capacitive element 8 is formed between a specific wiring A and a positive power supply.
【００１９】[0019]
【発明の効果】以上詳細に説明したように、本発明の半
導体集積回路の容量素子形成方法によれば、同一層間で
２本の配線を近接配置して形成される配線容量を利用す
ることにより、トランジスタを用いることなく、面積効
率良好に容量素子を形成でき、且つ配線と配線との間に
も所定の容量を形成することができる。As described in detail above, according to the method of forming a capacitor of a semiconductor integrated circuit of the present invention, the wiring capacitance formed by closely arranging two wirings between the same layers is utilized. A capacitor can be formed with good area efficiency without using a transistor, and a predetermined capacitance can be formed between wirings.
【図１】本発明の半導体集積回路の容量素子形成方法の
第１の実施形態を説明する説明図である。FIG. 1 is an explanatory diagram illustrating a first embodiment of a method for forming a capacitor of a semiconductor integrated circuit according to the present invention.
【図２】本発明の半導体集積回路の容量素子形成方法の
第２の実施形態を説明する図である。FIG. 2 is a diagram illustrating a second embodiment of a method for forming a capacitor of a semiconductor integrated circuit according to the present invention.
【図３】本発明の半導体集積回路の容量素子形成方法の
第３の実施形態を説明する図である。FIG. 3 is a diagram illustrating a third embodiment of a method for forming a capacitance element of a semiconductor integrated circuit according to the present invention.
【図４】本発明の半導体集積回路の容量素子形成方法を
実際の回路に適用して容量を形成した構成例である。FIG. 4 is a configuration example in which a capacitance is formed by applying the method of forming a capacitance element of a semiconductor integrated circuit of the present invention to an actual circuit.
【図５】本発明の半導体集積回路の容量素子形成方法を
実際の回路に適用して容量を形成した例である。FIG. 5 is an example in which a capacitor is formed by applying the method of forming a capacitor of a semiconductor integrated circuit of the present invention to an actual circuit.
【図６】本発明の半導体集積回路の容量素子形成方法を
実際の回路に適用して容量を形成した例である。FIG. 6 is an example in which a capacitance is formed by applying the method for forming a capacitance element of a semiconductor integrated circuit of the present invention to an actual circuit.
【図７】従来の方法で半導体集積回路に容量素子を形成
する方法を説明する図である。FIG. 7 is a diagram illustrating a method for forming a capacitor in a semiconductor integrated circuit by a conventional method.
【図８】従来の方法で半導体集積回路に容量素子を形成
する他の方法を説明する図である。FIG. 8 is a diagram illustrating another method for forming a capacitor on a semiconductor integrated circuit by a conventional method.
１、２、４、４ａ、５、５ａ、Ａ、Ｂ 配線 ３、６、７、８ 容量素子 ４ｂ、５ｂ 分岐線 1, 2, 4, 4a, 5, 5a, A, B Wiring 3, 6, 7, 8 Capacitance element 4b, 5b Branch line
Claims (4)
量素子形成方法において、 同一配線層に配線されている少なくとも２本の配線を近
接配置することにより生じる線間容量を、容量素子とす
ることを特徴とする容量素子形成方法。In a method for forming a capacitor in a semiconductor integrated circuit, a capacitance between lines generated by arranging at least two wirings arranged in the same wiring layer close to each other is used as the capacitor. A method for forming a capacitive element.
量素子形成方法において、 同一配線層に平行して配線されている２本の主配線から
それぞれ直交する方向に延びる同層の分岐線が順に平行
になるように近接配置することにより生じる線間容量
を、容量素子とすることを特徴とする容量素子形成方
法。2. A method of forming a capacitive element in a semiconductor integrated circuit, comprising: forming two branch lines extending in the direction orthogonal to each other from two main wirings arranged in parallel in the same wiring layer; A method for forming a capacitance element, wherein a capacitance between lines generated by closely arranging the lines in parallel is used as a capacitance element.
量素子形成方法において、 同一配線層に平行して配線されている２本の主配線から
それぞれ直交する方向に延びる同層の分岐線が順に平行
になるように近接配置し、且つ異なる２層間以上におい
て主配線からそれぞれ直交する方向に延びる同層の分岐
線が順に平行になるように近接配線することにより生じ
る線間容量を、容量素子とすることを特徴とする容量素
子形成方法。3. A capacitive element forming method for forming a capacitive element in a semiconductor integrated circuit, wherein branch lines of the same layer extending in orthogonal directions from two main wirings arranged in parallel in the same wiring layer are sequentially formed. The inter-line capacitance, which is generated by arranging adjacent lines so as to be in parallel so as to be parallel to each other and so that branch lines in the same layer extending in directions orthogonal to the main lines in two or more different layers are sequentially parallel to each other, is referred to as a capacitance element. A method for forming a capacitive element.
で、他方が負電源配線であることを特徴とする請求項１
乃至３記載の容量素子形成方法。4. The semiconductor device according to claim 1, wherein one of the two wirings is a positive power supply wiring and the other is a negative power supply wiring.
4. The method for forming a capacitive element according to any one of claims 3 to 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000290847A JP2002100732A (en) | 2000-09-25 | 2000-09-25 | Method for forming capacitive element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000290847A JP2002100732A (en) | 2000-09-25 | 2000-09-25 | Method for forming capacitive element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002100732A true JP2002100732A (en) | 2002-04-05 |
Family
ID=18774011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000290847A Pending JP2002100732A (en) | 2000-09-25 | 2000-09-25 | Method for forming capacitive element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002100732A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7276776B2 (en) | 2004-01-06 | 2007-10-02 | Renesas Technology Corp. | Semiconductor device |
| JP2008103527A (en) * | 2006-10-19 | 2008-05-01 | Renesas Technology Corp | Semiconductor device |
| JP2009186305A (en) * | 2008-02-06 | 2009-08-20 | Epson Toyocom Corp | Physical quantity sensor |
-
2000
- 2000-09-25 JP JP2000290847A patent/JP2002100732A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7276776B2 (en) | 2004-01-06 | 2007-10-02 | Renesas Technology Corp. | Semiconductor device |
| US7446390B2 (en) | 2004-01-06 | 2008-11-04 | Renesas Technology Corp. | Semiconductor device |
| US7557427B2 (en) | 2004-01-06 | 2009-07-07 | Renesas Technology Corp. | Semiconductor device |
| US7915708B2 (en) | 2004-01-06 | 2011-03-29 | Renesas Electronics Corporation | Semiconductor device |
| US8237282B2 (en) | 2004-01-06 | 2012-08-07 | Renesas Electronics Corporation | Semiconductor device |
| JP2008103527A (en) * | 2006-10-19 | 2008-05-01 | Renesas Technology Corp | Semiconductor device |
| JP2009186305A (en) * | 2008-02-06 | 2009-08-20 | Epson Toyocom Corp | Physical quantity sensor |
| US8250917B2 (en) | 2008-02-06 | 2012-08-28 | Seiko Epson Corporation | Physical quantity sensor |
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