JP2002094116A - Compound semiconductor light emitting device and its manufacturing method - Google Patents

Compound semiconductor light emitting device and its manufacturing method

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Publication number
JP2002094116A
JP2002094116A JP2001003249A JP2001003249A JP2002094116A JP 2002094116 A JP2002094116 A JP 2002094116A JP 2001003249 A JP2001003249 A JP 2001003249A JP 2001003249 A JP2001003249 A JP 2001003249A JP 2002094116 A JP2002094116 A JP 2002094116A
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JP
Japan
Prior art keywords
layer
gan
blue led
type
based semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001003249A
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Japanese (ja)
Inventor
Meitoku Rin
明徳 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RENYU KAGI KOFUN YUGENKOSHI
Original Assignee
RENYU KAGI KOFUN YUGENKOSHI
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Application filed by RENYU KAGI KOFUN YUGENKOSHI filed Critical RENYU KAGI KOFUN YUGENKOSHI
Publication of JP2002094116A publication Critical patent/JP2002094116A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49107Connecting at different heights on the semiconductor or solid-state body
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    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a compound semiconductor light emitting device and its manufacturing method whereby wire bonding can be performed only at one step in its manufacturing process and a current is spread uniformly. SOLUTION: The compound semiconductor light emitting device has a GaN semiconductor laminate structure formed on an insulation board. This structure comprises a topmost p-type layer and a light emitting active layer sandwiched between an n-type layer and the p-type layer. The periphery of this structure is etched to recess a peripheral exposed surface of the n-layer relative to its central part. An n-type electrode is formed on the exposed surface of the n-type layer, and a p-type electrode not electrically connected to the n-type electrode is formed on the p-type layer. A conductive layer is applied which covers the side wall and bottom surface of the insulation board and is not electrically connected to the n-type electrode, and an adhesive layer for increasing the adhesion is sandwiched between the side wall and the bottom surface of the insulation board and the conductive layer. The conductive layer is formed on a reflection mirror or a transparent layer.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、化合物半導体発光
素子及びその製造方法に関し、特に、側壁と底部表面が
塗布導電層に覆われる化合物半導体発光素子(例えば、
GaN系の発光ダイオード)及びその製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor light emitting device and a method of manufacturing the same, and more particularly, to a compound semiconductor light emitting device (for example, a compound semiconductor light emitting device in which a side wall and a bottom surface are covered with a coating conductive layer).
GaN-based light-emitting diode) and a method for manufacturing the same.

【0002】[0002]

【従来の技術】近年、例えば青色LEDまたは青色レー
ザーダイオード(Laser diode,LD)のような青色、
緑色または青/緑色発光素子の製造材料として、GaN
系化合物半導体が脚光を浴びている。従来の青色LED
は、一般に、基板上に、少なくとも一つのn型GaN系
化合物半導体層と、本質またはドープされたGaN系化
合物半導体材料で形成される活性層と、少なくとも一つ
のp型GaN系化合物半導体層と、を順に積層して構成
される。
2. Description of the Related Art In recent years, blue light, such as a blue LED or a blue laser diode (Laser diode, LD), has been developed.
GaN as a manufacturing material for green or blue / green light emitting devices
-Based compound semiconductors are in the spotlight. Conventional blue LED
In general, on a substrate, at least one n-type GaN-based compound semiconductor layer, an active layer formed of an intrinsic or doped GaN-based compound semiconductor material, at least one p-type GaN-based compound semiconductor layer, Are sequentially laminated.

【0003】従来の青色LEDの製造において、基板材
料として透明なサファイアがよく使われる。他の半導体
発光素子に用いられる半導体基板と異なり、サファイア
は電気絶縁材料であるため、n型電極をサファイア基板
上に直接に形成することができない。この問題を解決す
るために、青色LEDをエッチングしてn型GaN系化
合物半導体層を部分的に露出させることによりn型電極
を効率よく形成できる導電の表面が提供される。
In the production of conventional blue LEDs, transparent sapphire is often used as a substrate material. Unlike a semiconductor substrate used for other semiconductor light emitting devices, sapphire is an electrically insulating material, so that an n-type electrode cannot be formed directly on the sapphire substrate. In order to solve this problem, there is provided a conductive surface capable of efficiently forming an n-type electrode by etching a blue LED to partially expose an n-type GaN-based compound semiconductor layer.

【0004】図1は、従来の青色LEDを示す断面図で
ある。図1に示すように、従来の青色LEDは、サファ
イア基板101と、n型GaN系化合物半導体層102
と、本質またはドープされたGaN系化合物半導体材料
で形成される活性層103と、p型GaN系化合物半導
体層104と、n型GaN系化合物半導体層102の露
出表面に形成されるn型電極105と、p型GaN系化
合物半導体層104上に形成されるp型電極106と、
を備えている。
FIG. 1 is a sectional view showing a conventional blue LED. As shown in FIG. 1, a conventional blue LED includes a sapphire substrate 101 and an n-type GaN-based compound semiconductor layer 102.
An active layer 103 formed of an intrinsic or doped GaN-based compound semiconductor material; a p-type GaN-based compound semiconductor layer 104; and an n-type electrode 105 formed on an exposed surface of the n-type GaN-based compound semiconductor layer 102 And a p-type electrode 106 formed on the p-type GaN-based compound semiconductor layer 104;
It has.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、このよ
うな従来の青色LEDは、以下のような欠点がある。ま
ず、青色LEDの絶縁サファイア基板101がカップ形
状のリードフレーム107の表面上に載置される際に、
青色LEDの絶縁サファイア基板101はカップ形状の
リードフレーム107と電気的に接続されていない。青
色LEDをカップ形状のリードフレーム107と電気的
に接続するために、図2に示すように、金属接続ワイヤ
ー108によって、n型電極105をカップ形状のリー
ドフレーム107と電気的に接続させることが必要であ
る。そして、金属接続ワイヤー109によって、p型電
極106を分離リードフレーム110と電気的に接続す
るため、ワイヤーボンディングの製造工程を2回行わな
ければならない。また、金属ボンディングワイヤー10
9は、ボンディングパッド111を介して、p型電極1
06と電気的に接続することが好ましい。従って、従来
の青色LEDの製造において、このように、ワイヤーボ
ンディング工程を2回も行うため、製造工程が複雑で、
チップサイズも大きく、高コストの原因になる。
However, such a conventional blue LED has the following disadvantages. First, when the insulating sapphire substrate 101 of the blue LED is placed on the surface of the cup-shaped lead frame 107,
The insulating sapphire substrate 101 of the blue LED is not electrically connected to the cup-shaped lead frame 107. In order to electrically connect the blue LED to the cup-shaped lead frame 107, the n-type electrode 105 may be electrically connected to the cup-shaped lead frame 107 by a metal connection wire 108 as shown in FIG. is necessary. Then, in order to electrically connect the p-type electrode 106 to the separation lead frame 110 by the metal connection wire 109, the manufacturing process of wire bonding must be performed twice. In addition, the metal bonding wire 10
9 denotes a p-type electrode 1 via a bonding pad 111.
06 is preferably electrically connected. Therefore, in the conventional blue LED manufacturing, since the wire bonding process is performed twice as described above, the manufacturing process is complicated,
The chip size is large, which causes high cost.

【0006】図3は、図1に示した従来の青色LEDに
おける電極の配置を示す平面図である。図3に示すよう
に、従来の青色LEDは、n型電極105とp型電極1
06との構造及び配列が非対称的であるため、電流が上
下方向に対称的に流れない。このため、従来の青色LE
Dは、電流を均一に広げることができない。従って、従
来の青色LEDには、作動中に容易に損害をもたらす高
電流密度点が幾つか存在する。
FIG. 3 is a plan view showing the arrangement of electrodes in the conventional blue LED shown in FIG. As shown in FIG. 3, a conventional blue LED includes an n-type electrode 105 and a p-type electrode 1.
Since the structure and arrangement with the element 06 are asymmetric, current does not flow symmetrically in the vertical direction. For this reason, the conventional blue LE
D cannot spread the current uniformly. Thus, there are several high current density points in conventional blue LEDs that are easily damaged during operation.

【0007】さらに、従来の青色LEDは、周知の静電
気放電(ESD)問題が絶縁のサファイア基板101に
発生する。以上の欠点を有するため、従来の青色LED
は、機能と信頼性が低い。
Further, in the conventional blue LED, a known electrostatic discharge (ESD) problem occurs on the insulating sapphire substrate 101. Due to the above disadvantages, conventional blue LEDs
Has poor function and reliability.

【0008】ここで、ワイヤーボンディングの製造工程
を1回で済み、製造工程が簡単なローコストの青色LE
Dが期待される。また、電流が均一に分散し、ESD問
題の発生しない青色LEDも期待される。さらに、底部
の表面上に発光効率をアップするための反射ミラーを設
ける青色LEDも期待される。
[0008] Here, the manufacturing process of wire bonding only needs to be performed once, and the low-cost blue LE with a simple manufacturing process is used.
D is expected. Further, a blue LED in which the current is uniformly dispersed and the ESD problem does not occur is expected. Further, a blue LED provided with a reflection mirror on the bottom surface to increase the luminous efficiency is also expected.

【0009】[0009]

【課題を解決するための手段】本発明の目的は、上述の
問題を鑑みてなされたものであって、ワイヤーボンディ
ングの製造工程を1回で済み、製造工程が簡単でローコ
ストの化合物半導体発光素子及びその製造方法を提供す
ることにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made in view of the above-mentioned problem. The manufacturing process of wire bonding can be performed only once, and the manufacturing process is simple and low-cost. And a method for manufacturing the same.

【0010】本発明のもう一つの目的は、電流を均一に
広げる化合物半導体発光素子及びその製造方法を提供す
ることにある。
It is another object of the present invention to provide a compound semiconductor light emitting device capable of uniformly spreading a current and a method of manufacturing the same.

【0011】本発明のさらに一つの目的は、静電気放電
問題の発生しない化合物半導体発光素子及びその製造方
法を提供することにある。
It is still another object of the present invention to provide a compound semiconductor light emitting device which does not cause a problem of electrostatic discharge and a method of manufacturing the same.

【0012】本発明のさらにまた一つの目的は、底部表
面上に形成される反射ミラーを持つ化合物半導体発光素
子及びその製造方法を提供することにある。
It is still another object of the present invention to provide a compound semiconductor light emitting device having a reflection mirror formed on a bottom surface and a method of manufacturing the same.

【0013】本発明の第1の実施形態による化合物半導
体発光素子は、絶縁基板と、前記絶縁基板の上部表面に
形成され、中央部の表面が周辺部の表面より高い第1G
aN系半導体層と、前記第1GaN系半導体層の中央部
の表面上に形成され、光を発生する活性層と、前記活性
層上に形成される第2GaN系半導体層と、前記第2G
aN系半導体層上に形成される第1電極と、前記絶縁基
板の側壁と底部表面に塗布され、前記第1GaN系半導
体層の側壁と電気的に接続する導電層と、を備えてい
る。
The compound semiconductor light emitting device according to the first embodiment of the present invention is formed on an insulating substrate and an upper surface of the insulating substrate, and has a first surface having a central portion higher than a peripheral surface.
an aN-based semiconductor layer; an active layer formed on a surface of a central portion of the first GaN-based semiconductor layer to generate light; a second GaN-based semiconductor layer formed on the active layer;
a first electrode formed on the aN-based semiconductor layer; and a conductive layer applied to a sidewall and a bottom surface of the insulating substrate and electrically connected to the sidewall of the first GaN-based semiconductor layer.

【0014】本発明の第1の実施形態による化合物半導
体発光素子の製造方法は、絶縁基板を提供する工程と、
前記絶縁基板上に第1GaN系半導体層を形成する工程
と、前記第1GaN系半導体層上に光の発生する活性層
を形成する工程と、前記活性層上に第2GaN系半導体
層を形成する工程と、前記第2GaN系半導体層、前記
活性層及び前記第1GaN系半導体層の周辺部をそれぞ
れエッチングすることにより、前記第1GaN系半導体
の周辺部の露出表面を中央部の表面より低くさせる工程
と、前記第2GaN系半導体層上に第1電極を形成する
工程と、前記絶縁基板の側壁と底部表面を覆うととも
に、前記第1GaN系半導体層の側壁と電気的に接続す
る導電層を塗布する工程と、を備えている。
The method for manufacturing a compound semiconductor light emitting device according to the first embodiment of the present invention comprises the steps of: providing an insulating substrate;
Forming a first GaN-based semiconductor layer on the insulating substrate, forming an active layer that generates light on the first GaN-based semiconductor layer, and forming a second GaN-based semiconductor layer on the active layer And etching the peripheral portions of the second GaN-based semiconductor layer, the active layer, and the first GaN-based semiconductor layer so that the exposed surface of the peripheral portion of the first GaN-based semiconductor is lower than the surface of the central portion. Forming a first electrode on the second GaN-based semiconductor layer, and applying a conductive layer that covers a sidewall and a bottom surface of the insulating substrate and is electrically connected to the sidewall of the first GaN-based semiconductor layer. And

【0015】本発明の第2の実施形態によると、第1G
aN系半導体層の周辺部の表面上に形成される第2電極
は、活性層、第2GaN系半導体層及び第1電極と電気
的に接続しないが、前記絶縁基板の側壁と底部表面を覆
う導電層と電気的に接続する。
According to a second embodiment of the present invention, the first G
The second electrode formed on the surface of the peripheral portion of the aN-based semiconductor layer is not electrically connected to the active layer, the second GaN-based semiconductor layer, and the first electrode, but is electrically conductive to cover the side wall and the bottom surface of the insulating substrate. Make an electrical connection with the layer.

【0016】本発明の第3の実施形態によると、前記絶
縁基板の側壁及び底部表面に、前記第1電極と前記導電
層との間の粘着性を増強するための付着層が形成されて
から、この付着層上に前記塗布導電層が形成される。
According to a third embodiment of the present invention, after the adhesion layer for enhancing the adhesiveness between the first electrode and the conductive layer is formed on the side wall and the bottom surface of the insulating substrate. The applied conductive layer is formed on the adhesion layer.

【0017】本発明の第4の実施形態によると、前記導
電層は透光性であり、ITO酸化物層、CTO酸化物
層、ZnO酸化物層または薄金属層で形成される。前記
薄金属層は、厚みが0.001μmから1μmの範囲内
であり、Au、Ni、Pt、Al、Sn、In、Cr、
Ti、またはそれらの合金で形成される。
According to a fourth embodiment of the present invention, the conductive layer is translucent and is formed of an ITO oxide layer, a CTO oxide layer, a ZnO oxide layer or a thin metal layer. The thin metal layer has a thickness in the range of 0.001 μm to 1 μm, and includes Au, Ni, Pt, Al, Sn, In, Cr,
It is formed of Ti or an alloy thereof.

【0018】[0018]

【発明の実施の形態】以下、図面を参照して本発明の実
施形態について詳しく説明する。
Embodiments of the present invention will be described below in detail with reference to the drawings.

【0019】(第1の実施形態)図4〜図8は、本発明
の第1の実施形態における青色LED400の製造工程
を示す断面図である。
(First Embodiment) FIGS. 4 to 8 are sectional views showing steps of manufacturing a blue LED 400 according to a first embodiment of the present invention.

【0020】まず、図4に示すように、絶縁基板401
上に厚さ3μm〜5μmのn型層402が形成される。
絶縁基板401は、通常サファイアで形成される。その
後、n型層402上には、厚さ0.1μm〜0.3μmのn型
拘束層403と、厚さ500Å〜2000Åの発光用の
活性層404と、厚さ0.1μm〜0.3μmのp型拘束層4
05と、厚さ0.2μm〜1μmのp型層406とが、順
に形成される。402から406の各層は、GaN系化
合物半導体材料で形成される。例えば、4元素化合物半
導体材料InxAlyGa1-x-yN(x,yはモル分率で、
0≦x<1、0≦y<1、x+y=1)によって、導電
形態及びドーパント濃度の異なる402〜406の各層
を形成することができる。
First, as shown in FIG.
An n-type layer 402 having a thickness of 3 μm to 5 μm is formed thereon.
The insulating substrate 401 is usually formed of sapphire. Thereafter, on the n-type layer 402, an n-type constrained layer 403 having a thickness of 0.1 μm to 0.3 μm, an active layer 404 for light emission having a thickness of 500 to 2000 °, and a p-type constrained layer having a thickness of 0.1 μm to 0.3 μm. Layer 4
05 and a p-type layer 406 having a thickness of 0.2 μm to 1 μm are sequentially formed. Each of layers 402 to 406 is formed of a GaN-based compound semiconductor material. For example, a quaternary compound semiconductor material In x Al y Ga 1-xy N (x and y are mole fractions,
According to 0 ≦ x <1, 0 ≦ y <1, x + y = 1), layers 402 to 406 having different conductivity types and dopant concentrations can be formed.

【0021】次に、図5に示すように、所定パターンの
フォトマスクを用いて、フォトリソグラフィクにより青
色LED400を部分的にエッチングして周辺部を取り
除く。エッチングの時間を精確に制御することにより、
n型層402を露出させる。n型層402は、周辺部の
露出表面402aが中央部の表面402b(即ちn型層
402とn型拘束層403との間のインターフェース)
より低くになるように軽くエッチングされることが好ま
しい。エッチング工程が終了した後、青色LED400
は台形状の構造になり、上部の側壁400aが下部の側
壁400bより奥の方に位置する。本実施例において、
エッチング工程がドライエッチングを利用することが好
ましい。
Next, as shown in FIG. 5, using a photomask having a predetermined pattern, the blue LED 400 is partially etched by photolithography to remove the peripheral portion. By precisely controlling the etching time,
The n-type layer 402 is exposed. The n-type layer 402 has a peripheral exposed surface 402a having a central surface 402b (that is, an interface between the n-type layer 402 and the n-type constrained layer 403).
Preferably, it is lightly etched to be lower. After the etching process is completed, the blue LED 400
Has a trapezoidal structure, and the upper side wall 400a is located deeper than the lower side wall 400b. In this embodiment,
Preferably, the etching process utilizes dry etching.

【0022】続いて、図6に示すように、p型層406
の表面上にp型電極409が形成される。p型電極40
9は、p型GaN系化合物半導体材料とp型オーミック
接触を形成できる如何なる金属で形成される。本実施例
において、p型電極409は、例えばNi、Ti、A
l、Auまたはそれらの合金で形成される。p型電極4
09を形成する際に、厚さ50Å〜250Åの透明接触
層(transparent contact layer, TCL)407をp
型層406とp型電極409との間に入れてp型層40
6の全表面を覆うことにより、青色LED400の発光
効率及び電流分散均一度を同時に増やすことが好まし
い。TCL407は、透光性オーミック接触層であり、
例えばAu、Ni、Pt、Al、Sn、In、Cr、T
iまたはそれらの合金のような導電材料で形成される。
Subsequently, as shown in FIG. 6, the p-type layer 406 is formed.
A p-type electrode 409 is formed on the surface of the substrate. p-type electrode 40
9 is made of any metal capable of forming a p-type ohmic contact with a p-type GaN-based compound semiconductor material. In this embodiment, the p-type electrode 409 is made of, for example, Ni, Ti, A
1, Au or an alloy thereof. p-type electrode 4
When forming the layer 09, a transparent contact layer (TCL) 407 having a thickness of
Between the p-type layer 406 and the p-type electrode 409,
It is preferable to simultaneously increase the luminous efficiency and the current dispersion uniformity of the blue LED 400 by covering the entire surface of the blue LED 6. TCL 407 is a translucent ohmic contact layer,
For example, Au, Ni, Pt, Al, Sn, In, Cr, T
i or a conductive material such as an alloy thereof.

【0023】その後、図7に示すように、青色LED4
00上に、青色LED400の頂面及び上部の側壁40
0a及びn型層402aの露出表面を覆うように、PV
C(polyvinyl chloride)で形成する弾性巻きシート41
0が配置される。よって、青色LED400の下部の側
壁400bと底部表面400cのみが露出することにな
った。
Thereafter, as shown in FIG.
00, the top surface and the upper side wall 40 of the blue LED 400.
0a and the exposed surface of the n-type layer 402a.
Elastic rolled sheet 41 made of C (polyvinyl chloride)
0 is placed. Therefore, only the lower side wall 400b and the bottom surface 400c of the blue LED 400 are exposed.

【0024】最後に、図8に示すように、n型電極とし
て、青色LED400の下部の側壁400bと底部表面
400cを直接に覆うための導電層411が塗布され
る。青色LEDの頂面と上部の側壁400aとn型層4
02の露出表面402aは、弾性巻きシート410に保
護されるため、導電層411と接触しない。導電層41
1は、n型層402とn型オーミック接触を形成できる
如何なる金属、例えば、Au、Al、Ti、Cr、また
はそれらの合金で形成される。導電層411を形成した
後、弾性巻きシート410を取り除いて、青色LED4
00の頂面と上部の側壁400aとn型層402の露出
表面402aを露出させる。導電層411はn型層40
2の側壁にn型層402と電気的に接続するため、n型
電極として機能する。これにより、本発明の第1の実施
形態による青色LEDが完成される。
Finally, as shown in FIG. 8, a conductive layer 411 for directly covering the lower side wall 400b and the bottom surface 400c of the blue LED 400 is applied as an n-type electrode. Top and top sidewalls 400a of blue LED and n-type layer 4
The exposed surface 402 a of 02 is protected by the elastic winding sheet 410 and does not contact the conductive layer 411. Conductive layer 41
1 is formed of any metal capable of forming an n-type ohmic contact with the n-type layer 402, for example, Au, Al, Ti, Cr, or an alloy thereof. After forming the conductive layer 411, the elastic rolled sheet 410 is removed, and the blue LED 4
Then, the top surface and upper side wall 400a and the exposed surface 402a of the n-type layer 402 are exposed. The conductive layer 411 is the n-type layer 40
Since the side wall 2 is electrically connected to the n-type layer 402, it functions as an n-type electrode. Thereby, the blue LED according to the first embodiment of the present invention is completed.

【0025】図9は、図4〜図8に示す本発明の第1の
実施形態における青色LED400を示す平面図であ
る。図9に示すように、青色LED400のp型電極4
09とn型電極としての導電層411は、構造と配列が
対称的である。従って、青色LED400における電流
は、上下方向に沿ってp型電極409から導電層411
に流れ、しかも、図9の矢印に示すように、外側に向い
て均一に広がる。よって、本発明の青色LED400
は、効率よく電流を均一に広げる、高電流密度点が存在
しない。また、青色LED400の信頼性及び使用寿命
が格段に改善される。もちろん、p型電極409及び導
電層411は図9の特定形状に限定されることなく、種
々の変更が可能である。
FIG. 9 is a plan view showing the blue LED 400 according to the first embodiment of the present invention shown in FIGS. As shown in FIG. 9, the p-type electrode 4 of the blue LED 400
09 and the conductive layer 411 as an n-type electrode are symmetric in structure and arrangement. Therefore, the current in the blue LED 400 flows from the p-type electrode 409 to the conductive layer 411 along the vertical direction.
And spread uniformly outward as shown by the arrow in FIG. Therefore, the blue LED 400 of the present invention
Does not have a high current density point that efficiently and uniformly spreads the current. Further, the reliability and service life of the blue LED 400 are significantly improved. Of course, the p-type electrode 409 and the conductive layer 411 are not limited to the specific shape shown in FIG. 9 and various changes can be made.

【0026】図10は、本発明の第1の実施形態におけ
る青色LED400をカップ形状のリードフレーム10
7及び分離リードフレーム110に接続する方式を示す
断面図である。導電層411がn型層402と電気的に
接続し、青色LED400の底部表面400cを覆って
いるため、青色LED400がカップ形状のリードフレ
ーム107上に載置されると、n型層402は、導電層
411を介してカップ形状のリードフレーム107の表
面と電気的に接続する。言い換えれば、接続ワイヤーを
使わずにn型層402とカップ形状のリードフレーム1
07とを電気的に接続することができる。従って、p型
電極409と分離リードフレーム110との間のみ、接
続線109を使って電気的に接続する。よって、本発明
の青色LED400は、ワイヤーボンディングの製造工
程を1回で済むため、製造工程を簡素化し、製造コスト
も下げる。
FIG. 10 shows a blue LED 400 according to the first embodiment of the present invention.
FIG. 7 is a cross-sectional view illustrating a method of connecting to a separation lead frame 110 and a separation lead frame 110. Since the conductive layer 411 is electrically connected to the n-type layer 402 and covers the bottom surface 400c of the blue LED 400, when the blue LED 400 is placed on the cup-shaped lead frame 107, the n-type layer 402 It is electrically connected to the surface of the cup-shaped lead frame 107 via the conductive layer 411. In other words, without using the connection wire, the n-type layer 402 and the cup-shaped lead frame 1 are not used.
07 can be electrically connected. Therefore, only the p-type electrode 409 and the separation lead frame 110 are electrically connected using the connection line 109. Therefore, the blue LED 400 of the present invention simplifies the manufacturing process and reduces the manufacturing cost because only one wire bonding manufacturing process is required.

【0027】さらに、青色LED400の下部の側壁4
00b及び底部表面400cを覆っている導電層411
は、ESDの保護経路を提供するのみならず、活性層4
04から発生した光を反射することによって、青色LE
D400の発光効率を向上させる反射ミラーとして機能
する。
Further, the lower side wall 4 of the blue LED 400
00b and conductive layer 411 covering bottom surface 400c
Not only provides an ESD protection path, but also an active layer 4
04 by reflecting the light generated from the blue LE
It functions as a reflection mirror that improves the luminous efficiency of D400.

【0028】(第2の実施の形態)図11〜図13は、
本発明の第2の実施形態における青色LED700の各
製造工程を示す断面図である。図11〜図13におい
て、青色LED700と図4〜図8に示す青色LED4
00と同一の部分には、同一の符号を付すことにより、
説明を省略する。以下、第2の実施形態が第1の実施形
態と異なる部分のみを説明する。
(Second Embodiment) FIGS. 11 to 13 show:
It is sectional drawing which shows each manufacturing process of the blue LED700 in 2nd Embodiment of this invention. 11 to 13, a blue LED 700 and a blue LED 4 shown in FIGS.
By assigning the same reference numerals to the same parts as 00,
Description is omitted. Hereinafter, only the parts of the second embodiment that differ from the first embodiment will be described.

【0029】まず、図11に示すように、図5に示す半
導体構造を形成した後、上部の側壁400aと電気的に
接続しないn型電極708がn型層402の露出表面4
02a上に形成され、n型電極708と電気的に接続し
ないp型電極409がp型層406の表面上に形成され
る。n型電極708とp型電極409は、n型及びp型
GaN系化合物半導体材料とそれぞれn型及びp型オー
ミック接触を形成できる金属で形成される。本実施形態
において、例えば、Ni、Ti、Al、Au、またはそ
れらの合金で形成される。
First, as shown in FIG. 11, after the semiconductor structure shown in FIG. 5 is formed, an n-type electrode 708 which is not electrically connected to the upper side wall 400a is exposed to the exposed surface 4 of the n-type layer 402.
A p-type electrode 409 is formed on the p-type layer 406 and is not electrically connected to the n-type electrode 708. The n-type electrode 708 and the p-type electrode 409 are formed of a metal capable of forming n-type and p-type ohmic contacts with n-type and p-type GaN-based compound semiconductor materials, respectively. In the present embodiment, for example, it is formed of Ni, Ti, Al, Au, or an alloy thereof.

【0030】次に、図12に示すように、青色LED7
00の上層部を覆うPVC弾性巻きシート410が青色
LED700の上部に配置されることによって、n型電
極708、下部の側壁400b、及び底部表面400c
のみを露出させる。
Next, as shown in FIG.
By disposing the elastic PVC sheet 410 covering the upper layer of the blue LED 700 above the blue LED 700, the n-type electrode 708, the lower side wall 400b, and the bottom surface 400c are formed.
Only expose.

【0031】続いて、図13に示すように、青色LED
700のn型電極708、下部の側壁400b及び底部
表面400cを直接に覆うための導電層411が塗布さ
れる。ここで、青色LED700の上層部は、導電層4
11に接触しないように、弾性巻きシート410によっ
て保護される。導電層411例えばAu、Al、Ti、
Cr、またはそれらの合金で形成される。導電層411
が形成された後、弾性巻きシート410を取り除いて青
色LED700の上層部を露出させることにより、本発
明の第2の実施形態による青色LED700が完成され
る。
Subsequently, as shown in FIG.
A conductive layer 411 for directly covering the n-type electrode 708 of 700, the lower side wall 400b, and the bottom surface 400c is applied. Here, the upper layer portion of the blue LED 700 is the conductive layer 4
11 is protected by the elastic rolled sheet 410 so as not to come into contact therewith. The conductive layer 411, for example, Au, Al, Ti,
It is formed of Cr or an alloy thereof. Conductive layer 411
Is formed, the elastic winding sheet 410 is removed to expose the upper layer of the blue LED 700, thereby completing the blue LED 700 according to the second embodiment of the present invention.

【0032】図14は、本発明の第2の実施形態におけ
る青色LED700をカップ形状のリードフレーム10
7及び分離リードフレーム110に接続する方式を示す
断面図である。導電層411がn型電極708と電気的
に接続し、青色LED700の底部表面400cを覆っ
ているため、青色LED700がカップ形状のリードフ
レーム107上に載置されると、n型電極708は導電
層411を介してカップ形状のリードフレーム107の
表面と電気的に接続する。言い換えれば、接続ワイヤー
を使わずにn型電極708とカップ形状のリードフレー
ム107とを電気的に接続することができる。従って、
p型電極409と分離リードフレーム110との間のみ
接続線109を使って電気的に接続する。よって、本発
明の青色LED700は、ワイヤーボンディングの製造
工程を1回で済むため、製造工程を簡素化し、製造コス
トも下げる。
FIG. 14 shows a blue LED 700 according to the second embodiment of the present invention in a cup-shaped lead frame 10.
FIG. 7 is a cross-sectional view illustrating a method of connecting to a separation lead frame 110 and a separation lead frame 110. Since the conductive layer 411 is electrically connected to the n-type electrode 708 and covers the bottom surface 400c of the blue LED 700, when the blue LED 700 is placed on the cup-shaped lead frame 107, the n-type electrode 708 becomes conductive. It is electrically connected to the surface of the cup-shaped lead frame 107 via the layer 411. In other words, the n-type electrode 708 and the cup-shaped lead frame 107 can be electrically connected without using a connection wire. Therefore,
Electrical connection is made only between the p-type electrode 409 and the separation lead frame 110 using the connection line 109. Therefore, the blue LED 700 of the present invention simplifies the manufacturing process and reduces the manufacturing cost because the manufacturing process of the wire bonding only needs to be performed once.

【0033】(第3の実施形態)図15は、本発明の第
3の実施形態における青色LED900を示す断面図で
ある。図15における青色LED900は、図11〜図
13に示す青色LED700と同一の部分には、同一の
符号を付すことにより、説明を省略する。以下、第3の
実施形態が第2の実施形態と異なる部分のみを説明す
る。
(Third Embodiment) FIG. 15 is a sectional view showing a blue LED 900 according to a third embodiment of the present invention. The description of the blue LED 900 in FIG. 15 will be omitted by giving the same reference numerals to the same parts as those of the blue LED 700 shown in FIGS. Hereinafter, only the portions of the third embodiment that differ from the second embodiment will be described.

【0034】青色LED900の製造工程において、L
ED900のn型電極708、下部の側壁400b及び
底部表面400cを覆うための付着層901を導電層4
11形成の前に形成させる工程以外は、全ての工程が図
11〜図13に示す青色LED700の製造工程と同じ
である。付着層901は、絶縁基板401の側壁及び底
部表面が導電層411との粘着性を強化するために設け
られる。付着層901は、Ti、Ni、Al、Cr、P
d、または絶縁基板401の側壁及び底部表面が導電層
411との粘着性を強化できる金属で形成される。
In the manufacturing process of the blue LED 900, L
An adhesion layer 901 for covering the n-type electrode 708 of the ED 900, the lower side wall 400b, and the bottom surface 400c is formed of the conductive layer 4
Except for the step of forming before the formation of 11, all the steps are the same as the manufacturing steps of the blue LED 700 shown in FIGS. The adhesion layer 901 is provided so that the side surfaces and the bottom surface of the insulating substrate 401 can enhance the adhesion with the conductive layer 411. The adhesion layer 901 is made of Ti, Ni, Al, Cr, P
d, or the side wall and the bottom surface of the insulating substrate 401 are formed of a metal capable of enhancing the adhesion to the conductive layer 411.

【0035】(第4の実施形態)図16は、本発明の第
4の実施形態における青色LED1000を示す断面図
である。図16における青色LED1000は、図11
〜図13に示す青色LED700と同一の部分には、同
一の符号を付すことにより、説明を省略する。以下、第
4の実施形態が第2の実施形態と異なる部分のみを説明
する。
(Fourth Embodiment) FIG. 16 is a sectional view showing a blue LED 1000 according to a fourth embodiment of the present invention. The blue LED 1000 in FIG.
13 are denoted by the same reference numerals as in the blue LED 700 shown in FIG. Hereinafter, only the portions of the fourth embodiment that differ from the second embodiment will be described.

【0036】第2の実施形態で説明したように、活性層
404に発生した光は、青色LED700の上層部、即
ちp型層406を通して光を青色LED700の外に射
出する。しかし、第4の実施形態では、活性層404に
発生した光は、青色LED1000の底部、即ち絶縁基
板401から射出する。
As described in the second embodiment, the light generated in the active layer 404 emits light to the outside of the blue LED 700 through the upper layer of the blue LED 700, that is, the p-type layer 406. However, in the fourth embodiment, the light generated in the active layer 404 is emitted from the bottom of the blue LED 1000, that is, from the insulating substrate 401.

【0037】第4の実施形態の青色LED1000を実
現するために、導電層1001を活性層404に発生し
た光を透過できる透光層に形成させる。透光性導電層1
001は、ITO(Indium-tin-oxide)酸化物層、CTO
(Cadmium-tin-oxide)酸化物層、ZnO(Zinc oxide)層
または薄金属層を使用する。前記薄金属層は、厚みが0.
001μmから1μmの範囲内であり、Au、Ni、P
t、Al、Sn、In、Cr、Ti、またはそれらの合
金で形成される。
In order to realize the blue LED 1000 of the fourth embodiment, the conductive layer 1001 is formed as a light transmitting layer that can transmit the light generated in the active layer 404. Translucent conductive layer 1
001 is an ITO (Indium-tin-oxide) oxide layer, CTO
A (Cadmium-tin-oxide) oxide layer, a ZnO (Zinc oxide) layer or a thin metal layer is used. The thin metal layer has a thickness of 0.
Au, Ni, P within the range of 001 μm to 1 μm.
It is formed of t, Al, Sn, In, Cr, Ti, or an alloy thereof.

【0038】さらに、p型層406の全表面を覆うよう
にp型電極1002が形成される。第4の実施形態で
は、青色LED1000の発光効率を上げるために、p
型電極1002が反射ミラーとして活性層404に発生
した光を反射する。
Further, a p-type electrode 1002 is formed so as to cover the entire surface of p-type layer 406. In the fourth embodiment, in order to increase the luminous efficiency of the blue LED 1000, p
The mold electrode 1002 serves as a reflection mirror to reflect light generated on the active layer 404.

【0039】図16に示すように、第4の実施形態の青
色LED1000がカップ形状のリードフレーム107
上に載置されると、青色LED1000の正面が反転し
て下向きになり、p型電極1002をカップ形状のリー
ドフレーム107の表面と電気的に接続する。続いて、
透光性導電層1001は、ボンディングワイヤー109
を介して分離リードフレーム110と電気的に接続す
る。透光性導電層1001とボンディングワイヤー10
9との間のボンディング強度を強化するために、ボンデ
ィングパッド1003を使うのが好ましい。
As shown in FIG. 16, the blue LED 1000 according to the fourth embodiment is a cup-shaped lead frame 107.
When placed on top, the front surface of the blue LED 1000 is inverted and turned downward, and the p-type electrode 1002 is electrically connected to the surface of the cup-shaped lead frame 107. continue,
The light-transmitting conductive layer 1001 includes a bonding wire 109.
Is electrically connected to the separation lead frame 110 via Translucent conductive layer 1001 and bonding wire 10
It is preferable to use a bonding pad 1003 in order to increase the bonding strength between the bonding pad 100 and the bonding pad 9.

【0040】設置の方向が異なるが、第4の実施形態の
青色LED1000は、第2の実施形態と同じように、
ワイヤーボンディングの製造工程を1回で済むため、製
造工程を簡素化し、製造コストも下げる。さらに、青色
LED1000の絶縁基板401の側壁及び底部表面を
覆う透光性導電層1001がESDの保護経路を提供す
る。
Although the installation direction is different, the blue LED 1000 of the fourth embodiment is similar to the second embodiment,
Since only one wire bonding manufacturing process is required, the manufacturing process is simplified and the manufacturing cost is reduced. Further, the light-transmitting conductive layer 1001 covering the side wall and the bottom surface of the insulating substrate 401 of the blue LED 1000 provides an ESD protection path.

【0041】以上の実施形態では、本発明の技術を簡単
に説明するために、提出された具体例であり、本発明を
前記実施形態に限定されることなく、本発明の請求する
範囲で、種々の変更が可能である。
The above embodiment is a specific example submitted for simply explaining the technology of the present invention, and the present invention is not limited to the above embodiment, and is within the scope of the claims of the present invention. Various modifications are possible.

【図面の簡単な説明】[Brief description of the drawings]

【図1】従来の青色LEDを示す断面図である。FIG. 1 is a cross-sectional view illustrating a conventional blue LED.

【図2】図1に示した従来の青色LEDがカップ形状の
リードフレーム上に載置された状態を示す断面図であ
る。
FIG. 2 is a cross-sectional view showing a state in which the conventional blue LED shown in FIG. 1 is mounted on a cup-shaped lead frame.

【図3】図1に示した従来の青色LEDにおける電極の
配置を示す平面図である。
FIG. 3 is a plan view showing an arrangement of electrodes in the conventional blue LED shown in FIG.

【図4】本発明の第1の実施形態における青色LEDの
製造工程を示す断面図である。
FIG. 4 is a sectional view illustrating a manufacturing process of the blue LED according to the first embodiment of the present invention.

【図5】本発明の第1の実施形態における青色LEDの
製造工程を示す断面図である。
FIG. 5 is a cross-sectional view illustrating a manufacturing process of the blue LED according to the first embodiment of the present invention.

【図6】本発明の第1の実施形態における青色LEDの
製造工程を示す断面図である。
FIG. 6 is a cross-sectional view illustrating a manufacturing process of the blue LED according to the first embodiment of the present invention.

【図7】本発明の第1の実施形態における青色LEDの
製造工程を示す断面図である。
FIG. 7 is a cross-sectional view illustrating a manufacturing process of the blue LED according to the first embodiment of the present invention.

【図8】本発明の第1の実施形態における青色LEDの
製造工程を示す断面図である。
FIG. 8 is a cross-sectional view illustrating a manufacturing process of the blue LED according to the first embodiment of the present invention.

【図9】図8に示した青色LEDの電極の配置を示す平
面図である。
FIG. 9 is a plan view showing an arrangement of electrodes of the blue LED shown in FIG.

【図10】図8の青色LEDがカップ形状のリードフレ
ーム上に載置された状態を示す断面図である。
10 is a cross-sectional view showing a state where the blue LED of FIG. 8 is mounted on a cup-shaped lead frame.

【図11】本発明の第2の実施形態における青色LED
の製造工程を示す断面図である。
FIG. 11 shows a blue LED according to a second embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a manufacturing process of the second embodiment.

【図12】本発明の第2の実施形態における青色LED
の製造工程を示す断面図である。
FIG. 12 shows a blue LED according to a second embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a manufacturing process of the second embodiment.

【図13】本発明の第2の実施形態における青色LED
の製造工程を示す断面図である。
FIG. 13 shows a blue LED according to the second embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a manufacturing process of the second embodiment.

【図14】図13の青色LEDがカップ形状のリードフ
レーム上に載置された状態を示す断面図である。
14 is a cross-sectional view showing a state where the blue LED of FIG. 13 is mounted on a cup-shaped lead frame.

【図15】本発明の第3の実施形態における青色LED
がカップ形状のリードフレーム上に載置された状態を示
す断面図である。
FIG. 15 shows a blue LED according to a third embodiment of the present invention.
Is a cross-sectional view showing a state where is mounted on a cup-shaped lead frame.

【図16】本発明の第4の実施形態における青色LED
がカップ形状のリードフレーム上に載置された状態を示
す断面図である。
FIG. 16 shows a blue LED according to a fourth embodiment of the present invention.
Is a cross-sectional view showing a state where is mounted on a cup-shaped lead frame.

【符号の説明】[Explanation of symbols]

101 サファイア基板 102 n型GaN系化合物半導体層 103 活性層 104 p型GaN系化合物半導体層 105 n型電極 106 p型電極 107 カップ形状リードフレーム 108 金属ボンディングワイヤー 109 金属ボンディングワイヤー 110 分離リードフレーム 111 ボンディングパッド 400 青色LED 400a 上部の側壁 400b 下部の側壁 400c 底部表面 401 絶縁基板 402 n型層 402a 露出表面 402b 中央部の表面 403 n型拘束層 404 活性層 405 p型拘束層 406 p型層 407 透光性接触層 409 p型電極 410 弾性巻きシート 411 導電層 700 青色LED 708 p型電極 900 青色LED 901 付着層 1000 青色LED 1001 導電層 1002 p型電極 1003 ボンディングパッド Reference Signs List 101 sapphire substrate 102 n-type GaN-based compound semiconductor layer 103 active layer 104 p-type GaN-based compound semiconductor layer 105 n-type electrode 106 p-type electrode 107 cup-shaped lead frame 108 metal bonding wire 109 metal bonding wire 110 separation lead frame 111 bonding pad 400 Blue LED 400a Upper sidewall 400b Lower sidewall 400c Bottom surface 401 Insulating substrate 402 N-type layer 402a Exposed surface 402b Central surface 403 N-type constraining layer 404 Active layer 405 P-type constraining layer 406 P-type layer 407 Translucency Contact layer 409 P-type electrode 410 Elastic winding sheet 411 Conductive layer 700 Blue LED 708 P-type electrode 900 Blue LED 901 Adhesive layer 1000 Blue LED 1001 Conductive layer 1002 P-type electrode 1 03 bonding pad

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 絶縁基板と、 前記絶縁基板の上部表面に形成され、中央部の表面が周
辺部の表面より高い第1GaN系半導体層と、 前記第1GaN系半導体の中央部の上に形成され、光を
発生する活性層と、 前記活性層上に形成される第2GaN系半導体層と、 前記第2GaN系半導体層上に形成される第1電極と、 前記絶縁基板の側壁及び底部の表面に塗布され、前記第
1GaN系半導体層の側壁と電気的に接続する導電層
と、を備えていることを特徴とする化合物半導体発光素
子。
An insulating substrate; a first GaN-based semiconductor layer formed on an upper surface of the insulating substrate, a surface of a central portion higher than a surface of a peripheral portion; An active layer for generating light, a second GaN-based semiconductor layer formed on the active layer, a first electrode formed on the second GaN-based semiconductor layer, and a surface of a side wall and a bottom of the insulating substrate. A compound semiconductor light-emitting device, comprising: a conductive layer applied and electrically connected to a side wall of the first GaN-based semiconductor layer.
【請求項2】 前記第1GaN系半導体層の周辺部の表
面に形成され、前記活性層、前記第2GaN系半導体層
及び前記第1電極と電気的に接続しないが、前記導電層
と電気的に接続する第2電極、をさらに備えていること
を特徴とする請求項1記載の化合物半導体発光素子。
2. The semiconductor device, which is formed on a surface of a peripheral portion of the first GaN-based semiconductor layer and is not electrically connected to the active layer, the second GaN-based semiconductor layer, and the first electrode, but is electrically connected to the conductive layer. 2. The compound semiconductor light-emitting device according to claim 1, further comprising a second electrode connected thereto.
【請求項3】 前記絶縁基板の側壁及び底部表面と前記
導電層との間に挟まれる付着層と、をさらに備えている
ことを特徴とする請求項1記載の化合物半導体発光素
子。
3. The compound semiconductor light emitting device according to claim 1, further comprising: an adhesion layer sandwiched between the side wall and the bottom surface of the insulating substrate and the conductive layer.
【請求項4】 絶縁基板を提供する工程と、 前記絶縁基板上に第1GaN系半導体を形成する工程
と、 前記第1GaN系半導体層上に光を発生する活性層を形
成する工程と、 前記活性層上に第2GaN系半導体層を形成する工程
と、 前記第2GaN系半導体層、活性層及び第1GaN系半
導体層の周辺部をそれぞれエッチングすることにより、
前記第1GaN系半導体の周辺部の露出表面を中央部の
表面より低くさせる工程と、 前記第2GaN系半導体層上に第1電極を形成する工程
と、 前記絶縁基板の側壁及び底部表面を覆うと共に前記第1
GaN系半導体層と電気的に接続する導電層を塗布する
工程と、 を備えていることを特徴とする化合物半導体発光素子の
製造方法。
Providing an insulating substrate; forming a first GaN-based semiconductor on the insulating substrate; forming an active layer for generating light on the first GaN-based semiconductor layer; Forming a second GaN-based semiconductor layer on the layer; and etching the peripheral portions of the second GaN-based semiconductor layer, the active layer, and the first GaN-based semiconductor layer, respectively.
Making the exposed surface of the peripheral portion of the first GaN-based semiconductor lower than the surface of the central portion; forming a first electrode on the second GaN-based semiconductor layer; covering a side wall and a bottom surface of the insulating substrate; The first
Coating a conductive layer electrically connected to the GaN-based semiconductor layer. A method for manufacturing a compound semiconductor light-emitting device, comprising:
【請求項5】 前記活性層、前記第2GaN系半導体層
及び前記第1電極と電気的に接続しないように、前記第
1GaN系半導体層の周辺部の露出表面上に第2電極を
形成する工程、をさらに備えていることを特徴とする請
求項4記載の化合物半導体発光素子の製造方法。
5. A step of forming a second electrode on an exposed surface at a peripheral portion of the first GaN-based semiconductor layer so as not to be electrically connected to the active layer, the second GaN-based semiconductor layer, and the first electrode. 5. The method for manufacturing a compound semiconductor light emitting device according to claim 4, further comprising:
【請求項6】 前記導電層を塗布する工程の前に、前記
絶縁基板の側壁及び底部の表面上に付着層を形成する工
程を、さらに備えていることを特徴とする請求項4記載
の化合物半導体発光素子の製造方法。
6. The compound according to claim 4, further comprising, before the step of applying the conductive layer, a step of forming an adhesion layer on a side wall and a bottom surface of the insulating substrate. A method for manufacturing a semiconductor light emitting device.
JP2001003249A 2000-09-06 2001-01-11 Compound semiconductor light emitting device and its manufacturing method Pending JP2002094116A (en)

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TW089118295 2000-09-06

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005011857A (en) * 2003-06-17 2005-01-13 Nichia Chem Ind Ltd Nitride semiconductor light emitting device
JP2010123717A (en) * 2008-11-19 2010-06-03 Stanley Electric Co Ltd Semiconductor light emitting element and method for manufacturing it
US20100224858A1 (en) * 2009-03-06 2010-09-09 Advanced Optoelectronic Technology Inc. Lateral thermal dissipation led and fabrication method thereof
JP2011510493A (en) * 2008-01-19 2011-03-31 鶴山麗得電子實業有限公司 LED, package structure with LED, and method of manufacturing LED
JP2019201198A (en) * 2018-05-18 2019-11-21 オプト テック コーポレーション Light-emitting chip and related packaging structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0927639A (en) * 1995-07-12 1997-01-28 Toshiba Corp Semiconductor device
JPH10163530A (en) * 1996-11-27 1998-06-19 Nichia Chem Ind Ltd Nitride semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0927639A (en) * 1995-07-12 1997-01-28 Toshiba Corp Semiconductor device
JPH10163530A (en) * 1996-11-27 1998-06-19 Nichia Chem Ind Ltd Nitride semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005011857A (en) * 2003-06-17 2005-01-13 Nichia Chem Ind Ltd Nitride semiconductor light emitting device
JP2011510493A (en) * 2008-01-19 2011-03-31 鶴山麗得電子實業有限公司 LED, package structure with LED, and method of manufacturing LED
JP2010123717A (en) * 2008-11-19 2010-06-03 Stanley Electric Co Ltd Semiconductor light emitting element and method for manufacturing it
US20100224858A1 (en) * 2009-03-06 2010-09-09 Advanced Optoelectronic Technology Inc. Lateral thermal dissipation led and fabrication method thereof
US8513696B2 (en) * 2009-03-06 2013-08-20 Advanced Optoelectronic Technology, Inc. Lateral thermal dissipation LED and fabrication method thereof
JP2019201198A (en) * 2018-05-18 2019-11-21 オプト テック コーポレーション Light-emitting chip and related packaging structure

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