JP2002026384A - Integrated nitride semiconductor light emitting element - Google Patents
Integrated nitride semiconductor light emitting elementInfo
- Publication number
- JP2002026384A JP2002026384A JP2000203988A JP2000203988A JP2002026384A JP 2002026384 A JP2002026384 A JP 2002026384A JP 2000203988 A JP2000203988 A JP 2000203988A JP 2000203988 A JP2000203988 A JP 2000203988A JP 2002026384 A JP2002026384 A JP 2002026384A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- light emitting
- long side
- ohmic electrode
- emitting device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は窒化物半導体素子、
特に大面積の窒化物半導体発光素子に関する。The present invention relates to a nitride semiconductor device,
In particular, it relates to a large-area nitride semiconductor light emitting device.
【０００２】[0002]
【従来の技術】近年、窒化ガリウム系化合物半導体を用
いて構成された発光素子が、青色発光が可能に発光素子
として種々の用途に使用されるようになってきている。
この窒化ガリウム系化合物半導体を用いて構成された窒
化物半導体発光素子は、通常、サファイア基板の上にｎ
型窒化ガリウム系化合物半導体層、窒化ガリウム系化合
物半導体活性層、ｐ型窒化ガリウム系化合物半導体層が
順次積層され、ｐ側の層及び活性層の一部を除去して露
出させたｎ型窒化ガリウム系化合物半導体層上にｎ側オ
ーミック電極が形成され、ｐ型窒化ガリウム系化合物半
導体層上にｐ側オーミック電極が形成されて構成され
る。2. Description of the Related Art In recent years, light emitting devices formed using gallium nitride-based compound semiconductors have been used for various purposes as light emitting devices capable of emitting blue light.
A nitride semiconductor light emitting device constituted by using this gallium nitride-based compound semiconductor usually has n on a sapphire substrate.
N-type gallium nitride in which a p-type gallium nitride-based compound semiconductor layer, a gallium nitride-based compound semiconductor active layer, and a p-type gallium nitride-based compound semiconductor layer are sequentially stacked, and a p-side layer and a part of the active layer are removed and exposed. An n-side ohmic electrode is formed on the base compound semiconductor layer, and a p-side ohmic electrode is formed on the p-type gallium nitride based compound semiconductor layer.
【０００３】ここで、特に窒化物半導体発光素子では、
ｐ型窒化ガリウム系化合物半導体の抵抗が比較的高いた
めに、ｐ型窒化ガリウム系化合物半導体層のほぼ全面に
ｐ側のオーミック電極を形成することにより活性層全体
に電流が注入されるように構成している。また、窒化物
半導体発光素子では、上述のようにｎ型窒化ガリウム系
化合物半導体層上の一部にｎ側の電極を形成する必要が
あるため、活性層全体に電流が注入されるようにｎ型窒
化ガリウム系化合物半導体層の１つの隅部にｎ側のオー
ミック電極を形成し、その１つの隅部と対角を成すｐ側
オーミック電極の他の隅部にｐ側のパッド電極を形成し
ている。Here, in particular, in a nitride semiconductor light emitting device,
Since the resistance of the p-type gallium nitride-based compound semiconductor is relatively high, a current is injected into the entire active layer by forming a p-side ohmic electrode on almost the entire surface of the p-type gallium nitride-based compound semiconductor layer. are doing. Further, in the nitride semiconductor light emitting device, as described above, it is necessary to form an n-side electrode on a part of the n-type gallium nitride-based compound semiconductor layer. Forming an n-side ohmic electrode at one corner of the p-type gallium nitride-based compound semiconductor layer, and forming a p-side pad electrode at the other corner of the p-side ohmic electrode which is diagonal to the one corner. ing.
【０００４】すなわち、窒化物半導体発光素子では、絶
縁性のサファイア基板を用いて構成されていること、及
びｐ型窒化ガリウム系化合物半導体の抵抗値が比較的大
きいという、例えば、ＧａＡｓ系等の他の発光素子とは
異なる事情があるために、ｐ側オーミック電極をｐ型窒
化ガリウム系半導体層のほぼ全面に設けかつｎ側のオー
ミック電極とｐ側のパッド電極を対角を成す位置に形成
するという独特の構成により、活性層全体に電流が注入
されるようにしている。That is, the nitride semiconductor light emitting device is formed using an insulating sapphire substrate, and the p-type gallium nitride based compound semiconductor has a relatively large resistance value. Since there is a situation different from that of the light emitting element, the p-side ohmic electrode is provided on almost the entire surface of the p-type gallium nitride based semiconductor layer, and the n-side ohmic electrode and the p-side pad electrode are formed at diagonal positions. Current is injected into the entire active layer.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上述の
構成（電極構成）は、１つの発光素子チップが、例え
ば、３００μｍ×３００μｍ以下の大きさである場合に
は活性層にほぼ均一に電流を注入することができるが、
３００μｍ×３００μｍを越える大きさになると活性層
に注入される電流が不均一になるという問題点があり、
上記構成を相似形で大きくすることによって大面積の発
光素子を構成することはできなかった。そこで、大面積
の窒化物半導体発光素子は、１つの基板上に、３００μ
ｍ×３００μｍ程度の発光素子を線形又はアレイ状に複
数個配列することにより構成していた。しかしながら、
発光素子を複数個配列してなる大面積の窒化物半導体発
光素子は、隣接する発光素子間に、素子間を電気的に分
離するための溝を形成する必要があるために格子状に非
発光部分が形成され、発光効率を向上させることが困難
であるという問題点があった。However, in the above-described configuration (electrode configuration), when one light-emitting element chip has a size of, for example, 300 μm × 300 μm or less, current is almost uniformly injected into the active layer. Can be
If the size exceeds 300 μm × 300 μm, there is a problem that the current injected into the active layer becomes non-uniform,
It was not possible to construct a large-area light emitting element by increasing the above configuration in a similar manner. Therefore, a large-area nitride semiconductor light emitting device can be formed on one substrate by 300 μm.
It was configured by arranging a plurality of light emitting elements of about m × 300 μm in a linear or array. However,
A large-area nitride semiconductor light-emitting element in which a plurality of light-emitting elements are arranged does not emit light in a grid pattern because it is necessary to form a groove between adjacent light-emitting elements to electrically separate the elements. There is a problem that a portion is formed and it is difficult to improve luminous efficiency.
【０００６】そこで、本発明は、大面積でかつ発光効率
の良い集積型窒化物半導体発光素子を提供することを目
的とする。Accordingly, an object of the present invention is to provide an integrated nitride semiconductor light emitting device having a large area and high luminous efficiency.
【０００７】[0007]
【課題を解決するための手段】以上の目的を達成するた
めに、本発明に係る集積型窒化物半導体発光素子は、基
板上に複数の発光素子が並置されてなり、上記発光素子
はそれぞれ、上記基板上に形成されたｎ型窒化ガリウム
系化合物半導体層が分離溝によって分離されてなる長方
形のｎ層と、長方形のｐ型窒化ガリウム系化合物半導体
が、その一方の長辺と２つの短辺とがそれぞれ上記ｎ層
の一方の長辺と２つの短辺と近接するように上記ｎ層上
に設けられて成るｐ層と、上記各ｎ層の他方の長辺と上
記ｐ層の他方の長辺との間のｎ層上に設けられ、上記ｐ
層の長辺と実質的に同一の長さを有するｎ側オーミック
電極と、上記ｐ層上のほぼ全面に形成されたｐオーミッ
ク電極と、上記ｐオーミック電極上に、上記ｐ層の一方
の長辺に沿って設けられたｐパッド電極とを備え、上記
ｐ層の一方の長辺と上記ｎ側オーミック電極との間隔を
２５０μｍ以下に設定したことを特徴とする。In order to achieve the above object, an integrated nitride semiconductor light emitting device according to the present invention comprises a plurality of light emitting devices juxtaposed on a substrate. A rectangular n-layer in which the n-type gallium nitride-based compound semiconductor layer formed on the substrate is separated by a separation groove and a rectangular p-type gallium nitride-based compound semiconductor have one long side and two short sides. Are provided on the n layer so as to be close to one long side and two short sides of the n layer, respectively, the other long side of each n layer and the other of the p layer Provided on the n layer between the long side and
An n-side ohmic electrode having substantially the same length as the long side of the layer; a p-ohmic electrode formed over substantially the entire surface of the p-layer; A p pad electrode provided along the side, and a distance between one long side of the p layer and the n-side ohmic electrode is set to 250 μm or less.
【０００８】以上のように構成された本発明に係る集積
型窒化物半導体発光素子は、上記ｐ層の一方の長辺と上
記ｎ側オーミック電極との間隔を２５０μｍ以下に設定
しているので、各発光素子の活性層全体にほぼ均一に電
流を注入することができ、均一に発光させることができ
るので、各発光素子における発光効率を良好にできる。
また、本発明に係る集積型窒化物半導体発光素子におい
ては、均一発光及び発光効率を劣化させることなく、各
発光素子を一方向（長手方向）に十分長くすることがで
きるので、発光面積を大きくできかつ発光効率を高くで
きる。In the integrated nitride semiconductor light emitting device according to the present invention having the above-described structure, the distance between one long side of the p layer and the n-side ohmic electrode is set to 250 μm or less. A current can be almost uniformly injected into the entire active layer of each light emitting element, and light can be emitted uniformly, so that the light emitting efficiency of each light emitting element can be improved.
Further, in the integrated nitride semiconductor light emitting device according to the present invention, each light emitting device can be made sufficiently long in one direction (longitudinal direction) without deteriorating uniform light emission and light emission efficiency. And the luminous efficiency can be increased.
【０００９】また、本発明に係る集積型窒化物半導体発
光素子では、各発光素子においてより均一な発光を可能
にしかつより発光効率を高くするために、上記ｐ層の一
方の長辺と上記ｎ側オーミック電極との間隔を２２０μ
ｍ以下に設定することがさらに好ましい。In the integrated nitride semiconductor light emitting device according to the present invention, one long side of the p-layer and n 220μ spacing from the side ohmic electrode
m is more preferably set to m or less.
【００１０】また、本発明に係る集積型窒化物半導体発
光素子では、上記複数の発光素子を直列に接続するよう
に構成してもよい。In the integrated nitride semiconductor light emitting device according to the present invention, the plurality of light emitting devices may be connected in series.
【００１１】また、本発明に係る集積型窒化物半導体発
光素子では、上記複数の発光素子を並列に接続するよう
に構成してもよい。In the integrated nitride semiconductor light emitting device according to the present invention, the plurality of light emitting devices may be connected in parallel.
【００１２】さらに、上記基板として透光性を有する基
板を用い、上記各発光素子で発光された光を上記基板を
介して出力するように構成してもよい。Further, a light-transmitting substrate may be used as the substrate, and light emitted by each of the light-emitting elements may be output through the substrate.
【００１３】また、本発明に係る集積型窒化物半導体発
光素子では、上記ｎ層を複数の窒化ガリウム系半導体層
で構成し、その複数の窒化ガリウム系半導体層のうちの
少なくとも１つが５．５〜７．２×１０−３Ωｃｍの抵
抗率と膜厚２μｍ以上のｎ型層であることが好ましい。In the integrated nitride semiconductor light emitting device according to the present invention, the n-layer is composed of a plurality of gallium nitride based semiconductor layers, and at least one of the plurality of gallium nitride based semiconductor layers is 5.5. An n-type layer having a resistivity of about 7.2 × 10 −3 Ωcm and a film thickness of 2 μm or more is preferable.
【００１４】[0014]
【発明の実施の形態】以下、図面を参照しながら本発明
に係る実施の形態の集積型窒化物半導体発光素子につい
て説明する。 実施の形態１．本実施の形態１の集積型窒化物半導体発
光素子は、図１に示すように、例えば、１０００μｍ×
１０００μｍのサファイア基板１１上に長方形の３つの
発光素子１，２，３を互いに平行に配置しかつ、各発光
素子の幅をある一定の値以下に設定することにより各素
子の活性層にそれぞれ均一に電流が流れるようにして、
全体としての発光効率を向上させたことを特徴としてい
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an integrated nitride semiconductor light emitting device according to an embodiment of the present invention will be described with reference to the drawings. Embodiment 1 FIG. As shown in FIG. 1, the integrated nitride semiconductor light emitting device of the first embodiment has, for example, 1000 μm ×
By arranging three rectangular light emitting elements 1, 2 and 3 in parallel on a 1000 μm sapphire substrate 11 and setting the width of each light emitting element to a certain value or less, the active layer of each element is uniformly formed. So that the current flows through
It is characterized by improving the luminous efficiency as a whole.
【００１５】本実施の形態１の集積型窒化物半導体素子
は、窒化ガリウム系化合物半導体の特有の構成におい
て、本発明者らにより見出された次のような知見に基づ
いてなされたものである。すなわち、窒化ガリウム系化
合物半導体を用いて構成された発光素子は、従来技術の
欄において説明したように、ｎ層上の一部にｎ側オーミ
ック電極を形成し、そのｎ側オーミック電極に近接して
ｎ層上に活性層を介してｐ層を形成し、さらにそのｐ層
の上のほぼ全面にｐ側オーミック電極を形成するという
独特の構造を有する。このような独特の構成において
は、ｎ側オーミック電極から２５０μｍ以内の距離にあ
る活性層に注入される電流はほぼ一定であるが、２５０
μｍ以上離れると急激に減少する。実際には２２０μｍ
より離れると活性層に注入される電流は徐徐に減少しは
じめるが、２５０μｍまでは電流値は実質的に一定とみ
なすことができる。また、この現象（活性層が２５０μ
ｍ以上離れると注入される電流が急激に減少するという
現象）は、ｎ層の抵抗値に起因して生じると考えられる
が、通常、用いられるｎ層の抵抗値の範囲においては、
変わらないことが確認されている。The integrated nitride semiconductor device according to the first embodiment is based on the following findings discovered by the present inventors in a specific configuration of a gallium nitride-based compound semiconductor. . That is, a light-emitting element formed using a gallium nitride-based compound semiconductor has an n-side ohmic electrode formed on a part of the n-layer and is close to the n-side ohmic electrode as described in the section of the prior art. Thus, a p-layer is formed on the n-layer via an active layer, and a p-side ohmic electrode is formed on almost the entire surface of the p-layer. In such a unique configuration, the current injected into the active layer within a distance of 250 μm or less from the n-side ohmic electrode is substantially constant.
When the distance is more than μm, it decreases rapidly. Actually 220 μm
As the distance increases, the current injected into the active layer starts to decrease gradually, but the current value can be regarded as substantially constant up to 250 μm. In addition, this phenomenon (when the active layer is 250 μm)
is considered to be caused by the resistance value of the n-layer, but usually, in the range of the resistance value of the n-layer used,
It has been confirmed that it has not changed.
【００１６】上述の知見から次のことが言える。ｎ型窒
化ガリウム系化合物半導体層の上に、一方向に長い長方
形の活性層及びｐ型窒化ガリウム系化合物半導体層を形
成した場合であっても、ｎ側オーミック電極からの距離
を２５０μｍ以内とすれば、活性層全体にほぼ均一に電
流を注入することができる。具体的には、長方形の活性
層及びｐ型窒化ガリウム系化合物半導体層の１つの長辺
に沿って活性層及びｐ型窒化ガリウム系化合物半導体層
と同じ長さのｎ側オーミック電極を形成し、そのｎ側オ
ーミック電極と活性層及びｐ型窒化ガリウム系化合物半
導体層の他の長辺との間の距離を２５０μｍ以下、より
好ましくは２２０μｍ以下にすれば、活性層にほぼ均一
に電流を注入することができる。本実施の形態１の集積
型窒化物半導体発光素子は、上述の考えに基いて構成さ
れたものである。The following can be said from the above findings. Even when a rectangular active layer and a p-type gallium nitride-based compound semiconductor layer that are long in one direction are formed on the n-type gallium nitride-based compound semiconductor layer, the distance from the n-side ohmic electrode is within 250 μm. If this is the case, the current can be injected almost uniformly over the entire active layer. Specifically, an n-side ohmic electrode having the same length as the active layer and the p-type gallium nitride-based compound semiconductor layer is formed along one long side of the rectangular active layer and the p-type gallium nitride-based compound semiconductor layer, When the distance between the n-side ohmic electrode and the other long side of the active layer and the p-type gallium nitride-based compound semiconductor layer is 250 μm or less, more preferably 220 μm or less, current is injected almost uniformly into the active layer. be able to. The integrated nitride semiconductor light emitting device according to the first embodiment is configured based on the above-described concept.
【００１７】詳細に説明すると、実施の形態１の集積型
窒化物半導体発光素子の発光素子１，２，３において、
各半導体層及び電極はそれぞれ以下のように形成され
る。 （１）ｎ型窒化ガリウム系化合物半導体層１２（ｎ層１
２）は、例えば、サファイアからなる基板１１上のほぼ
全面に成長されたｎ型窒化ガリウム系化合物半導体層が
分離溝４１により分離されて、平面形状が長方形になる
ように形成される。ここで、本実施の形態１において、
ｎ型窒化ガリウム系化合物半導体層１２（ｎ層１２）
は、好ましくは、図４に示すように、サファイア基板１
１上に形成された膜厚１．５μｍのアンドープＧａＮ層
１２１、膜厚２．２μｍのＳｉドープＧａＮ層１２２、
膜厚３０００ÅのアンドープＧａＮ層１２３、膜厚３０
０ÅのＳｉドープＧａＮ層１２４、膜厚５０Åのアンド
ープＧａＮ層１２５、多層膜層１２６の積層構造とす
る。このようにｎ層１２を上記積層構造とすることによ
り、順方向電圧Ｖｆを低くできかつ発光効率を良くでき
る。尚、多層膜層１２６は、好ましくは、アンドープＧ
ａＮよりなり膜厚４０Åの第１の層と、アンドープＩｎ
０．１３Ｇａ０．８７Ｎよりなり膜厚２０Åの第２の層
を交互にそれぞれ１０層になるように積層することによ
り構成する。More specifically, in the light emitting devices 1, 2, and 3 of the integrated nitride semiconductor light emitting device of the first embodiment,
Each semiconductor layer and each electrode are formed as follows. (1) n-type gallium nitride-based compound semiconductor layer 12 (n-layer 1
In the case of 2), for example, the n-type gallium nitride-based compound semiconductor layer grown on almost the entire surface of the substrate 11 made of sapphire is separated by the separation groove 41 so that the planar shape becomes rectangular. Here, in the first embodiment,
n-type gallium nitride-based compound semiconductor layer 12 (n-layer 12)
Is preferably a sapphire substrate 1 as shown in FIG.
1, an undoped GaN layer 121 having a thickness of 1.5 μm, a Si-doped GaN layer 122 having a thickness of 2.2 μm,
Undoped GaN layer 123 of thickness 3000 °, thickness of 30
A laminated structure of a 0 ° Si-doped GaN layer 124, an undoped GaN layer 125 with a thickness of 50 °, and a multilayer film layer 126 is adopted. By thus forming the n-layer 12 with the above-described laminated structure, the forward voltage Vf can be reduced and the luminous efficiency can be improved. The multilayer film 126 is preferably made of undoped G
a first layer made of aN and having a thickness of 40 °;
It is constituted by alternately laminating the second layers of 0.13Ga0.87N and having a film thickness of 20 ° so as to have 10 layers each.
【００１８】また、本実施の形態１の積層構造のｎ層１
２全体としての抵抗率は、実質的には膜厚２．２μｍの
ＳｉドープＧａＮ層１２２により決まり、本実施の形態
１においてはこの層１２２の抵抗率を５．５〜７．２×
１０-3Ωｃｍの範囲でかつ膜厚が２．０μｍ以上に設定
することが好ましく、このようにすると発光層１０全体
により均一に電流を注入することができ、より均一な発
光が得られる。尚、ＧａＮ層において、３×１０18〜６
×１０18ｃｍ-3の範囲でＳｉをドープすることにより、
抵抗率が５．５〜７．２×１０-3Ωｃｍの範囲のＳｉド
ープＧａＮ膜を構成できる。The n-layer 1 of the laminated structure of the first embodiment
2 as a whole is substantially determined by the Si-doped GaN layer 122 having a thickness of 2.2 μm, and in the first embodiment, the resistivity of this layer 122 is set to 5.5 to 7.2 ×
It is preferable to set the thickness within the range of 10 −3 Ωcm and the thickness of 2.0 μm or more. In this case, the current can be more uniformly injected into the entire light emitting layer 10 and more uniform light emission can be obtained. In the GaN layer, 3 × 10 18 to 6
By doping Si in a range of × 10 18 cm -3 ,
A Si-doped GaN film having a resistivity in the range of 5.5 to 7.2 × 10 −3 Ωcm can be formed.
【００１９】（２）活性層１０は、ｎ層１２とほぼ同一
の長さとｎ層１２より狭い幅を有する長方形であって、
その１つの長辺がｎ層１２の１つの長辺に実質的に一致
するようにｎ層１２上に形成される。このように形成す
ることにより、ｎ層１２上に活性層１０に沿ってｎ側オ
ーミック電極を形成するための領域が確保される。ここ
で、本実施の形態１では、活性層１０の幅は、ｎ側オー
ミック電極から離れた側に位置する長辺とｎ側オーミッ
ク電極との距離Ｌ１，Ｌ２，Ｌ３が２２０μｍになるよ
うに設定した。また、本実施の形態１において、活性層
１０はＧａＮの一部をＩｎで置き換えたＩｎxＧａ1-xＮ
層により構成することができる。また、活性層１０は、
ＩｎxＧａ1-xＮ層を少なくとも１層含むように構成する
こともできる。このようにすると、ＩｎxＧａ1-xＮ層に
おけるＩｎの含有量を変化させることにより発光波長を
変えることができる。(2) The active layer 10 is a rectangle having substantially the same length as the n-layer 12 and a width smaller than that of the n-layer 12,
The long side is formed on n layer 12 such that one long side substantially coincides with one long side of n layer 12. By forming in this manner, a region for forming an n-side ohmic electrode on the n-layer 12 along the active layer 10 is secured. Here, in the first embodiment, the width of the active layer 10 is set such that the distances L1, L2, and L3 between the long sides located on the side remote from the n-side ohmic electrode and the n-side ohmic electrode are 220 μm. did. In the first embodiment, the active layer 10 is formed of In x Ga 1 -xN in which a part of GaN is replaced by In.
It can be composed of layers. Further, the active layer 10
It may be configured to include at least one In x Ga 1 -xN layer. In this case, the emission wavelength can be changed by changing the In content in the In x Ga 1 -xN layer.
【００２０】（３）ｎ側オーミック電極１４（１４ａ）
は、活性層１０とほぼ同一の長さを有し、ｎ層１２上
に、活性層１０に沿ってかつ活性層１０と近接して形成
される。このｎ側オーミック電極１４と活性層１０との
間の間隔は、製造上の制約により１０〜２０μｍに設定
されるが、本発明においては間隔を１０μｍ以下にする
ことが好ましく、このようにすると、均一に電流を注入
することができる幅を大きくすることができる。すなわ
ち、ｎ側オーミック電極１４と活性層１０との間隔を２
０μｍにすると、均一に電流を注入することができる活
性層の幅は最大で２００μｍであるが、ｎ側オーミック
電極１４と活性層１０との間隔を５μｍにすると、均一
に電流を注入することができる活性層の幅は最大で２１
５μｍにできる。また、ｎ側オーミック電極１４（１４
ａ）は、ｎ層１２とのオーミック接触を良好にするため
に、ＷとＡｌを含む層とすることが好ましく、さらに好
ましくは、Ｗ層（２００Å）、Ａｌ層（１０００Å）、
Ｗ層（５００Å）、Ｐｔ層（３０００Å）、Ｎｉ層（６
０Å）を順次積層することにより形成する。(3) n-side ohmic electrode 14 (14a)
Has substantially the same length as the active layer 10 and is formed on the n-layer 12 along the active layer 10 and in proximity to the active layer 10. The distance between the n-side ohmic electrode 14 and the active layer 10 is set to 10 to 20 μm due to manufacturing restrictions. In the present invention, the distance is preferably set to 10 μm or less. The width over which current can be injected uniformly can be increased. That is, the distance between the n-side ohmic electrode 14 and the active layer 10 is set to 2
When the width is 0 μm, the width of the active layer that can uniformly inject current is 200 μm at the maximum. However, when the distance between the n-side ohmic electrode 14 and the active layer 10 is 5 μm, the current can be injected uniformly. The maximum width of the active layer is 21
It can be 5 μm. Further, the n-side ohmic electrode 14 (14
a) is preferably a layer containing W and Al in order to improve the ohmic contact with the n-layer 12, more preferably a W layer (200 °), an Al layer (1000 °),
W layer (500 °), Pt layer (3000 °), Ni layer (6
0 °) are sequentially laminated.
【００２１】（４）ｐ型窒化ガリウム系半導体層１３
は、活性層１０と同一平面形状を有し活性層１０上に重
ねて形成される。実際には、活性層１０及びｐ型窒化ガ
リウム系半導体層１３は、ｎ層１２上に活性層１０及び
ｐ層１３を重ねて形成した後、ｎ側オーミック電極１４
を形成するｎ層１２表面を露出させるために一括してエ
ッチングすることにより形成する。尚、本実施の形態１
では、ｐ型窒化ガリウム系半導体層１３は１５００Åの
厚さに形成した。(4) P-type gallium nitride based semiconductor layer 13
Has the same planar shape as the active layer 10, and is formed on the active layer 10. Actually, the active layer 10 and the p-type gallium nitride based semiconductor layer 13 are formed by superposing the active layer 10 and the p-layer 13 on the n-layer 12 and then forming the n-side ohmic electrode 14.
Is formed by etching all at once in order to expose the surface of the n-layer 12 for forming. The first embodiment
Then, the p-type gallium nitride based semiconductor layer 13 was formed to a thickness of 1500 °.
【００２２】（５）ｐ側オーミック電極１５は、ｐ型窒
化ガリウム系半導体層１３上のほぼ全面に形成され、ｐ
層１３と良好なオーミック接触を得るために、Ｎｉ層と
Ｐｔ層とを積層することにより構成することが好まし
く、より好ましくは、Ｎｉ層１００ÅとＰｔ層５００Å
を積層することにより構成する(5) The p-side ohmic electrode 15 is formed on almost the entire surface of the p-type gallium nitride-based semiconductor layer 13.
In order to obtain good ohmic contact with the layer 13, it is preferable that the Ni layer and the Pt layer are stacked, and more preferably, the Ni layer and the Pt layer are stacked.
By stacking
【００２３】（６）そして、ｐパッド電極１６（１６
ａ）は、例えば、膜厚３０００ÅのＰｔからなり、ｐ側
オーミック電極１５上において、ｎ側オーミック電極１
４とは離れた側に位置するｐ側オーミック電極１５の長
辺に沿って形成される。(6) Then, the p pad electrode 16 (16
a) is composed of, for example, Pt having a film thickness of 3000 ° and is formed on the p-side ohmic electrode 15 on the n-side ohmic electrode 1.
4 is formed along the long side of the p-side ohmic electrode 15 located on the side distant from 4.
【００２４】さらに、本実施の形態１の集積型窒化物半
導体発光素子において、上述のように構成された発光素
子１，２，３は、絶縁保護膜１７により素子間が分離さ
れ、接続電極２１により以下のように接続される。絶縁
保護膜１７は、各発光素子のｐパッド電極１６（１６
ａ）上及びｎ側オーミック電極１４（１４ａ）上を除い
て素子全体を覆うように形成される。接続電極２１は、
発光素子１のｎ側オーミック電極１４ａ上、分離溝４１
に形成された絶縁膜１７上及び発光素子２のｐ側オーミ
ック電極１６ａ上に連続して間の形成され、これによ
り、発光素子１のｎ側オーミック電極１４ａと発光素子
２のｐ側オーミック電極１６ａが接続される。また、接
続電極２１は、発光素子２と発光素子３との間において
も同様に形成され、これにより、発光素子２のｎ側オー
ミック電極１４ａと発光素子３のｐ側オーミック電極１
６ａが接続される。接続電極２１は、Ｐｔ又はＡｕ等、
種々の金属で構成することができるが、ｐ及びｎパッド
電極との密着性を良好にするために、Ｔｉ（例えば、４
００Å）、Ｐｔ（例えば、６０００Å）、Ａｕ（例え
ば、１０００Å）、Ｎｉ（例えば、６０Å）を順に積層
した構造とすることが好ましい。Further, in the integrated nitride semiconductor light emitting device according to the first embodiment, the light emitting devices 1, 2, and 3 configured as described above are separated from each other by the insulating protective film 17, and the connection electrodes 21 are formed. Are connected as follows. The insulating protective film 17 serves as a p-pad electrode 16 (16
a) It is formed so as to cover the entire device except on the upper side and the n-side ohmic electrode 14 (14a). The connection electrode 21
On the n-side ohmic electrode 14a of the light emitting element 1, the separation groove 41
Is continuously formed on the insulating film 17 formed on the p-side ohmic electrode 16a of the light-emitting element 2 and the n-side ohmic electrode 14a of the light-emitting element 1 and the p-side ohmic electrode 16a of the light-emitting element 2. Is connected. The connection electrode 21 is similarly formed between the light emitting element 2 and the light emitting element 3, whereby the n-side ohmic electrode 14 a of the light emitting element 2 and the p-side ohmic electrode 1
6a is connected. The connection electrode 21 is made of Pt, Au, or the like.
Although it can be made of various metals, in order to improve the adhesion to the p and n pad electrodes, Ti (for example, 4
00 °), Pt (eg, 6000 °), Au (eg, 1000 °), and Ni (eg, 60 °) are preferably stacked in this order.
【００２５】尚、本実施の形態１ではさらに、発光素子
１のｐパッド電極１６上に接続電極２１と同様の材料か
らなる外部接続用電極２６が形成され、発光素子３のｎ
パッド電極１４上に接続電極２１と同様の材料からなる
外部接続用電極２４が形成される。In the first embodiment, an external connection electrode 26 made of the same material as the connection electrode 21 is further formed on the p pad electrode 16 of the light emitting element 1,
An external connection electrode 24 made of the same material as the connection electrode 21 is formed on the pad electrode 14.
【００２６】以上のように構成された実施の形態１の集
積型窒化物半導体発光素子の各発光素子１，２，３にお
いて、活性層１０を長方形に形成し、活性層１０の一方
の長辺に沿って近接するようにｎ側オーミック電極を形
成し、活性層１０の他方の長辺とｎ側オーミック電極と
の距離Ｌ１，Ｌ２，Ｌ３を２２０μｍに設定しているの
で、活性層１０全体に略均一に電流を注入することがで
きる。このように構成したことにより、本実施の形態１
の集積型窒化物半導体素子は、各発光素子１，２，３の
活性層１０全体に渡って均一に発光させることができる
ので、各発光素子における発光効率を高くすることがで
き、全体としての発光効率をよくできる。In each of the light emitting devices 1, 2, 3 of the integrated nitride semiconductor light emitting device of the first embodiment configured as described above, the active layer 10 is formed in a rectangular shape, and one long side of the active layer 10 is formed. The n-side ohmic electrode is formed so as to be close to along, and the distances L1, L2, and L3 between the other long side of the active layer 10 and the n-side ohmic electrode are set to 220 μm. The current can be injected substantially uniformly. With this configuration, the first embodiment
Can emit light uniformly over the entire active layer 10 of each of the light emitting elements 1, 2, and 3, so that the light emitting efficiency of each light emitting element can be increased, and Luminous efficiency can be improved.
【００２７】また、本実施の形態１の集積型窒化物半導
体素子においては、一方向のみに互いに平行な分離溝４
１を形成することにより各素子を分離しているので、格
子状に溝を形成して各素子を分離した従来例に比較し
て、基板１１全体の面積に対する分離溝４１の占める面
積の割合を少なくすることができる。これにより、集積
型窒化物半導体素子の全体の面積に対する活性層１０が
占める面積（発光素子１，２，３の活性層１０を合計し
た面積）の割合を増加させることができ、発光効率を向
上させることができる。In the integrated nitride semiconductor device according to the first embodiment, the separation grooves 4 parallel to each other only in one direction.
1, the respective elements are separated from each other, so that the ratio of the area occupied by the separation grooves 41 to the entire area of the substrate 11 is smaller than that in the conventional example in which the grooves are formed in a lattice shape and the respective elements are separated. Can be reduced. Thereby, the ratio of the area occupied by the active layer 10 (the total area of the active layers 10 of the light emitting elements 1, 2, and 3) to the entire area of the integrated nitride semiconductor element can be increased, and the luminous efficiency is improved. Can be done.
【００２８】実施の形態１の変形例．本変形例の集積型
窒化物半導体発光素子は、素子の静電耐圧特性を良くす
るために、ＳｉドープＧａＮ層１２２を４．２μｍにな
るように形成し、かつｐ層１３を３５００Åの厚さにな
るように形成した以外は、実施の形態１と同様に構成さ
れる。以上のように構成された変形例の集積型窒化物半
導体発光素子は、実施の形態１と同様、活性層１０全体
に均一に電流を注入することができ、均一でかつ発光効
率の良好な素子とできる。また、本変形例の集積型窒化
物半導体発光素子は、ＳｉドープＧａＮ層１２２及びｐ
層１３をそれぞれ実施の形態１に比較して厚くしている
ので、実施の形態１の素子に比較して静電耐圧を向上さ
せることができる。Modification of Embodiment 1 In the integrated nitride semiconductor light emitting device of the present modification, in order to improve the electrostatic withstand voltage characteristics of the device, the Si-doped GaN layer 122 is formed to have a thickness of 4.2 μm, and the p-layer 13 has a thickness of 3500 °. The configuration is the same as that of the first embodiment, except that it is formed so that The integrated nitride semiconductor light emitting device of the modified example configured as described above is capable of uniformly injecting a current into the entire active layer 10 as in the first embodiment, and is a device having uniform and good luminous efficiency. And can be. Further, the integrated nitride semiconductor light emitting device of the present modified example has the Si doped GaN layer 122 and the p-type
Since the thickness of each of the layers 13 is larger than that of the first embodiment, the electrostatic breakdown voltage can be improved as compared with the element of the first embodiment.
【００２９】実施の形態２．次に、本発明に係る実施の
形態２の集積型窒化物半導体発光素子について、図５を
参照しながら説明する。本実施の形態２の集積型窒化物
半導体発光素子は、以下の点で実施の形態１の集積型窒
化物半導体発光素子と異なる。 相違点１．実施の形態１の集積型窒化物半導体発光素子
において、接続電極２１及び外部接続電極２４，２６を
形成することなく、素子全体を覆うように絶縁保護膜３
０を形成し、発光素子１，２，３のｐパッド電極上にそ
れぞれ絶縁保護膜３０を貫通するスルーホール６１を形
成し、発光素子１，２，３の各ｎ側オーミック電極上に
それぞれ絶縁保護膜３０を貫通するスルーホール６２を
形成する。Embodiment 2 Next, an integrated nitride semiconductor light emitting device according to a second embodiment of the present invention will be described with reference to FIG. The integrated nitride semiconductor light emitting device of the second embodiment differs from the integrated nitride semiconductor light emitting device of the first embodiment in the following points. Difference 1. In the integrated nitride semiconductor light emitting device of the first embodiment, the insulating protection film 3 is formed so as to cover the entire device without forming the connection electrode 21 and the external connection electrodes 24 and 26.
0 is formed, and through holes 61 are formed on the p-pad electrodes of the light emitting elements 1, 2, 3 through the insulating protective film 30, respectively, and the insulating holes are formed on the n-side ohmic electrodes of the light emitting elements 1, 2, 3 respectively. A through hole 62 penetrating through the protective film 30 is formed.
【００３０】相違点２．絶縁保護膜３０に形成されたス
ルーホール６１を介して、発光素子１，２，３のｐパッ
ド電極間を互いに接続電極５１で接続する。 相違点３．絶縁保護膜３０に形成されたスルーホール６
２を介して、発光素子１，２，３のｎ側オーミック電極
間を互いに接続電極５２で接続する。以上の相違点１，
２，３以外は、実施の形態１の集積型窒化物半導体発光
素子と同様に構成する。すなわち、実施の形態２の集積
型窒化物半導体発光素子は、実施の形態１の素子におい
て発光素子１，２，３を並列に接続したものである。以
上のように構成された実施の形態２の集積型窒化物半導
体発光素子は、実施の形態１と同様、発光効率を向上さ
せることができる。Difference 2. The connection electrodes 51 connect the p pad electrodes of the light emitting elements 1, 2, and 3 to each other via the through holes 61 formed in the insulating protection film 30. Difference 3. Through hole 6 formed in insulating protection film 30
The n-side ohmic electrodes of the light emitting elements 1, 2 and 3 are connected to each other via the connection electrode 52 through the connection electrode 52. Difference 1 above
Except for 2 and 3, the configuration is the same as that of the integrated nitride semiconductor light emitting device of the first embodiment. That is, the integrated nitride semiconductor light emitting device of the second embodiment is obtained by connecting the light emitting devices 1, 2, and 3 in parallel with the device of the first embodiment. The integrated nitride semiconductor light-emitting device according to the second embodiment configured as described above can improve the luminous efficiency similarly to the first embodiment.
【００３１】以上の実施の形態１，２では、発光素子が
３つの場合について説明したが、本発明はこれに限られ
るものではなく、２つの発光素子を用いて構成した物で
あっても良いし、３以上の発光素子で構成したものであ
ってもよい。In Embodiments 1 and 2 described above, the case where three light emitting elements are used has been described. However, the present invention is not limited to this, and may be configured using two light emitting elements. Alternatively, the light emitting element may be formed of three or more light emitting elements.
【００３２】また、実施の形態１，２では、最も好まし
い例として、活性層１０（ｐ層１３）の外側の長辺とｎ
側オーミック電極との距離Ｌ１，Ｌ２，Ｌ３を２２０μ
ｍに設定した場合について説明したが、本発明はこれに
限られるものではなく、２５０μｍ以下、好ましくは２
２０μｍ以下に設定すればよい。In the first and second embodiments, as the most preferable example, the long side outside the active layer 10 (p layer 13) and n
The distance L1, L2, L3 from the side ohmic electrode is 220μ.
Although the description has been given of the case where m is set to m, the present invention is not limited to this.
It may be set to 20 μm or less.
【００３３】[0033]
【実施例】以下、本発明に係る実施例を示す。尚、本発
明はこれに限定されるものではない。 ［実施例１］ （基板１１）サファイア（Ｃ面）よりなる基板１１をＭ
ＯＶＰＥの反応容器内にセットし、水素を流しながら、
基板の温度を１０５０℃まで上昇させ、基板のクリーニ
ングを行う。この基板１１としては他にＲ面、Ａ面を主
面とするサファイア基板、スピネル（ＭｇＡｌ2Ｏ4）の
ような絶縁性基板などでもよい。Embodiments of the present invention will be described below. Note that the present invention is not limited to this. [Example 1] (Substrate 11) The substrate 11 made of sapphire (C-plane) was M
Set in the OVPE reaction vessel, while flowing hydrogen,
The temperature of the substrate is raised to 1050 ° C., and the substrate is cleaned. The substrate 11 may be a sapphire substrate having an R surface or an A surface as a main surface, or an insulating substrate such as spinel (MgAl 2 O 4 ).
【００３４】（ｎ型窒化ガリウム系化合物半導体層１
２）基板をクリーニング後、ｎ型窒化ガリウム系化合物
半導体層１２を次の構成で成長させる。基板の温度を５
１０℃まで下げ、基板１１上にＧａＮよりなるバッファ
層を１００Å成長させる。次にバッファ層成長後、温度
を１０５０℃まで上昇させ、アンドープＧａＮ層１２１
を１．５μｍの膜厚で成長させる。続いて１０５０℃
で、Ｓｉを４．５×１０18／ｃｍ3ドープしたＧａＮ層
１２２を２．２μｍの膜厚で成長させる。(N-type gallium nitride-based compound semiconductor layer 1
2) After cleaning the substrate, an n-type gallium nitride-based compound semiconductor layer 12 is grown in the following configuration. Substrate temperature 5
The temperature is lowered to 10 ° C., and a GaN buffer layer is grown on the substrate 11 by 100 °. Next, after growing the buffer layer, the temperature is increased to 1050 ° C., and the undoped GaN layer 121 is grown.
Is grown to a thickness of 1.5 μm. Then 1050 ° C
Then, a GaN layer 122 doped with 4.5 × 10 18 / cm 3 of Si is grown to a thickness of 2.2 μm.
【００３５】続いて１０５０℃で、アンドープＧａＮ層
１２３を３０００Åの膜厚で、さらにＳｉを４．５×１
０18／ｃｍ3ドープしたＧａＮ層１２４を３００Å、さ
らにアンドープＧａＮ層１２５を５０Åの膜厚で成長さ
せる。続いて同様の温度で、アンドープＧａＮよりなる
第１の層を４０Å、温度を８００℃にして、続いてアン
ドープＩｎ0.13Ｇａ0.87Ｎよりなる第２の層を２０Åの
膜厚で成長させ、これらの操作を繰り返し、第１＋第２
＋の順で交互に１０層ずつ積層させ、最後に第１の層を
積層させた、ｎ型多層膜層１２６を成長させる。Subsequently, at 1050 ° C., the undoped GaN layer 123 was formed to a thickness of 3000
The GaN layer 124 doped with 0 18 / cm 3 is grown to a thickness of 300 °, and the undoped GaN layer 125 is grown to a thickness of 50 °. Subsequently, at the same temperature, the first layer made of undoped GaN is heated to 40 ° C. and the temperature is set to 800 ° C., and then the second layer made of undoped In 0.13 Ga 0.87 N is grown to a thickness of 20 °. Repeat the operation, 1st + 2nd
An n-type multilayer layer 126 having ten layers stacked alternately in the order of + and the first layer stacked last is grown.
【００３６】（活性層１３）次にｎ型窒化ガリウム系化
合物半導体層１２を成長後、アンドープＧａＮよりなる
障壁層を２００Åの膜厚で成長させ、続いて温度を８０
０℃にして、Ｓｉを５×１０17／ｃｍ3ドープしたＩｎ
0.3Ｇａ0.7Ｎよりなる井戸層を３０Åの膜厚で成長させ
る。そして障壁＋井戸＋障壁＋井戸・・・・の順で障壁
層を６層と、井戸層５層を交互に積層して、総膜厚１３
５０Åの多重量子井戸よりなる活性層１３を積層させ
る。(Active Layer 13) Next, after growing the n-type gallium nitride-based compound semiconductor layer 12, a barrier layer made of undoped GaN is grown to a thickness of 200.degree.
0 ° C., and 5 × 10 17 / cm 3 doped In
A well layer of 0.3 Ga 0.7 N is grown to a thickness of 30 °. Then, six barrier layers and five well layers are alternately stacked in the order of barrier + well + barrier + well.
An active layer 13 composed of a multiple quantum well of 50 ° is laminated.
【００３７】（ｐ型窒化ガリウム系化合物半導体層１
４）活性層１３成長後、ｐ型窒化ガリウム系化合物半導
体１４を次の構成で成長させる。次に１０５０℃で、Ｍ
ｇを５×１０19／ｃｍ3ドープしたｐ型Ａｌ0.1Ｇａ0.9
Ｎよりなる第３の層を２５Åの膜厚で成長させ、続いて
アンドープＧａＮよりなる第４の層を２５Åの膜厚で成
長させ、これらの操作を繰り返し、第３＋第４の順で交
互に４層ずつ積層した超格子よりなるｐ型多層膜層を２
００Åの膜厚で成長させる。続いて１０５０℃で、Ｍｇ
を１×１０20／ｃｍ3ドープしたｐ型ＧａＮよりなる層
を２７００Åの膜厚で成長させる。反応終了後、温度を
室温まで下げ、窒素雰囲気中で７００℃でアニーリング
を行い、ｐ型層をさらに低抵抗化する。(P-type gallium nitride-based compound semiconductor layer 1
4) After the growth of the active layer 13, a p-type gallium nitride-based compound semiconductor 14 is grown in the following configuration. Then at 1050 ° C., M
g × 5 × 10 19 / cm 3 doped p-type Al 0.1 Ga 0.9
A third layer made of N is grown to a thickness of 25 °, a fourth layer made of undoped GaN is grown to a thickness of 25 °, and these operations are repeated, and alternately in the third + fourth order. A p-type multilayer film layer consisting of a superlattice laminated four by four
It is grown to a thickness of 00 °. Subsequently, at 1050 ° C., Mg
Is grown at a thickness of 2700 ° from a p-type GaN doped with 1 × 10 20 / cm 3 . After the completion of the reaction, the temperature is lowered to room temperature, and annealing is performed at 700 ° C. in a nitrogen atmosphere to further reduce the resistance of the p-type layer.
【００３８】以上のようにして窒化ガリウム系化合物半
導体を成長させたウエハーを反応容器から取り出し、分
離溝を形成する部分を除きウエハ全体にＳｉＯ2マスク
を形成し、ＲＩＥによって、サファイア基板に到達する
までエッチングを行うことにより分離溝を形成する。さ
らに分離溝の形成に用いたＳｉＯ2マスクを剥離し、ｎ
型窒化ガリウム系化合物半導体層１２を露出するため
に、露出させる部分を除くｐ型窒化ガリウム系化合物半
導体層１４の上にＳｉＯ2マスクを形成し、ＲＩＥによ
って、エッチングを行い、ｎ型窒化ガリウム系化合物半
導体層１２（ＳｉドープＧａＮ層１２２）の表面を露出
させる。The wafer on which the gallium nitride-based compound semiconductor has been grown as described above is taken out of the reaction vessel, and a SiO 2 mask is formed on the entire wafer except for a portion where a separation groove is to be formed, and reaches the sapphire substrate by RIE. The isolation groove is formed by performing the etching up to this point. Further, the SiO 2 mask used for forming the separation groove is peeled off, and n
In order to expose the n-type gallium nitride-based compound semiconductor layer 12, an SiO 2 mask is formed on the p-type gallium nitride-based compound semiconductor layer 14 excluding the exposed portion, and the n-type gallium nitride-based compound semiconductor layer is etched by RIE. The surface of the compound semiconductor layer 12 (Si-doped GaN layer 122) is exposed.
【００３９】次にｐ型窒化ガリウム系化合物半導体層１
４のほぼ全面を開口させ、他の部分を覆うようにレジス
ト塗布し、開口させたｐ型窒化ガリウム系化合物半導体
層上にＮｉを１００Å、Ｐｔを５００Å積層後、アニー
ルしてｐ側オーミック電極１５を形成する。さらにｐ側
オーミック電極の一部にＰｔを３０００Å、Ｎｉを６０
Åからなるｐ側パッド電極１６ａ（１６）を形成する。
次にレジストを除去し、今度はｎ型窒化ガリウム系化合
物半導体層上にＷを２００Å、Ａｌを１０００Å、Ｗを
５００Å、Ｐｔを３０００Å、Ｎｉを６０Åの順で積層
したｎ側オーミック電極１４を形成する。Next, the p-type gallium nitride compound semiconductor layer 1
4 is coated with a resist so as to cover almost the entire surface, and the other portions are covered. Ni is deposited on the opened p-type gallium nitride-based compound semiconductor layer at 100 ° and Pt at 500 °, and then annealed to form a p-side ohmic electrode 15. To form Further, a part of the p-side ohmic electrode is made of Pt 3000 ° and Ni 60
A p-side pad electrode 16a (16) made of Å is formed.
Next, the resist is removed, and an n-side ohmic electrode 14 is formed on the n-type gallium nitride-based compound semiconductor layer, in which W is stacked in the order of 200 °, Al is 1000 °, W is 500 °, Pt is 3000 °, and Ni is 60 °. I do.
【００４０】次に全面にＳｉＯ2よりなる絶縁保護膜１
７を１．５μｍの膜厚で形成し、ｐ側パッド電極とｎ側
オーミック電極の一部をＲＩＥにより露出させる。さら
に表面に接続電極を形成する部分を開口させるようにマ
スク形成して分離溝を挟むｐ側パッド電極とｎ側オーミ
ック電極とを電気的に接続する接続電極として、Ｔｉを
４００Å、Ｐｔを６０００Å、Ａｕを１０００Å、Ｎｉ
を６０Åの膜厚で形成する。最後にＳｉＯ2からなる絶
縁保護膜３０を１．５μｍの膜厚で形成し、外部と電気
的に接続できるように接続電極２４、２６上の絶縁保護
膜３０をＲＩＥでエッチングすることにより除去して集
積型窒化物半導体素子を完成させる。Next, an insulating protective film 1 made entirely of SiO 2
7 is formed with a thickness of 1.5 μm, and a part of the p-side pad electrode and the n-side ohmic electrode is exposed by RIE. Further, as a connection electrode for electrically connecting a p-side pad electrode and an n-side ohmic electrode sandwiching a separation groove by forming a mask so as to open a portion where a connection electrode is formed on the surface, Ti is 400 °, Pt is 6000 °, Au 1000Å, Ni
Is formed with a thickness of 60 °. Finally, an insulating protective film 30 made of SiO 2 is formed with a thickness of 1.5 μm, and the insulating protective film 30 on the connection electrodes 24 and 26 is removed by RIE so as to be electrically connected to the outside. To complete an integrated nitride semiconductor device.
【００４１】以上のような工程で、１０００μｍ×１０
００μｍの基板上に３つの窒化物半導体素子が直列に接
続された図１の素子を作製したところ、動作電圧が１
０．５Ｖ、従来の３００μｍ×３００μｍ（動作電圧
３．５Ｖ）と同等の発光効率を示し、かつ各素子におい
てほぼ均一な発光が得られた。この素子は、動作電圧が
１０．５Ｖであるために、抵抗等の制御装置を介するこ
とでバッテリー電源（１２Ｖ）での使用が可能になる。In the above steps, 1000 μm × 10
When the device of FIG. 1 in which three nitride semiconductor devices were connected in series on a substrate of 00 μm was manufactured, the operating voltage was 1
The luminous efficiency was 0.5 V, equivalent to the conventional 300 μm × 300 μm (operating voltage 3.5 V), and almost uniform light emission was obtained in each element. Since this element has an operating voltage of 10.5 V, it can be used on a battery power supply (12 V) through a control device such as a resistor.
【００４２】[0042]
【発明の効果】以上詳細に説明したように、本発明に係
る集積型窒化物半導体発光素子は、上記ｐ層の一方の長
辺と上記ｎ側オーミック電極との間隔を２５０μｍ以下
に設定しているので、各発光素子の活性層全体にほぼ均
一に電流を注入することができので、均一に発光させる
ことができ、各発光素子における発光効率を良好にでき
る。また、本発明に係る集積型窒化物半導体発光素子に
おいては、均一発光及び発光効率を劣化させることな
く、各発光素子を一方向（長手方向）に十分長くするこ
とができるので、発光面積を大きくできかつ発光効率を
高くできるので、大面積でかつ発光効率の良い窒化物半
導体発光素子を提供することができる。As described above in detail, in the integrated nitride semiconductor light emitting device according to the present invention, the distance between one long side of the p layer and the n-side ohmic electrode is set to 250 μm or less. Therefore, current can be injected almost uniformly into the entire active layer of each light emitting element, so that light can be emitted uniformly and the light emitting efficiency of each light emitting element can be improved. Further, in the integrated nitride semiconductor light emitting device according to the present invention, each light emitting device can be made sufficiently long in one direction (longitudinal direction) without deteriorating uniform light emission and light emission efficiency. Therefore, a nitride semiconductor light emitting device having a large area and high luminous efficiency can be provided.
【図１】 本発明に係る実施の形態１の集積型窒化物半
導体発光素子の平面図である。FIG. 1 is a plan view of an integrated nitride semiconductor light emitting device according to a first embodiment of the present invention.
【図２】 図１のＡ−Ａ’線についての部分断面図（発
光素子１，２の部分）である。FIG. 2 is a partial cross-sectional view (portion of light-emitting elements 1 and 2) taken along line AA ′ of FIG.
【図３】 図１のＡ−Ａ’線についての部分断面図（発
光素子３の部分）である。FIG. 3 is a partial cross-sectional view (portion of a light emitting element 3) taken along line AA ′ of FIG.
【図４】 ｎ型窒化ガリウム系化合物半導体層の積層構
造を示す断面図である。FIG. 4 is a cross-sectional view showing a stacked structure of an n-type gallium nitride-based compound semiconductor layer.
【図５】 本発明に係る実施の形態２の集積型窒化物半
導体発光素子の平面図である。FIG. 5 is a plan view of an integrated nitride semiconductor light emitting device according to a second embodiment of the present invention.
１，２，３…発光素子、 １０…活性層、 １１…サファイア基板、 １２…ｎ型窒化ガリウム系化合物半導体層、 １３…ｐ型窒化ガリウム系半導体層、 １４，１４ａ…ｎ側オーミック電極、 １５…ｐ側オーミック電極、 １６，１６ａ…ｐパッド電極、 １７…絶縁保護膜、 ２１，５１，５２…接続電極、 ２４，２６…外部接続電極、 ３０…絶縁保護膜、 ６１，６２…スルーホール、 ４１…分離溝、 １２１…アンドープＧａＮ層、 １２２…ＳｉドープＧａＮ層、 １２３…アンドープＧａＮ層、 １２４…ＳｉドープＧａＮ層、 １２５…アンドープＧａＮ層、 １２６…多層膜層。 1, 2, 3 ... light emitting element, 10 ... active layer, 11 ... sapphire substrate, 12 ... n-type gallium nitride based compound semiconductor layer, 13 ... p-type gallium nitride based semiconductor layer, 14, 14a ... n-side ohmic electrode, 15 ... p-side ohmic electrode, 16, 16a ... p pad electrode, 17 ... insulating protective film, 21, 51, 52 ... connecting electrode, 24, 26 ... external connecting electrode, 30 ... insulating protective film, 61, 62 ... through hole, 41: separation groove, 121: undoped GaN layer, 122: Si-doped GaN layer, 123: undoped GaN layer, 124: Si-doped GaN layer, 125: undoped GaN layer, 126: multilayer film layer.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 仁木 勇 徳島県阿南市上中町岡491番地100 日亜化 学工業株式会社内 (72)発明者 庄野 博文 徳島県阿南市上中町岡491番地100 日亜化 学工業株式会社内 (72)発明者 若木 貴功 徳島県阿南市上中町岡491番地100 日亜化 学工業株式会社内 (72)発明者 森 誠一郎 徳島県阿南市上中町岡491番地100 日亜化 学工業株式会社内 Ｆターム(参考） 5F041 AA03 AA05 CA34 CA40 CA46 CA57 CA65 CA73 CA82 CA92 CB23 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Isamu Niki 491-1100 Kamikanakamachi Oka, Anan City, Tokushima Prefecture Inside Nichika Gaku Kogyo Co., Ltd. Within Aka Kagaku Kogyo Co., Ltd. (72) Takakazu Wakagi, Inventor 491-1100 Kaminakamachi Oka, Anan City, Tokushima Prefecture Inside Nika Kagaku Kogyo Co., Ltd. F-term (reference) in Nichia Chemical Industry Co., Ltd. 5F041 AA03 AA05 CA34 CA40 CA46 CA57 CA65 CA73 CA82 CA92 CB23
Claims (6)
り、 上記発光素子はそれぞれ、 上記基板上に形成されたｎ型窒化ガリウム系化合物半導
体層が分離溝によって分離されてなる長方形のｎ層と、 長方形のｐ型窒化ガリウム系化合物半導体が、その一方
の長辺と２つの短辺とがそれぞれ上記ｎ層の一方の長辺
と２つの短辺と近接するように上記ｎ層上に設けられて
成るｐ層と、 上記各ｎ層の他方の長辺と上記ｐ層の他方の長辺との間
のｎ層上に設けられ、上記ｐ層の長辺と実質的に同一の
長さを有するｎ側オーミック電極と、 上記ｐ層上のほぼ全面に形成されたｐオーミック電極
と、 上記ｐオーミック電極上に、上記ｐ層の一方の長辺に沿
って設けられたｐパッド電極とを備え、上記ｐ層の一方
の長辺と上記ｎ側オーミック電極との間隔を２５０μｍ
以下に設定したことを特徴とする集積型窒化物半導体発
光素子。A plurality of light emitting elements are juxtaposed on a substrate. Each of the light emitting elements has a rectangular n-type gallium nitride compound semiconductor layer formed on the substrate and separated by a separation groove. And a rectangular p-type gallium nitride-based compound semiconductor on the n-layer such that one long side and two short sides thereof are close to one long side and two short sides of the n layer, respectively. The p layer provided is provided on the n layer between the other long side of each of the n layers and the other long side of the p layer, and has a length substantially equal to the long side of the p layer. An n-side ohmic electrode having a thickness, a p-ohmic electrode formed over substantially the entire surface of the p-layer, and a p-pad electrode provided on the p-ohmic electrode along one long side of the p-layer. And a distance between one long side of the p-layer and the n-side ohmic electrode. 250 μm
An integrated nitride semiconductor light emitting device characterized by the following settings.
ック電極との間隔を２２０μｍ以下に設定した請求項１
記載の集積型窒化物半導体発光素子2. The distance between one long side of the p-layer and the n-side ohmic electrode is set to 220 μm or less.
Integrated nitride semiconductor light emitting device
請求項１又は２記載の集積型窒化物半導体発光素子。3. The integrated nitride semiconductor light emitting device according to claim 1, wherein said plurality of light emitting devices are connected in series.
請求項１又は２記載の集積型窒化物半導体発光素子。4. The integrated nitride semiconductor light emitting device according to claim 1, wherein said plurality of light emitting devices are connected in parallel.
子で発光された光を上記基板を介して出力する請求項１
〜４のうちのいずれか１項に記載の集積型窒化物半導体
発光素子。5. The light-emitting device according to claim 1, wherein the substrate has a light-transmitting property, and outputs light emitted from each of the light-emitting elements through the substrate.
5. The integrated nitride semiconductor light-emitting device according to any one of items 1 to 4,
層からなり、その複数の窒化ガリウム系半導体層のうち
の少なくとも１つが５．５〜７．２×１０−３Ωｃｍの
抵抗率と膜厚２μｍ以上のｎ型層である請求項１〜５の
うちのいずれか１つに記載の集積型窒化物半導体発光素
子。6. The n-layer comprises a plurality of gallium nitride-based semiconductor layers, and at least one of the plurality of gallium nitride-based semiconductor layers has a resistivity and a film thickness of 5.5 to 7.2 × 10 −3 Ωcm. The integrated nitride semiconductor light emitting device according to claim 1, wherein the integrated nitride semiconductor light emitting device is an n-type layer having a thickness of 2 μm or more.
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