JP2001516971A - Coplanar Si / Ge composite substrate and method of manufacturing the same - Google Patents
Coplanar Si / Ge composite substrate and method of manufacturing the sameInfo
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Abstract
(57)【要約】 シリコン領域を有するシリコンウエハと、前記シリコン領域の内部に集積化された少なくとも一つのGeXSi1-X領域と、を含む半導体構造。前記シリコン及びGeXSi1-X領域は、実質的にコプレナな表面であることができる。前記構造は、前記シリコン領域に形成された少なくとも一つのエレクトロニクスデバイスと、前記少なくとも一つのGeXSi1-X領域に形成されたIII−V材料の少なくとも一つのエレクトロニクスデバイスとを含むことができる。前記構造は、例えば、集積III−V/Si半導体マイクロチップであることができる。本発明の他の実施形態によれば、表面を有するシリコンウエハを提供することと、前記ウエハの前記表面の内部にビアのパターンを形成することと、前記ビアの内部にGe XSi1-Xの領域を堆積することとを含む半導体構造の製造方法が提供される。この方法は、前記ウエハと前記GeXSi1-X領域とが実質的にコプレナな表面を有するように前記ウエハを処理することを含むことができる。他の実施形態は、表面を有するシリコンウエハを提供することと、前記シリコンウエハの前記表面にGeXSi1-Xの領域を堆積することと、前記堆積されたGeXSi1-X領域がシリコンの内部に集積化されるようにシリコンを前記表面に堆積することとを含む半導体構造の製造方法を提供する。 (57) [Summary] A silicon wafer having a silicon region, and at least one Ge integrated inside the silicon region;XSi1-XA semiconductor structure comprising: a region; The silicon and GeXSi1-XThe region can be a substantially coplanar surface. The structure includes at least one electronic device formed in the silicon region and the at least one Ge device.XSi1-XAt least one electronic device of III-V material formed in the region. The structure can be, for example, an integrated III-V / Si semiconductor microchip. According to another embodiment of the present invention, providing a silicon wafer having a surface, forming a pattern of vias within the surface of the wafer, and forming a Ge within the via. XSi1-XA method for manufacturing a semiconductor structure, comprising: depositing a region of the semiconductor structure. The method comprises the steps of:XSi1-XTreating the wafer such that the region has a substantially coplanar surface. Another embodiment provides a silicon wafer having a surface, and Ge is provided on the surface of the silicon wafer.XSi1-XDepositing an area ofXSi1-XDepositing silicon on said surface such that regions are integrated within the silicon.
Description
(発明の背景) 本発明は、格子不整合な半導体材料の集積化に関しており、特に、SiGe材
料のSi基板上への集積化に関する。BACKGROUND OF THE INVENTION The present invention relates to the integration of lattice-mismatched semiconductor materials, and more particularly, to the integration of SiGe materials on Si substrates.
【0001】 多くの格子整合したデバイス及び回路が成熟するにつれて、格子不整合な半導
体、デバイス及び回路への興味が増している。増加する商業的な興味の裏側には
、集積化及び部品性能という2つの推進力がある。異なる半導体材料を共通の基
板上に集積することは、設計者に性能の改善、コストの低下、及び信頼性の増加
を可能にする。これより、この内的な進歩の影響を最も受けるアプリケーション
とは、現在ではもっと従来的なパッケージング法で別個にパッケージングして結
合されている複数のタイプの半導体材料を必要とするシステムであろう。これら
のアプリケーションの例は、Si上へのIII−V材料の集積化、及びSiGe回 路のSiCMOSとの集積化である。そのようなシングルチップシステムは、通
信技術において、特に無線通信技術において、広いアプリケーションを有するも
のと期待されている。As many lattice-matched devices and circuits have matured, interest in lattice-mismatched semiconductors, devices and circuits has increased. Behind the increasing commercial interest are two driving forces: integration and component performance. Integrating different semiconductor materials on a common substrate allows designers to improve performance, reduce cost, and increase reliability. Thus, the applications most affected by this internal advance are those systems that require multiple types of semiconductor materials that are now separately packaged and bonded in more traditional packaging methods. Would. Examples of these applications are the integration of III-V materials on Si and the integration of SiGe circuits with SiCMOS. Such single-chip systems are expected to have wide applications in communication technology, especially in wireless communication technology.
【0002】 異なる半導体を結合したものの有益性は、結果として得られる材料の質に依存
する。基板と堆積層との間の大きな格子不整合は、材料の堆積中に応力を生じて
堆積層の中に多くの欠陥を生成し、劣った材料特性及び限られた性能を招く結果
になる。高不整合堆積層におけるスレッディング転位(threading d
islocation)の密度を制御するためには、確立された手法は、基板の
パターニング及び組成傾斜の2つしかない。基板のパターニングの場合、このア
イデアは、スレッディング転位は結合構造(ジオメトリ;geometry)の
必然である、すなわち転位は結晶内で終わることができないという知識を利用す
る。基板をより小さな成長領域にパターニングすることによって自由端を他の自
由端に近づけることができれば、そのときには、スレッディング転位密度を減少
させることが可能である。この技法は、転位核の形成(dislocation
nucleation)が激しくない低不整合システムに対して最も良く作用
するが、高不整合システムのスレッディング転位密度も同様に低減するであろう
。[0002] The benefit of combining different semiconductors depends on the quality of the resulting material. Large lattice mismatch between the substrate and the deposited layer creates stresses during the deposition of the material, creating many defects in the deposited layer, resulting in poor material properties and limited performance. Threading dislocations in highly mismatched deposited layers
There are only two established approaches to controlling the density of islocation: substrate patterning and composition gradients. In the case of patterning a substrate, the idea makes use of the knowledge that threading dislocations are a necessity of a geometry, ie, dislocations cannot end in the crystal. If the free end can be made closer to other free ends by patterning the substrate into smaller growth areas, then the threading dislocation density can be reduced. This technique involves the formation of dislocation nuclei (dislocation nuclei).
While it works best for low mismatch systems where the nucleation is not severe, the threading dislocation density of high mismatch systems will be reduced as well.
【0003】 他の確立された手法は、組成傾斜層の使用である。全体として大きな不整合に
到達するために、一連の小さな不整合界面によって、スレッディング転位密度を
低く抑えながら大きな緩和を得ることができるであろうことが想像される。各層
が実質的に緩和され、下の層からのスレッディング転位を再利用することができ
るならば、この結果が可能である。この方法は、ずいぶん以前に、格子不整合な
GaAs基板上に成長したGaAsPのLEDに経験的なやりかたで適用された
。しかし、GaAsPプロセスが製造へ移された後は、引き続く格子不整合研究
の大半は単一の不整合界面に焦点を絞った。AlGaAs/GaAs構造及びI
nGaAsP/InP構造が光エレクトロニクス及びエレクトロニクスデバイス
のアプリケーションで主流になるにつれて、アプリケーションにおける格子不整
合材料に対する推進力は減少した。これらの材料系が完全に開発されるまで、高
不整合層の実施は不必要のようであった。[0003] Another established approach is the use of compositionally graded layers. It is envisioned that a series of small mismatched interfaces would allow for a large relaxation while keeping the threading dislocation density low to reach a large mismatch overall. This result is possible if each layer is substantially relaxed and threading dislocations from underlying layers can be reused. This method has long been applied empirically to GaAsP LEDs grown on lattice-mismatched GaAs substrates. However, after the GaAsP process was moved into manufacturing, most of the subsequent lattice mismatch studies focused on a single mismatch interface. AlGaAs / GaAs structure and I
As nGaAsP / InP structures have become mainstream in optoelectronic and electronic device applications, the driving force for lattice mismatched materials in applications has decreased. Until these material systems were fully developed, the implementation of a highly mismatched layer appeared unnecessary.
【0004】 傾斜層に対する新しい興味が、新規な部品に対する要求の増加、及び更なる集
積化に対する要求の増加のために生じてきた。緩和傾斜SiGeにおける進歩は
、Si上の緩和SiGeに基づくSiGeデバイス、及び中間緩和SiGe傾斜
層を使用したSi上へのIII−V材料の集積化が可能であることを示してきてい る。これより、緩和された傾斜SiGe層は、SiGeデバイス及び/又はIII −VデバイスとSi基板との間の材料ブリッジとして機能することができる。[0004] New interest in graded layers has arisen due to the increasing demand for new components and increasing integration requirements. Advances in relaxed graded SiGe have shown that SiGe devices based on relaxed SiGe on Si and the integration of III-V materials on Si using intermediate relaxed SiGe graded layers are possible. Thus, the relaxed graded SiGe layer can function as a material bridge between the SiGe device and / or III-V device and the Si substrate.
【0005】 しかし、これらの材料の進歩は、これらの緩和層と引き続くデバイスとを比較
的標準のSi回路プロセスによって生成するための適切なプロセスシーケンスが
発見されない限りは、不完全である。エレクトロニクス及び光エレクトロニクス
システムの決定的な(クリティカルな)見解は、多くのアプリケーションにおけ
るメインのデータ処理が、今日の半導体産業で優勢にあるSiCMOS回路で実
行されることができるということである。Siベースのシングルチップシステム
の新しい領域を創り出すためには、SiCMOS回路を上述の緩和傾斜SiGe
における材料の進歩と結び付ける構造及びプロセスが必要である。However, advances in these materials are imperfect unless a suitable process sequence for producing these relaxation layers and subsequent devices by relatively standard Si circuit processes is found. The definitive (critical) view of electronics and optoelectronic systems is that the main data processing in many applications can be performed in SiCMOS circuits that predominate in today's semiconductor industry. In order to create a new area of Si-based single-chip systems, SiCMOS circuits can be implemented using the relaxed gradient SiGe described above
There is a need for structures and processes that tie in with the advances in materials in.
【0006】 (発明の要旨) 本発明は、コプレナSiGe/Si基板を製造する方法を提供する。SiGe
領域は、緩和傾斜SiGe技術を使用して形成される。以下で説明される平坦化
(プレーナライゼーション)プロセスは、SiCMOSプロセスを通じて処理さ
れ得る改変されたSiウエハを生成する。CMOSプロセスにおける適当な時点
で、SiGe領域の上又は中のデバイスがメタライズされてCMOS回路に接続
され、Siデバイス、SiGeデバイス、及び/又はIII−Vデバイスを使用し ているシングルチップシステムを生成することができる。SUMMARY OF THE INVENTION The present invention provides a method for manufacturing a coplanar SiGe / Si substrate. SiGe
The regions are formed using relaxed gradient SiGe technology. The planarization process described below produces a modified Si wafer that can be processed through a SiCMOS process. At an appropriate point in the CMOS process, devices on or in the SiGe region are metallized and connected to CMOS circuits to create a single-chip system using Si, SiGe, and / or III-V devices. be able to.
【0007】 本発明はさらに、緩和GeSi結晶性合金表面がSiとコプレナ的な仕方で共
存できるような構造を製造する半導体構造及び方法を提供する。そのような基板
は、GeSi材料及びデバイス、並びに/又はGeSi上に成長されたIII−V 材料及びデバイスとSiエレクトロニクスとの集積化が望まれるような多くのア
プリケーション(the plethora of applications
)を活用する(harness)ために必須である。The present invention further provides a semiconductor structure and method for producing a structure in which a relaxed GeSi crystalline alloy surface can coexist with Si in a coplanar manner. Such substrates can be used in many applications where integration of Si electronics with GeSi materials and devices and / or III-V materials and devices grown on GeSi is desired.
) Is required for harnessing.
【0008】 したがって、本発明のある実施形態によれば、シリコン領域と、そのシリコン
領域の内部に集積化された少なくとも一つのGeXSi1-X領域とを有するシリコ
ンウエハを備えている半導体構造が提供される。シリコン及びGeXSi1-X領域
は、実質的にコプレナな表面であることができる。この構造は、前記シリコン領
域に形成された少なくとも一つのエレクトロニクスデバイスと、前記少なくとも
一つのGeXSi1-X領域に形成されたIII−V材料からなる少なくとも一つのエ レクトロニクスデバイスとを含むことができる。この構造は、例えば集積化III −V/Si半導体マイクロチップであってもよい。Thus, according to one embodiment of the present invention, a semiconductor structure comprising a silicon wafer having a silicon region and at least one Ge x Si 1-x region integrated within the silicon region Is provided. The silicon and Ge x Si 1-x regions can be substantially coplanar surfaces. The structure may include at least one electronic device formed in the silicon region and at least one electronic device made of III-V material formed in the at least one Ge x Si 1-x region. it can. This structure may be, for example, an integrated III-V / Si semiconductor microchip.
【0009】 本発明の他の実施形態によれば、表面を有するシリコンウエハを提供すること
と、そのウエハの前記表面の内部にビアのパターンを形成することと、そのビア
の内部にGeXSi1-Xの領域を堆積することとを含む半導体構造の製造方法が提
供される。この方法は、ウエハとGeXSi1-X領域とが実質的にコプレナな表面
を有するように、ウエハを処理することを含むことができる。他の実施形態は、
表面を有するシリコンウエハを提供することと、そのシリコンウエハの前記表面
にGeXSi1-Xの領域を堆積することと、堆積されたGeXSi1-X領域がシリコ
ンの内部に集積化されるように前記表面にシリコンを堆積することとを含む半導
体構造の製造方法を提供する。According to another embodiment of the present invention, there is provided a silicon wafer having a surface, forming a pattern of vias inside said surface of the wafer, and Ge x Si inside the vias. A method of fabricating a semiconductor structure comprising depositing a 1-X region is provided. The method can include treating the wafer such that the wafer and the Ge x Si 1-x regions have a substantially coplanar surface. Other embodiments include:
Providing a silicon wafer having a surface, depositing a region of the Ge X Si 1-X, it was deposited Ge X Si 1-X region is inside integration of silicon on the surface of the silicon wafer Depositing silicon on the surface as described above.
【0010】 本発明のこれら及び他の目的、特徴、及び効果は、添付の図面に描かれている
ように、本発明の好適な実施形態の以下の詳細な説明を考慮すれば、明らかにな
るであろう。 (発明の詳細な説明) 図1A〜1Eは、本発明にしたがってGeSi合金及びSiの両方を表面に有
する基板のウエハを製造するプロセスを示す、半導体構造の一連の側面図である
。図1Aは、最初のプロセス工程を示しており、ここでは、最初に、従来のSi
ウエハ100のパターニングを行う。そのようなウエハは通常は(001)向き
のウエハであり、(001)ウエハのオフカットはウエハを[110]方向に向か
って6度ポリッシュすることによって誘起される。このSiウエハは、ビア10
2がウエハの中にエッチングされ得るように、リソグラフ的にパターニングされ
てマスクされるべきである。これらのビアは、GeSi材料が堆積される領域に
なるであろう。[0010] These and other objects, features, and advantages of the present invention will become apparent in view of the following detailed description of a preferred embodiment of the invention, as illustrated in the accompanying drawings. Will. DETAILED DESCRIPTION OF THE INVENTION FIGS. 1A-1E are a series of side views of a semiconductor structure illustrating a process for manufacturing a wafer of a substrate having both a GeSi alloy and Si on a surface in accordance with the present invention. FIG. 1A shows an initial process step, in which first a conventional Si
The patterning of the wafer 100 is performed. Such a wafer is typically a (001) oriented wafer, and offcutting of the (001) wafer is induced by polishing the wafer six times in the [110] direction. This Si wafer has via 10
It should be lithographically patterned and masked so that 2 can be etched into the wafer. These vias will be areas where the GeSi material is deposited.
【0011】 例えば、SiウエハはSiO2の層104でコートされ、ウィットなホトレジ ストでカバーされ、リソグラフ的に現像されて、ウエハに所望のパターンを製造
することができる。HF水又はバッファドエッチング溶液をその後に使用して、
ホトレジストが除去された領域から酸化物を除去することができる。最後に、ホ
トレジストが除去された後にKOHのようなSiO2をエッチングしないエッチ ング溶液にウエハを浸すことによって、Siビア102を形成することができる
。この結果が、Siビアの形成である。より垂直な側壁が望まれるときには、例
えば、KOHエッチング工程の代わりにドライエッチングを使用することができ
る。For example, a Si wafer can be coated with a layer of SiO 2 104, covered with a witty photoresist, and lithographically developed to produce the desired pattern on the wafer. Using HF water or a buffered etching solution afterwards,
The oxide can be removed from the areas where the photoresist has been removed. Finally, by immersing the wafer in an etch packaging solution does not etch the SiO 2 such as KOH after photoresist has been removed, it is possible to form the Si vias 102. The result is the formation of Si vias. If more vertical sidewalls are desired, for example, a dry etch can be used instead of a KOH etch step.
【0012】 ウエハはその後に洗浄されて、残りのプロセスにこのエッチング工程からのコ
ンタミネーションが持ち込まれないことを確実にすることができる。ウエハはそ
の後に、化学的気相成長システムのようなGeSi堆積システムの中に挿入され
る。図1Bに示されているように、傾斜GeSi層106は、Ge組成がビア1
02の中の材料の厚さにわたって傾斜するように堆積される。傾斜領域の終わり
では、所望の組成の一様な組成のGeSi層108が、成長表面が成長の終了前
にSi表面を横切るように成長される。この要件が、ビアの中でのGeSiの成
長がSiウエハの表面の上方に達することを確実にし、また、引き続く平坦化工
程が一様層の下方に位置する組成傾斜層の中には達しないことを確実にする。The wafer can then be cleaned to ensure that no contamination from this etching step is introduced into the rest of the process. The wafer is then inserted into a GeSi deposition system, such as a chemical vapor deposition system. As shown in FIG. 1B, the graded GeSi layer 106 has a Ge composition of via 1
02 is deposited to be graded across the thickness of the material in 02. At the end of the graded region, a uniform composition GeSi layer 108 of the desired composition is grown such that the growth surface crosses the Si surface before the end of growth. This requirement ensures that the growth of GeSi in the via reaches above the surface of the Si wafer, and that subsequent planarization steps do not extend into the compositionally graded layer located below the uniform layer Make sure that.
【0013】 SiGeの成長のために使用される条件は、緩和SiGe傾斜構造に対する最
適成長条件と一致するべきである。例えば、Ge30%の濃度を合金化するよう
に成長される傾斜層は、典型的にはUHVCVDで、約750〜800℃の温度
で且つ25mTの反応炉圧力の下で成長される。傾斜率は、典型的には1μmあ
たりGe10%以下である。The conditions used for the growth of SiGe should be consistent with the optimal growth conditions for a relaxed SiGe graded structure. For example, a graded layer grown to alloy a concentration of 30% Ge is typically grown by UHVCVD at a temperature of about 750-800 ° C. and under a reactor pressure of 25 mT. The slope rate is typically 10% Ge or less per μm.
【0014】 図1Cに示されているように、ウエハはその後に、化学機械的にポリッシュバ
ックされて、一様なGeSi領域108がSi表面とコプレナになる。もし、酸
化物層がこのポリッシュ工程のために除去されなければ、これをポリッシュプロ
セスの制御として使用することができる。ウエハがポリッシュされるときの色の
変化が、Siウエハ表面への接近のシグナルとなるであろう。Si表面に到達す
ると、その表面はコプレナであるのでポリッシュは終了される。As shown in FIG. 1C, the wafer is then chemically mechanically polished back to make uniform GeSi regions 108 coplanar with the Si surface. If the oxide layer is not removed for this polishing step, it can be used as a control for the polishing process. The change in color as the wafer is polished will signal the approach to the Si wafer surface. When the Si surface is reached, polishing is terminated because the surface is coplanar.
【0015】 この構造によれば、この段階でウエハを従来のSiエレクトロニクス(CMO
S)製造ラインに挿入して、SiエレクトロニクスのためにSi領域を処理する
ことが可能であることが理解されるであろう。唯一の制約は、最高温度工程の温
度を低くするようにSiCMOSプロセスが改変されるかもしれないという点で
ある。このプロセスは、GeSi合金中でGe70〜100%であるような高G
e合金を必要とするかもしれない。これらの合金の融点は、936℃であるGe
の融点に近づく。これより、GeSi合金層がGe100%にまで傾斜するとき
には、Ge層が著しくダメージを受けないようにSiCMOS処理温度が下げら
れるべきである。According to this structure, at this stage, the wafer is replaced with the conventional Si electronics (CMO).
S) It will be appreciated that it is possible to insert into a production line to process the Si area for Si electronics. The only limitation is that the SiCMOS process may be modified to lower the temperature of the highest temperature step. This process is suitable for high G, such as 70-100% Ge in GeSi alloy.
An e-alloy may be required. The melting point of these alloys is 936 ° C. Ge
Approaching its melting point. Thus, when the GeSi alloy layer is tilted to 100% Ge, the SiCMOS processing temperature should be lowered so that the Ge layer is not significantly damaged.
【0016】 平坦化及び/又はCMPを使用した改良された傾斜SiGe構造における他の
進歩が本発明と組み合わされて、SiGe材料の質を改良することができること
も理解されるであろう。例えば、ここで説明されているプロセスを使用して、G
e50%合金とSiとのコプレナを生成することができる。SiGe領域の上へ
の引き続く連続した傾斜層の成長の結果として、高Ge濃度の改良されたSiG
e合金がSiGeビア領域の上にもたらされるであろう。It will also be appreciated that other advancements in improved graded SiGe structures using planarization and / or CMP can be combined with the present invention to improve the quality of the SiGe material. For example, using the process described here, G
eCoplanar of 50% alloy and Si can be produced. As a result of the subsequent growth of the continuous graded layer over the SiGe region, a high Ge concentration of the improved SiG
An e-alloy will be provided over the SiGe via area.
【0017】 アプリケーションの例は、GeSiトランジスタと伝統的なSiCMOS回路
及びデバイスとの集積化である。この場合、GeSi領域はGe30%まで傾斜
されてもよく、SiCMOSプロセスの処理温度は、わずかに変更されなければ
ならないだけであろう。An example of an application is the integration of GeSi transistors with traditional SiCMOS circuits and devices. In this case, the GeSi region may be sloped to 30% Ge, and the processing temperature of the SiCMOS process will only need to be changed slightly.
【0018】 図1Eに示されているように、SiCMOSエレクトロニクスは領域110と
して示されており、これは例えば、Siトランジスタとそれらの間の従来の内部
配線(インターコネクト)とを含むことができる。SiCMOSとの集積III− Vデバイスの場合、一般に合金はより高い格子定数、例えばGe70〜100%
まで傾斜される。これらのより高いGe組成は、より大きな格子定数を有し、し
たがってIII−V材料の幾つかとは格子不整合である。また、この場合、上記の ように、プロセスの開始時にオフカットウエハを使用することが避けられない。As shown in FIG. 1E, SiCMOS electronics is shown as region 110, which may include, for example, Si transistors and conventional interconnects between them. For integrated III-V devices with SiCMOS, the alloy generally has a higher lattice constant, eg, 70-100% Ge.
Tilted up. These higher Ge compositions have larger lattice constants and are therefore lattice mismatched with some of the III-V materials. In this case, as described above, it is inevitable to use an off-cut wafer at the start of the process.
【0019】 Si領域の上へのCMOS製造の間に、全プロセスの間、GeSi領域をSi
O2でカバーすることができる。SiCMOSの製造後に、GeSiの上方の領 域が露出されることができて、SiCMOS又はエレクトロニクスは酸化物又は
窒化物のパシベーションマスク層112で保護されることができる。ひとたびG
eSi領域が露出されると、図1Eに示されるようにIII−V材料の層114を 堆積することができる。高転位密度がGaAs層に形成されることを防ぐために
、Geの上へのGaAsの成長を正確に開始する際に、注意深くなければならな
い。III−V成長後に、この材料は規定され又はエッチングされることができ( マスクは分解されてリフトオフされる)、最後のメタライゼーションが行われて
III−Vデバイスが内部配線(インターコネクト)116を介してお互いに且つ Siエレクトロニクスにも接続され、これによって集積III−V/Siチップが 形成される。During CMOS fabrication over the Si region, the GeSi region is
It can be covered by O 2. After fabrication of the SiCMOS, the area above the GeSi can be exposed and the SiCMOS or electronics can be protected with an oxide or nitride passivation mask layer 112. Once G
Once the eSi region is exposed, a layer 114 of III-V material can be deposited as shown in FIG. 1E. Care must be taken in accurately starting the growth of GaAs on Ge to prevent high dislocation densities from forming in the GaAs layer. After III-V growth, this material can be defined or etched (the mask is disassembled and lifted off) and the final metallization is performed.
The III-V devices are connected to each other and to the Si electronics via internal interconnects (interconnects) 116, thereby forming an integrated III-V / Si chip.
【0020】 図2は、マイクロチップ120として形成された例示的なコプレナSiエレク
トロニクス/GeSiコンポジット基板の上面図である。このチップは、上述の
ように製造されたGeSi領域122と、内部配線(インターコネクト)126
によってこのGeSi領域に接続されたSiCMOS回路領域124とを含む。FIG. 2 is a top view of an exemplary coplanar Si electronics / GeSi composite substrate formed as a microchip 120. This chip includes a GeSi region 122 manufactured as described above, and an internal wiring (interconnect) 126.
And a SiCMOS circuit region 124 connected to the GeSi region.
【0021】 本発明が、その幾つかの好適な実施形態に関して示され且つ説明されてきたが
、その形態及びその詳細に対する様々な変化、省略及び追加が、本発明の考え及
び範囲を逸脱することなく、これに行われてもよい。Although the present invention has been shown and described with reference to certain preferred embodiments thereof, various changes, omissions and additions to that form and its details depart from the spirit and scope of the invention. Instead, this may be done.
【図1】 図1A〜図1Eは、本発明にしたがってGeSi合金及びSiの
両方を表面に有する基板のウエハを製造するプロセスを示す、半導体構造の一連
の側面図である。1A-1E are a series of side views of a semiconductor structure illustrating a process for manufacturing a wafer of a substrate having both a GeSi alloy and Si on a surface in accordance with the present invention.
【図2】 図2は、マイクロチップとして形成された例示的なコプレナSi
エレクトロニクス/GeSiコンポジット基板の上面図である。FIG. 2 shows an exemplary coplanar Si formed as a microchip.
FIG. 2 is a top view of an electronics / GeSi composite substrate.
───────────────────────────────────────────────────── フロントページの続き (71)出願人 77 Massachusetts Ave nue,Cambridge,MA 02139 USA 【要約の続き】 の領域を堆積することと、前記堆積されたGeXSi1-X 領域がシリコンの内部に集積化されるようにシリコンを 前記表面に堆積することとを含む半導体構造の製造方法 を提供する。────────────────────────────────────────────────── internal ─── front page continued (71) applicant 77 Massachusetts Ave nue, Cambridge, depositing a region of the continuation of Abstract MA 02139 USA, the deposited Ge X Si 1-X regions is silicon Depositing silicon on said surface so as to be integrated in the semiconductor device.
Claims (10)
、 を備える、半導体構造。1. A semiconductor structure, comprising: a silicon wafer having a silicon region; and at least one Ge x Si 1-x region integrated inside the silicon region.
を備えている、請求の範囲1に記載の半導体構造。2. The semiconductor structure according to claim 1, wherein said silicon and Ge x Si 1 -x regions have a substantially coplanar surface.
ニクスデバイスをさらに備えている、請求の範囲1に記載の半導体構造。3. The semiconductor structure according to claim 1, further comprising at least one electronic device formed in said silicon region.
の範囲1に記載の半導体構造。4. The semiconductor structure of claim 1, further comprising at least one electronic device of III-V material formed in said at least one Ge x Si 1-x region.
の範囲1に記載の半導体構造。5. The semiconductor structure of claim 1, further comprising at least one electronic device of III-V material formed in said at least one Ge x Si 1-x region.
、 前記シリコン領域の内部に集積化された少なくとも一つのGeXSi1-X領域と
、 前記少なくとも一つのGeXSi1-X領域に形成されたIII−V材料の少なくと も一つのエレクトロニクスデバイスと、 を備える、集積III−V/Si半導体マイクロチップ。6. A silicon wafer having a silicon region; at least one electronic device formed in the silicon region; at least one Ge x Si 1-x region integrated inside the silicon region; An integrated III-V / Si semiconductor microchip comprising: at least one electronic device of III-V material formed in at least one Ge x Si 1-x region.
、 前記シリコン領域の内部に集積化された少なくとも一つのGeXSi1-X領域と
、 前記少なくとも一つのGeXSi1-X領域に形成されたGeSi材料の少なくと
も一つのエレクトロニクスデバイスと、 を備える、集積GeSi/Si半導体マイクロチップ。7. A silicon wafer having a silicon region; at least one electronic device formed in the silicon region; at least one Ge x Si 1-x region integrated inside the silicon region; An integrated GeSi / Si semiconductor microchip comprising: at least one electronic device of GeSi material formed in at least one Ge x Si 1-x region.
表面を有するように前記ウエハを処理する工程をさらに含む、請求の範囲8に記
載の方法。9. The method of claim 8, further comprising treating the wafer such that the wafer and the Ge x Si 1-x region have a substantially coplanar surface.
リコンを前記表面に堆積する工程と、 を含む、半導体構造の製造方法。10. Providing a silicon wafer having a surface, depositing a Ge x Si 1-x region on the surface of the silicon wafer, wherein the deposited Ge x Si 1-x region is silicon. Depositing silicon on said surface so as to be integrated inside said semiconductor device.
Applications Claiming Priority (3)
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US5909197P | 1997-09-16 | 1997-09-16 | |
US60/059,091 | 1997-09-16 | ||
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JP2001516971A true JP2001516971A (en) | 2001-10-02 |
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US (2) | US20010006249A1 (en) |
EP (1) | EP1036412A1 (en) |
JP (1) | JP2001516971A (en) |
KR (1) | KR20010024041A (en) |
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WO (1) | WO1999014804A1 (en) |
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JP2744350B2 (en) | 1990-11-22 | 1998-04-28 | キヤノン株式会社 | Semiconductor substrate and method of manufacturing the same |
US5221413A (en) * | 1991-04-24 | 1993-06-22 | At&T Bell Laboratories | Method for making low defect density semiconductor heterostructure and devices made thereby |
JP2970425B2 (en) * | 1994-09-26 | 1999-11-02 | 日本電気株式会社 | Manufacturing method of bipolar transistor |
-
1998
- 1998-09-08 EP EP98944807A patent/EP1036412A1/en not_active Withdrawn
- 1998-09-08 CA CA002302758A patent/CA2302758A1/en not_active Abandoned
- 1998-09-08 US US09/149,191 patent/US20010006249A1/en not_active Abandoned
- 1998-09-08 JP JP2000512245A patent/JP2001516971A/en active Pending
- 1998-09-08 WO PCT/US1998/018715 patent/WO1999014804A1/en not_active Application Discontinuation
- 1998-09-08 KR KR1020007002779A patent/KR20010024041A/en not_active Application Discontinuation
-
1999
- 1999-01-04 US US09/224,720 patent/US6171936B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US20010006249A1 (en) | 2001-07-05 |
CA2302758A1 (en) | 1999-03-25 |
KR20010024041A (en) | 2001-03-26 |
WO1999014804A1 (en) | 1999-03-25 |
US6171936B1 (en) | 2001-01-09 |
EP1036412A1 (en) | 2000-09-20 |
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