JP2001337348A - Array substrate and method of manufacture thereof - Google Patents
Array substrate and method of manufacture thereofInfo
- Publication number
- JP2001337348A JP2001337348A JP2000159598A JP2000159598A JP2001337348A JP 2001337348 A JP2001337348 A JP 2001337348A JP 2000159598 A JP2000159598 A JP 2000159598A JP 2000159598 A JP2000159598 A JP 2000159598A JP 2001337348 A JP2001337348 A JP 2001337348A
- Authority
- JP
- Japan
- Prior art keywords
- array substrate
- semiconductor layer
- layer
- auxiliary capacitance
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、アレイ基板および
その製造方法に関する。The present invention relates to an array substrate and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】平面表示装置において、画素電極により
表示される表示画像を所定時間保持するための補助容量
を形成するため、アレイ基板上の画素電極と重なる領域
に走査線と平行且つ独立した補助容量線を形成し、画素
電極との間に補助容量を形成している。平面表示装置に
あっては、大画面、高精細化、高画質、開口率向上の必
要性に伴い、画素電極中に非光透過部を形成し、開口率
に著しい影響を及ぼす補助容量線の面積の低減が要求さ
れている。しかし、この補助容量線は、画素電極の電位
変動を抑えるためには、充分小さくすることが出来なか
った。2. Description of the Related Art In a flat panel display device, an auxiliary capacitor for holding a display image displayed by a pixel electrode for a predetermined period of time is formed in an area overlapping with a pixel electrode on an array substrate in parallel with and independent of a scanning line. A capacitance line is formed, and an auxiliary capacitance is formed between the capacitor line and the pixel electrode. In a flat display device, with the necessity of a large screen, high definition, high image quality, and an improvement in aperture ratio, a non-light-transmitting portion is formed in the pixel electrode, and an auxiliary capacitance line that significantly affects the aperture ratio is formed. A reduction in area is required. However, this auxiliary capacitance line could not be made sufficiently small in order to suppress the potential fluctuation of the pixel electrode.
【０００３】特開平１１−１６８１８８号公報には、上
記課題を解決するために、キャパシタの第1の導電膜の
表面に井戸状の複数の凹部を形成し、かつこの凹部の内
面に半球状のシリコン膜を形成する技術が開示されてい
る。つまり、キャパシタの導電膜の表面に複数の凹部を
形成し、実効的なキャパシタ電極の表面積を増やすこと
によって容量を増大させると共に、さらに、凹部の内部
に半球状の凹凸をシリコン膜のアニール処理により形成
し、凹部の内面の表面積がさらに増大し、充分なキャパ
シタ容量の確保が可能となる。しかしながら、上記キャ
パシタの製造を平面表示装置の画素部に適用する場合に
は、製造工程が複雑になり、歩留まりが低下する。In order to solve the above-mentioned problem, Japanese Patent Application Laid-Open No. H11-168188 discloses that a plurality of well-shaped recesses are formed on the surface of a first conductive film of a capacitor, and a hemispherical recess is formed on the inner surface of the recess. A technique for forming a silicon film has been disclosed. In other words, a plurality of concave portions are formed on the surface of the conductive film of the capacitor, the capacitance is increased by increasing the effective surface area of the capacitor electrode, and further, hemispherical irregularities are formed inside the concave portions by annealing the silicon film. As a result, the surface area of the inner surface of the concave portion is further increased, and sufficient capacitor capacity can be secured. However, when the production of the capacitor is applied to the pixel portion of the flat panel display, the production process becomes complicated, and the yield decreases.
【０００４】[0004]
【発明が解決しようとする課題】また、半球状のグレイ
ンは、アモルファスシリコンをアニール処理することに
より作成されるが、アモルファスシリコンを結晶成長さ
せて、ポリシリコンを作成する場合に、アニール処理で
は、ガラス全体を長時間高温下に曝すこととなり、例え
ば７００℃くらいの高温に耐えうるガラスを使用するこ
とになり、コストの増大を招くことになる。本発明で
は、上記技術課題に対処してなされたものであって、開
口率を保ったまま補助容量部面積を拡大するアレイ基板
およびその製造方法を提供することを目的としている。Further, hemispherical grains are formed by annealing amorphous silicon. However, in the case where amorphous silicon is crystal-grown to form polysilicon, the annealing process is performed in the following manner. The entire glass is exposed to a high temperature for a long time. For example, a glass that can withstand a high temperature of about 700 ° C. is used, which leads to an increase in cost. The present invention has been made in view of the above-mentioned technical problem, and has as its object to provide an array substrate in which the area of the auxiliary capacitance portion is increased while maintaining the aperture ratio, and a method of manufacturing the same.
【０００５】[0005]
【課題が解決するための手段】請求項１記載の発明は、
絶縁基板上にマトリクス状に配置される信号線及び走査
線の交点近傍に配置されるスイッチング素子、及び前記
信号線および前記走査線に囲まれた領域に対応して配置
される画素電極と、前記画素電極と電気的に接続される
補助容量と、を備えたアレイ基板であって、前記補助容
量は半導体層又は金属層と、絶縁膜と、電極とで構成さ
れ、前記半導体層または前記金属層の表面が凸凹構造を
もつことを特徴としている。この発明によれば、開口率
を保持したまま、補助容量の実効面積を大きくすること
が可能となる。以下、本発明の実施の形態について詳細
に説明する。According to the first aspect of the present invention,
A switching element arranged in the vicinity of an intersection of a signal line and a scanning line arranged in a matrix on an insulating substrate, and a pixel electrode arranged corresponding to a region surrounded by the signal line and the scanning line; An array substrate comprising: a storage capacitor electrically connected to a pixel electrode; wherein the storage capacitor includes a semiconductor layer or a metal layer, an insulating film, and an electrode, and includes the semiconductor layer or the metal layer. Is characterized in that its surface has an uneven structure. According to the present invention, it is possible to increase the effective area of the auxiliary capacitance while maintaining the aperture ratio. Hereinafter, embodiments of the present invention will be described in detail.
【０００６】[0006]
【発明の実施の形態】以下、本発明の実施例について平
面表示装置を例にとり、図面を参照して説明する。この
実施例の平面表示装置１００は、図１に示すように、ア
レイ基板２００と、アレイ基板２００に対向配置される
対向基板３００と、これら２枚の基板２００、３００の
間隔を保持するスペーサ２０２と、アレイ基板２００と
対向基板３００間に狭持される液晶層等の光物性層４０
０と、を備え、アレイ基板２００および対向基板３００
の外表面に偏光板２０１、３０１を備えている。対向基
板３００は、ガラス等の透明絶縁基板３１０上にITO（I
ndium Tin Oxide）膜からなる対向電極３９０を備
え、対向電極３９０表面には、配向膜３０３が形成され
る。アレイ基板２００は、ガラス等の透明絶縁基板２１
０上にほぼ平行に等間隔に配置された信号線２６０と、
それにほぼ直交し信号線２６０と層間絶縁層２５０で電
気的に絶縁されたゲート線２４０と、それらの交点付近
に配置されるスイッチ素子の薄膜トランジスタ（ＴＦ
Ｔ；Ｔｈｉｎ ｆｉｌｍ ｔｒａｎｓｉｓｔｏｒ）を介
してＩＴＯ膜からなる画素電極２９０がマトリクス状に
配置されている。このアレイ基板２００のTFT上には、
着色層２８０が設けられ、画素電極２９０は着色層２８
０上に配置されている。また、着色層２８０上の非表示
領域には、アレイ基板２００と一体的に形成されたスペ
ーサ２０２が設けられ、アレイ基板２００のスペーサ２
０２を設けた側の表面には、配向膜２０３が形成され
る。また、アレイ基板２００は信号線２６０と、ゲート
線２４０と同一材料、同一工程で配置された補助容量線
２４２とで形成される補助容量を備えている。補助容量
は、TFTのソース電極を介して画素電極２９０と接続し
ている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings, taking a flat panel display as an example. As shown in FIG. 1, the flat panel display device 100 of this embodiment includes an array substrate 200, an opposing substrate 300 that is disposed to face the array substrate 200, and a spacer 202 that keeps a space between the two substrates 200 and 300. And an optical physical layer 40 such as a liquid crystal layer sandwiched between the array substrate 200 and the counter substrate 300.
0, and the array substrate 200 and the counter substrate 300
Are provided with polarizing plates 201 and 301 on the outer surface thereof. The opposing substrate 300 is made of ITO (I) on a transparent insulating substrate 310 such as glass.
There is provided a counter electrode 390 made of a ndium tin oxide (ndium tin oxide) film, and an alignment film 303 is formed on the surface of the counter electrode 390. The array substrate 200 is made of a transparent insulating substrate 21 such as glass.
0, signal lines 260 arranged substantially in parallel at equal intervals,
A gate line 240 which is substantially orthogonal to the signal line 260 and is electrically insulated by the interlayer insulating layer 250, and a thin film transistor (TF) of a switch element arranged near the intersection thereof.
The pixel electrodes 290 made of an ITO film are arranged in a matrix via a thin film transistor (T; Thin film transistor). On the TFT of this array substrate 200,
A coloring layer 280 is provided, and the pixel electrode 290 is
0. In a non-display area on the coloring layer 280, a spacer 202 formed integrally with the array substrate 200 is provided.
An alignment film 203 is formed on the surface on the side where 02 is provided. The array substrate 200 includes an auxiliary capacitance formed by the signal line 260 and an auxiliary capacitance line 242 formed of the same material and the same process as the gate line 240. The storage capacitor is connected to the pixel electrode 290 via the source electrode of the TFT.
【０００７】図１（ｂ）に、補助容量部の略拡大図を示
す。半導体膜２２５表面は、凸凹形状となっており、そ
の上にゲート絶縁膜２３０を介して補助容量線２４２が
形成される。この凹凸は補助容量内に２組以上形成さ
れ、補助容量の表面積を増大させている。一般に容量の
大きさは、容量部の表面積に比例するので、容量部を形
成する電極、つまり半導体膜２２５の表面が凸凹形状を
とると、表面積が増大する。したがって、表面積に比例
する容量も増大する。このように、容量部の少なくとも
一方の電極、つまり半導体膜２２５または補助容量電極
２４２の少なくとも一方の表面を凸凹形状とすること
で、補助容量線の平面積を増大することなく、容量を増
大することができる。特に、本実施例のように、この補
助容量を備えたアレイ基板２００を平面表示装置１００
に適用する場合は、補助容量の平面積は一定のため、開
口率を保ったままで、補助容量を増大することができ
る。次に、本発明の一実施の形態として、平面表示装置
の製造方法について説明する。まず、アレイ基板２００
の製造工程を図２を参照しながら説明する。図２（a）
に示すように、ガラス等の透明絶縁基板２１０上に、ア
ンダーコート層２１１として、SiNxおよびＳｉＯｘの２
層を一面に塗布し、アンダーコート層２１１上に、非晶
質シリコン層２２１をプラズマCVD法を用いて５０nmの
膜厚に成膜する。FIG. 1B is a schematic enlarged view of the auxiliary capacitance section. The surface of the semiconductor film 225 has an uneven shape, and an auxiliary capacitance line 242 is formed thereon via a gate insulating film 230. Two or more sets of these irregularities are formed in the auxiliary capacitance, and increase the surface area of the auxiliary capacitance. In general, the size of the capacitor is proportional to the surface area of the capacitor portion. Therefore, when the surface of the electrode forming the capacitor portion, that is, the surface of the semiconductor film 225 has an uneven shape, the surface area increases. Therefore, the capacity proportional to the surface area also increases. In this manner, by forming at least one electrode of the capacitance portion, that is, at least one surface of the semiconductor film 225 or the auxiliary capacitance electrode 242 into an uneven shape, the capacitance can be increased without increasing the plane area of the auxiliary capacitance line. be able to. In particular, as in the present embodiment, the array substrate 200 having this auxiliary capacitance is
In this case, since the plane area of the auxiliary capacitance is constant, the auxiliary capacitance can be increased while maintaining the aperture ratio. Next, as an embodiment of the present invention, a method for manufacturing a flat panel display will be described. First, the array substrate 200
Will be described with reference to FIG. Fig. 2 (a)
As shown in FIG. 2, on a transparent insulating substrate 210 made of glass or the like, as an undercoat layer 211, two layers of SiNx and SiOx are used.
The layer is applied on one surface, and an amorphous silicon layer 221 is formed on the undercoat layer 211 to a thickness of 50 nm by a plasma CVD method.
【０００８】次に、レーザービーム５０１を用いて、非
晶質シリコンを多結晶シリコンに改質する（図２
（ｂ））。レーザービームの走査は、線状長手方向に広
げたレーザービームをパルス状に非晶質シリコン層２２
１に照射し、走査方向におよそ９０％ずつレーザービー
ムが重なるよう走査する。非晶質シリコン層２２１の照
射部は溶融し、盛り上がり、凸凹が発生し、例えば、最
も厚みの薄い領域で４０nm、厚い領域で９０nmの凹凸が
形成される。厚い領域は突起となり、急峻である。この
ように、非晶質シリコンを多結晶シリコンに改質する
際、レーザービームを不均一または不連続に走査したの
で、改質されて形成された多結晶シリコン層２２３は、
その表面が突起部２２２を有した凸凹形状となる。ここ
で、エネルギービームとしてレーザービームを用いた
が、これに限らず、イオンビーム、電子ビーム等を使用
することができる。次に、５％程度のフッ酸溶液で、ウ
ェットエッチング処理し、突起部２２２の先端を丸める
（図２（ｄ））。次に、多結晶シリコン層２２３をパタ
ーニングして、島状の半導体膜２２０を形成し、基板全
面にゲート絶縁膜２３０となるSiO2、ゲート線２４０と
なるMo及びその合金等２４２を堆積し、パターニングし
てゲート線２４０およびゲート線２４０を兼ねたゲート
電極２４１を形成する。Next, amorphous silicon is modified into polycrystalline silicon using a laser beam 501 (FIG. 2).
(B)). The laser beam is scanned by pulsing the laser beam expanded in the linear longitudinal direction into an amorphous silicon layer 22.
1 and scanning is performed so that the laser beams overlap by about 90% in the scanning direction. The irradiated portion of the amorphous silicon layer 221 is melted, swells, and has irregularities. For example, irregularities of 40 nm are formed in the thinnest region and 90 nm are formed in the thickest region. The thick region becomes a projection and is steep. As described above, when the amorphous silicon is modified into polycrystalline silicon, the laser beam is scanned non-uniformly or discontinuously, so that the modified polycrystalline silicon layer 223 is
The surface has an uneven shape having a protrusion 222. Here, a laser beam is used as the energy beam, but the present invention is not limited to this, and an ion beam, an electron beam, or the like can be used. Next, wet etching is performed with a hydrofluoric acid solution of about 5% to round off the tip of the protrusion 222 (FIG. 2D). Next, the polycrystalline silicon layer 223 is patterned to form an island-shaped semiconductor film 220, and SiO 2 serving as the gate insulating film 230, Mo serving as the gate line 240 and its alloy 242 are deposited on the entire surface of the substrate, By patterning, a gate line 240 and a gate electrode 241 serving also as the gate line 240 are formed.
【０００９】ゲート線２４０上からN型不純物の燐イオ
ンを低濃度に打ち込み、さらに、ゲート電極２４１を覆
い、半導体膜２２０の幅より狭い幅でレジストを形成
し、その上面から燐イオンを高濃度に注入して、高濃度
に注入された領域以外の箇所がLDD（lightly doped d
rain）領域２２６として形成される。次にレジストを除
去し、層間絶縁層２５０と、金属膜を堆積,パターニン
グしてドレイン電極２６２と一体的に形成された信号線
２６０、およびソース電極２６１を形成し、TFTが形成
される（図２(e)）。次に基板全面に、SiNxからなるパ
ッシベーション膜２７０を形成したあと、緑色の着色層
２８０Gを所定のパターンに露光・現像・焼成して形成
し、同様にして青色、赤色の着色層２８０B、２８０Rを
順次形成する。次に、着色層２８０及びパッシベーショ
ン膜２７０に形成された開口２７１を介してソース電極
２６１に接続する画素電極２９０を形成した後、画素電
極２９０上に黒レジストをスピンナーを用いて塗布・乾
燥後、所定のパターンに露光・現像・焼成して、スペー
サ２０２を形成した。こうして、アレイ基板２００を作
製し、さらに、アレイ基板２００のスペーサ２０２、画
素電極２９０、着色層２８０を覆う全面にポリイミドか
らなる配向膜２０３を成膜する。[0009] A low concentration of N-type impurity phosphorus ions is implanted from above the gate line 240, a resist is formed with a width smaller than the width of the semiconductor film 220 to cover the gate electrode 241, and a high concentration of phosphorus ions is formed from the upper surface thereof. And LDD (lightly doped d)
rain) region 226. Next, the resist is removed, an interlayer insulating layer 250, a metal film is deposited and patterned to form a signal line 260 formed integrally with the drain electrode 262, and a source electrode 261 to form a TFT (FIG. 2 (e)). Next, after forming a passivation film 270 made of SiNx on the entire surface of the substrate, a green colored layer 280G is formed by exposing, developing, and firing in a predetermined pattern, and blue and red colored layers 280B, 280R are formed in the same manner. Form sequentially. Next, after forming a pixel electrode 290 connected to the source electrode 261 through the opening 271 formed in the coloring layer 280 and the passivation film 270, a black resist is applied on the pixel electrode 290 using a spinner and dried. Exposure, development, and baking were performed in a predetermined pattern to form a spacer 202. Thus, the array substrate 200 is manufactured, and an alignment film 203 made of polyimide is formed on the entire surface of the array substrate 200 covering the spacer 202, the pixel electrode 290, and the coloring layer 280.
【００１０】次に、ガラス等の透明絶縁基板３１０上に
ITO膜を成膜し、対向基板３００を作製し、対向基板３
００全面にポリイミドからなる配向膜３０３を成膜す
る。アレイ基板２００の表示領域の外周辺部分にシール
材を塗布し、アレイ基板２００および対向基板３００を
それぞれの電極２９０，３９０が対向するよう貼り合
せ、これら基板２００、３００間に液晶４００を注入す
る。さらに、アレイ基板２００および対向基板３００の
外表面に偏光板２０１，３０１を配置し、液晶表示装置
１００が作製される。以上、詳述したように、補助容量
部の少なくとも一方の電極が凹凸形状となっているた
め、開口率を保持したまま、補助容量の実行面積を広げ
ることができる。また、上述の実施の形態では、液晶表
示装置を例にとり説明したが、アレイ基板および対向基
板間に光物性層として蛍光体等の発光層を設けたEL（el
ectro luminescence）ディスプレイであってもよい。
また、上述の実施の形態では、エッチングの工程は、ウ
ェットプロセスにより行ったが、ドライプロセスにより
おこなってもよい。たとえば、CDE（chemicaldry etch
ing）法やＲＩＥ（reactive ion etching）法により
行うことができ、CF4、O2等の混合ガスを用いることが
できる。Next, on a transparent insulating substrate 310 such as glass,
An ITO film is formed, and a counter substrate 300 is formed.
An alignment film 303 made of polyimide is formed on the entire surface of the substrate. A sealing material is applied to the outer peripheral portion of the display area of the array substrate 200, the array substrate 200 and the opposing substrate 300 are bonded so that the electrodes 290, 390 face each other, and a liquid crystal 400 is injected between the substrates 200, 300. . Further, polarizing plates 201 and 301 are arranged on the outer surfaces of the array substrate 200 and the counter substrate 300, and the liquid crystal display device 100 is manufactured. As described above in detail, since at least one electrode of the auxiliary capacitance portion has an uneven shape, the effective area of the auxiliary capacitance can be increased while maintaining the aperture ratio. In the above-described embodiment, the liquid crystal display device is described as an example. However, an EL (e.g., EL) in which a light-emitting layer such as a phosphor is provided as an optical physical layer between an array substrate and a counter substrate.
ectro luminescence) display.
Further, in the above-described embodiment, the etching process is performed by a wet process, but may be performed by a dry process. For example, CDE (chemical dry etch
ing) method or RIE (reactive ion etching) method, and a mixed gas such as CF 4 and O 2 can be used.
【００１１】また、エッチングは、酸素を含む雰囲気中
での４５０℃以上の熱処理により行うこともできる。ま
た、上述の実施の形態では、補助容量線を独立に設け、
補助容量線と半導体層の間で補助容量を形成している
が、例えば、前段のゲート線またはゲート電極を補助容
量線として用いるようにしてもよい。このようにして補
助容量を形成すると、さらに開口率を確保することが可
能となる。また、上述の実施の形態では、MIM型であっ
てもよい。反射型でもよい。Further, the etching can be performed by a heat treatment at 450 ° C. or more in an atmosphere containing oxygen. In the above-described embodiment, the auxiliary capacitance line is provided independently,
Although the storage capacitor is formed between the storage capacitor line and the semiconductor layer, for example, a preceding gate line or gate electrode may be used as the storage capacitor line. When the auxiliary capacitance is formed in this manner, it is possible to further secure the aperture ratio. Further, in the above embodiment, the MIM type may be used. It may be a reflection type.
【００１２】[0012]
【発明の効果】本発明によれば、開口率を変えることな
く、補助容量の実効面積が増大可能なアレイ基板および
その製造方法を提供することが出来る。According to the present invention, it is possible to provide an array substrate capable of increasing the effective area of the storage capacitor without changing the aperture ratio, and a method of manufacturing the same.
【図１】図１は、本発明の平面表示装置の一実施例を示
す概略図であり、(a)は略断面図、（ｂ）は略平面図を
示す。FIG. 1 is a schematic view showing one embodiment of a flat panel display according to the present invention, wherein (a) is a schematic sectional view and (b) is a schematic plan view.
【図２】図２は、本発明のアレイ基板の一部製造方法を
示す略断面図である。FIG. 2 is a schematic cross-sectional view showing a method for partially manufacturing an array substrate according to the present invention.
１００・・・表示装置 ２００・・・アレイ基板 ３００・・・対向基板 ４００・・・光物性層 100 display device 200 array substrate 300 counter substrate 400 optical property layer
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 29/78 ６２７Ｇ Ｆターム(参考） 2H092 JA25 JA29 JA35 JA38 JA42 JA44 JA46 JA47 JB13 JB23 JB32 JB33 JB38 JB51 JB57 JB63 JB64 JB69 KA03 KA04 KA05 KA07 KA08 MA05 MA08 MA13 MA18 MA19 MA27 MA28 MA35 MA37 MA41 NA07 NA24 NA25 PA02 PA03 QA07 5C094 AA10 AA42 AA43 BA03 BA43 CA19 DA13 EA03 EA04 EA07 EA10 FA04 FB12 FB14 FB15 FB19 GB01 5F110 AA30 BB01 CC02 DD02 DD13 DD14 DD17 EE04 EE06 EE14 FF02 GG02 GG03 GG04 GG12 GG13 GG15 GG25 GG45 HJ01 HJ13 HM15 NN02 NN24 NN72 NN73 PP01 PP05 PP08 QQ05 QQ11 5G435 AA03 AA17 BB12 CC09 HH13 HH16 KK05 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI theme coat ゛ (Reference) H01L 29/78 627G F term (Reference) 2H092 JA25 JA29 JA35 JA38 JA42 JA44 JA46 JA47 JB13 JB23 JB32 JB33 JB38 JB51 JB57 JB63 JB64 JB69 KA03 KA04 KA05 KA07 KA08 MA05 MA08 MA13 MA18 MA19 MA27 MA28 MA35 MA37 MA41 NA07 NA24 NA25 PA02 PA03 QA07 5C094 AA10 AA42 AA43 BA03 BA43 CA19 DA13 EA03 EA04 EA07 EA10 FA04 FB12 DD13 FB12 DD13 EE06 EE14 FF02 GG02 GG03 GG04 GG12 GG13 GG15 GG25 GG45 HJ01 HJ13 HM15 NN02 NN24 NN72 NN73 PP01 PP05 PP08 QQ05 QQ11 5G435 AA03 AA17 BB12 CC09 HH13 HH16 KK05
Claims (6)
信号線及び走査線の交点近傍に配置されるスイッチング
素子、及び前記信号線および前記走査線に囲まれた領域
に対応して配置される画素電極と、前記画素電極と電気
的に接続される補助容量と、を備えたアレイ基板であっ
て、前記補助容量は半導体層又は金属層と、絶縁膜と、
電極とで構成され、前記半導体層または前記金属層の表
面が凸凹構造をもつことを特徴とするアレイ基板。1. A switching element arranged near an intersection of a signal line and a scanning line arranged in a matrix on an insulating substrate, and arranged corresponding to a region surrounded by the signal line and the scanning line. A pixel electrode, an array substrate including an auxiliary capacitor electrically connected to the pixel electrode, wherein the auxiliary capacitor is a semiconductor layer or a metal layer, an insulating film,
And an electrode, wherein the surface of the semiconductor layer or the metal layer has an uneven structure.
に２組以上存在することを特徴とする請求項１記載のア
レイ基板。2. The array substrate according to claim 1, wherein two or more sets of the unevenness of the uneven structure exist in the auxiliary capacitance.
ム、ガリウム砒素などの半導体物質の単結晶、多結晶ま
たは非晶質層であり、不純物を含むことを特徴とする請
求項１記載のアレイ基板。3. The array substrate according to claim 1, wherein the semiconductor layer is a single crystal, polycrystal, or amorphous layer of a semiconductor material such as silicon, germanium, and gallium arsenide, and contains an impurity.
板の製造方法において、前記絶縁基板上に半導体層を形
成する工程と、前記半導体層上にエネルギービームを不
均一または不連続に走査する工程と、前記絶縁基板上に
前記半導体層を覆って絶縁膜を配置する工程と、前記半
導体層上に前記絶縁膜を介して導電層を形成する工程
と、を有することを特徴としたアレイ基板の製造方法。4. A method of manufacturing an array substrate provided with an auxiliary capacitor on an insulating substrate, wherein a semiconductor layer is formed on the insulating substrate, and an energy beam is scanned non-uniformly or discontinuously on the semiconductor layer. An array substrate, comprising: a step of arranging an insulating film on the insulating substrate so as to cover the semiconductor layer; and a step of forming a conductive layer on the semiconductor layer via the insulating film. Manufacturing method.
連続に走査する工程の後に、前記絶縁基板をエッチング
する工程を備え、前記走査する工程により前記半導体層
に形成された突起をエッチングすることを特徴とする請
求項４記載のアレイ基板の製造方法。5. The method according to claim 1, further comprising, after the step of scanning the energy beam non-uniformly or discontinuously, a step of etching the insulating substrate, wherein the projection formed on the semiconductor layer is etched by the scanning step. The method for manufacturing an array substrate according to claim 4, wherein
ム、イオンビーム、電子ビームのいずれかであることを
特徴とする請求項４記載のアレイ基板の製造方法。6. The method according to claim 4, wherein the energy beam is one of a laser beam, an ion beam, and an electron beam.
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|---|---|---|---|
| JP2000159598A JP2001337348A (en) | 2000-05-30 | 2000-05-30 | Array substrate and method of manufacture thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000159598A JP2001337348A (en) | 2000-05-30 | 2000-05-30 | Array substrate and method of manufacture thereof |
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|---|---|
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Family
ID=18663899
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| Country | Link |
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Cited By (8)
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|---|---|---|---|---|
| KR100603284B1 (en) * | 2002-10-22 | 2006-07-20 | 삼성에스디아이 주식회사 | Electroluminescent display panel wherein capacitance is increased |
| JP2007140463A (en) * | 2005-11-23 | 2007-06-07 | Samsung Sdi Co Ltd | Liquid crystal display array board and method of fabricating same |
| US7612377B2 (en) | 2005-01-31 | 2009-11-03 | Samsung Electronics Co., Ltd. | Thin film transistor array panel with enhanced storage capacitors |
| KR101041141B1 (en) | 2009-03-03 | 2011-06-13 | 삼성모바일디스플레이주식회사 | organic light emitting display device and the fabricating method of the same |
| US8048783B2 (en) | 2009-03-05 | 2011-11-01 | Samsung Mobile Display Co., Ltd. | Method of forming polycrystalline silicon layer and atomic layer deposition apparatus used for the same |
| JP2013235082A (en) * | 2012-05-08 | 2013-11-21 | Seiko Epson Corp | Manufacturing method of electro-optic device, electro-optic device, and electronic apparatus |
| US8890165B2 (en) | 2009-11-13 | 2014-11-18 | Samsung Display Co., Ltd. | Method of forming polycrystalline silicon layer, thin film transistor, organic light emitting diode display device having the same, and methods of fabricating the same |
| US9117798B2 (en) | 2009-03-27 | 2015-08-25 | Samsung Display Co., Ltd. | Thin film transistor, method of fabricating the same and organic light emitting diode display device including the same |
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Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100603284B1 (en) * | 2002-10-22 | 2006-07-20 | 삼성에스디아이 주식회사 | Electroluminescent display panel wherein capacitance is increased |
| US7612377B2 (en) | 2005-01-31 | 2009-11-03 | Samsung Electronics Co., Ltd. | Thin film transistor array panel with enhanced storage capacitors |
| JP2007140463A (en) * | 2005-11-23 | 2007-06-07 | Samsung Sdi Co Ltd | Liquid crystal display array board and method of fabricating same |
| KR100754126B1 (en) * | 2005-11-23 | 2007-08-30 | 삼성에스디아이 주식회사 | array board of Liquid Crystal Display and fabrication method thereof |
| US7868338B2 (en) | 2005-11-23 | 2011-01-11 | Samsung Mobile Display Co., Ltd. | Liquid crystal display array board and method of fabricating the same |
| EP2226845A3 (en) * | 2009-03-03 | 2014-04-02 | Samsung Display Co., Ltd. | Organic light emitting diode display device and method of fabricating the same |
| KR101041141B1 (en) | 2009-03-03 | 2011-06-13 | 삼성모바일디스플레이주식회사 | organic light emitting display device and the fabricating method of the same |
| US8409887B2 (en) | 2009-03-03 | 2013-04-02 | Samsung Display Co., Ltd. | Organic light emitting diode display device and method of fabricating the same |
| US9035311B2 (en) | 2009-03-03 | 2015-05-19 | Samsung Display Co., Ltd. | Organic light emitting diode display device and method of fabricating the same |
| US8048783B2 (en) | 2009-03-05 | 2011-11-01 | Samsung Mobile Display Co., Ltd. | Method of forming polycrystalline silicon layer and atomic layer deposition apparatus used for the same |
| US8546248B2 (en) | 2009-03-05 | 2013-10-01 | Samsung Display Co., Ltd. | Method of forming polycrystalline silicon layer and atomic layer deposition apparatus used for the same |
| US9117798B2 (en) | 2009-03-27 | 2015-08-25 | Samsung Display Co., Ltd. | Thin film transistor, method of fabricating the same and organic light emitting diode display device including the same |
| US8890165B2 (en) | 2009-11-13 | 2014-11-18 | Samsung Display Co., Ltd. | Method of forming polycrystalline silicon layer, thin film transistor, organic light emitting diode display device having the same, and methods of fabricating the same |
| JP2013235082A (en) * | 2012-05-08 | 2013-11-21 | Seiko Epson Corp | Manufacturing method of electro-optic device, electro-optic device, and electronic apparatus |
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