JP2001319945A - Board for mounting electronic part - Google Patents
Board for mounting electronic partInfo
- Publication number
- JP2001319945A JP2001319945A JP2001052472A JP2001052472A JP2001319945A JP 2001319945 A JP2001319945 A JP 2001319945A JP 2001052472 A JP2001052472 A JP 2001052472A JP 2001052472 A JP2001052472 A JP 2001052472A JP 2001319945 A JP2001319945 A JP 2001319945A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- bonding pad
- electronic component
- wall
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10125—Reinforcing structures
- H01L2224/10126—Bump collar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【技術分野】本発明は，電子部品搭載用基板に関し，特
にボンディングパッドの接続構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for mounting electronic components, and more particularly to a connection structure for bonding pads.
【０００２】[0002]
【従来技術】従来，電子部品搭載用基板としては，図１
２に示すごとく，絶縁基板９４に電子部品９７９を搭載
するための搭載用凹部９７を設け，その周囲にボンディ
ングパッド９５，９３５及び導体パターン９３１を形成
したものがある。搭載用凹部９７の壁面には壁面パター
ン９６が設けられ，その一端はボンディングパッド９５
の接続端部９２０と接続している。他のボンディングパ
ッド９３５は導体パターン９３１と接続している。2. Description of the Related Art Conventionally, as a substrate for mounting electronic parts, FIG.
As shown in FIG. 2, a mounting recess 97 for mounting an electronic component 979 is provided on an insulating substrate 94, and bonding pads 95, 935 and a conductor pattern 931 are formed around the mounting recess 97. A wall pattern 96 is provided on the wall surface of the mounting recess 97, and one end thereof is provided with a bonding pad 95.
Is connected to the connection end portion 920. Another bonding pad 935 is connected to the conductor pattern 931.
【０００３】導体パターン９３１及びボンディングパッ
ド９５，９３５は，一般に銅箔のエッチングにより形成
される。これらの表面は銅メッキ膜により被覆されてい
る。ボンディングパッド９５，９３５は銅メッキ膜上に
更にニッケル金めっき膜を形成している。The conductor pattern 931 and the bonding pads 95 and 935 are generally formed by etching a copper foil. These surfaces are covered with a copper plating film. The bonding pads 95 and 935 further form a nickel gold plating film on the copper plating film.
【０００４】上記導体パターン，ボンディングパッド及
び壁面パターンを形成するに当たっては，絶縁基板の表
面全体を被覆する銅箔に対して，パターン形成部以外の
部分をエッチングにより除去し，次いで，絶縁基板の表
面全体に無電解メッキを行い不要部分をソフトエッチン
グにより除去する。次いで，表面をソルダーレジストに
より被覆した後，ボンディングパッド部分を開口させそ
の内部に金メッキ膜を形成する。In forming the conductor pattern, the bonding pad and the wall surface pattern, portions of the copper foil covering the entire surface of the insulating substrate other than the pattern forming portion are removed by etching, and then the surface of the insulating substrate is removed. The whole is subjected to electroless plating, and unnecessary portions are removed by soft etching. Next, after the surface is covered with a solder resist, a bonding pad portion is opened and a gold plating film is formed therein.
【０００５】[0005]
【解決しようとする課題】しかしながら，図１２に示す
ごとく，ボンディングパッド９５の金属メッキ膜をエッ
チングするときに，搭載用凹部９７の開口段部９５９に
応力が集中しやすい。このため，開口段部９５９に位置
する，ボンディングパッド９５と壁面パターン９６との
接続端部９２０が侵食されやすく，細幅になる傾向にあ
る。このため，回路のインダクタンスを低く安定に抑え
ることが困難になり，また，接続端部９２０にクラック
が発生しやすくなる。これにより，ボンディングパッド
９５の電気接続信頼性が低下するおそれがある。However, as shown in FIG. 12, when the metal plating film of the bonding pad 95 is etched, stress tends to concentrate on the opening step 959 of the mounting concave portion 97. For this reason, the connection end 920 between the bonding pad 95 and the wall pattern 96 located at the opening step 959 tends to be eroded, and tends to be narrow. For this reason, it is difficult to suppress the inductance of the circuit low and stably, and a crack is easily generated at the connection end 920. As a result, the electrical connection reliability of the bonding pad 95 may be reduced.
【０００６】本発明はかかる従来の問題点に鑑み，電気
特性が高く，かつ壁面パターンとボンディングパッドと
の電気接続信頼性に優れた電子部品搭載用基板を提供し
ようとするものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has as its object to provide an electronic component mounting board having high electric characteristics and excellent electric connection reliability between a wall pattern and a bonding pad.
【０００７】[0007]
【課題の解決手段】請求項１の発明は，電子部品を搭載
するための搭載用凹部と，該搭載用凹部の側壁に設けた
壁面パターンと，該壁面パターンと接続したボンディン
グパッドとを有する電子部品搭載用基板において，上記
壁面パターンと上記ボンディングパッドとの間は，搭載
用凹部の開口段部に沿って延びる帯状パターンにより接
続されていることを特徴とする電子部品搭載用基板であ
る。According to the first aspect of the present invention, there is provided an electronic device having a mounting recess for mounting an electronic component, a wall pattern provided on a side wall of the mounting recess, and a bonding pad connected to the wall pattern. In the component mounting board, the electronic component mounting board is characterized in that the wall pattern and the bonding pad are connected by a band-shaped pattern extending along the opening step of the mounting recess.
【０００８】本発明においては，搭載用凹部の開口段部
に帯状パターンを設け，その搭載用凹部側は壁面パター
ン上端部と接続し，その基板周縁側はボンディングパッ
ドと接続している。そのため，応力が集中しやすい搭載
用凹部の開口段部は，壁面パターンと帯状パターンによ
り被覆されることになる。それゆえ，開口段部が補強さ
れ，パターン侵食を抑制することができる。したがっ
て，本発明によれば，壁面パターンとボンディングパッ
ドとの間の電気的接続性が確保され，電気特性の信頼性
が向上する。In the present invention, a band-shaped pattern is provided at the opening step of the mounting recess, the mounting recess side is connected to the upper end of the wall pattern, and the substrate peripheral side is connected to the bonding pad. For this reason, the opening step of the mounting concave portion where stress tends to concentrate is covered with the wall surface pattern and the band-shaped pattern. Therefore, the opening step is reinforced and the pattern erosion can be suppressed. Therefore, according to the present invention, electrical connectivity between the wall surface pattern and the bonding pad is ensured, and the reliability of electrical characteristics is improved.
【０００９】帯状パターンはボンディングパッドと同一
面に形成され，互いに電気的に接続している。また，帯
状パターンは，壁面パターンの上端部と接続している。
したがって，壁面パターンと帯状パターンとボンディン
グパッドとは互いに電気的に接続している。The strip pattern is formed on the same surface as the bonding pad, and is electrically connected to each other. The strip pattern is connected to the upper end of the wall pattern.
Therefore, the wall pattern, the strip pattern, and the bonding pad are electrically connected to each other.
【００１０】帯状パターンは，ボンディングパッドの搭
載用凹部側から，開口段部に沿って延設されている。ボ
ンディングパッドの搭載用凹部側からの帯状パターンの
ボンディングパッド間の長さＬは，５０μｍ以上である
ことが好ましい（図２参照）。５０μｍ未満の場合に
は，搭載用凹部の開口段部の補強効果が低下し，壁面パ
ターンと帯状パターンとの間のパターン侵食を抑制する
ことができないおそれがある。The band-shaped pattern extends from the mounting recess side of the bonding pad along the opening step. It is preferable that the length L between the bonding pads of the strip pattern from the mounting recess side of the bonding pads is 50 μm or more (see FIG. 2). If it is less than 50 μm, the effect of reinforcing the stepped portion of the mounting recess decreases, and there is a possibility that pattern erosion between the wall pattern and the strip pattern cannot be suppressed.
【００１１】請求項２の発明のように，上記帯状パター
ンは，隣接するボンディングパッドの間を連結している
ことが好ましい。これにより，開口段部が一層補強され
る。このため，壁面パターンと帯状パターンとの間のパ
ターン侵食を効果的に抑制することができる。It is preferable that the belt-shaped pattern connects adjacent bonding pads. Thereby, the opening step is further reinforced. For this reason, pattern erosion between the wall surface pattern and the strip pattern can be effectively suppressed.
【００１２】請求項３の発明のように，上記帯状パター
ンは，搭載用凹部の開口段部の全周を被覆して形成され
ていることが好ましい。これにより，搭載用凹部の開口
段部が一層補強される。このため，壁面パターンと帯状
パターンとの間のパターン侵食を効果的に抑制すること
ができる。Preferably, the belt-like pattern is formed so as to cover the entire periphery of the opening step of the mounting recess. Thereby, the opening step of the mounting concave portion is further reinforced. For this reason, pattern erosion between the wall surface pattern and the strip pattern can be effectively suppressed.
【００１３】上記帯状パターンの幅Ｍは，５〜７００μ
ｍであることが好ましい。５μｍ未満の場合には，搭載
用凹部の開口段部にパターン侵食が発生するおそれがあ
り，７００μｍを超える場合には，搭載用凹部周辺の高
密度配線が妨げられるおそれがある。The width M of the strip pattern is 5 to 700 μm.
m is preferable. If it is less than 5 μm, pattern erosion may occur at the step of the mounting recess, and if it exceeds 700 μm, high-density wiring around the mounting recess may be hindered.
【００１４】帯状パターンは，セミアディティブ法，ア
ディティブ法，サブトラクティブ法などにより形成する
ことができる。帯状パターンは，例えば，ボンディング
パッドや壁面パターンとともに形成することもできる。The strip pattern can be formed by a semi-additive method, an additive method, a subtractive method, or the like. The strip pattern can be formed, for example, together with a bonding pad or a wall pattern.
【００１５】壁面パターンは，搭載用凹部の壁面に幅広
に形成されていることが好ましい。更に，壁面パターン
は，帯状パターンの長さよりも広い幅に形成されている
ことが好ましい。これにより，開口段部におけるパター
ン侵食をより効果的に防止することができる。また，壁
面パターンは，搭載用凹部の全面に設けられていてもよ
い。壁面パターンは，接地回路または電源回路であるこ
とが好ましい。これにより，低インダクタンス回路にす
ることができる。また，壁面パターンは，信号回路であ
ってもよい。The wall pattern is preferably formed wide on the wall surface of the mounting recess. Further, the wall pattern is preferably formed to have a width wider than the length of the strip pattern. Thus, pattern erosion at the opening step can be more effectively prevented. Further, the wall surface pattern may be provided on the entire surface of the mounting concave portion. The wall pattern is preferably a ground circuit or a power supply circuit. Thereby, a low inductance circuit can be obtained. Further, the wall pattern may be a signal circuit.
【００１６】ボンディングパッドにおける，帯状パター
ンと接続している接続端部の幅は，基板周縁側端部の幅
よりも大きいことが好ましい。これにより，接続端部が
エッチングの際に侵食されたとしても接続端部に十分な
幅を残すことができ，ボンディングパッドと帯状パター
ンとの電気的接続信頼性が更に向上する。It is preferable that the width of the connection end of the bonding pad connected to the belt-shaped pattern is larger than the width of the edge on the peripheral edge of the substrate. As a result, even if the connection end is eroded during etching, a sufficient width can be left at the connection end, and the electrical connection reliability between the bonding pad and the strip pattern is further improved.
【００１７】請求項４の発明のように，上記ボンディン
グパッドは，曲線部を有することが好ましい。曲線部
は，ボンディングパッドの外形が曲線である部分をい
う。曲線部は直線部に比べて，応力が局部に集中しにく
い。このため，ボンディングパッドに応力集中による亀
裂が生じにくくなる。また，耐熱衝撃性も向上する。し
たがって，壁面パターンとボンディングパッドとの間の
電気的接続性がより一層確保される。ボンディングパッ
ドの外形は，すべてが曲線であってもよいし，一部分の
みが曲線であってもよい。It is preferable that the bonding pad has a curved portion. The curved portion is a portion where the outer shape of the bonding pad is a curved line. In the curved part, stress is less likely to concentrate on a local part than in the straight part. For this reason, cracks due to stress concentration are less likely to occur in the bonding pad. Also, the thermal shock resistance is improved. Therefore, electrical connectivity between the wall pattern and the bonding pad is further ensured. The outer shape of the bonding pad may be entirely curved or only a portion may be curved.
【００１８】請求項５の発明のように，上記ボンディン
グパッドにおける少なくとも上記帯状パターンと接続す
る接続部分は，曲線部であることが好ましい。上記接続
部分は，応力が集中しやすい部分である。この部分を曲
線にすることにより，応力集中を緩和でき，亀裂の発生
を抑制することができる。According to a fifth aspect of the present invention, it is preferable that at least a connection portion of the bonding pad connected to the band-shaped pattern is a curved portion. The connection portion is a portion where stress tends to concentrate. By making this portion a curve, stress concentration can be alleviated, and generation of cracks can be suppressed.
【００１９】請求項６の発明のように，上記ボンディン
グパッドにおける上記接続部分は，上記帯状パターンに
向けて曲線によって徐々に拡大している曲線部からなる
ことが好ましい。これにより，この接続部分の集中応力
を緩和でき，亀裂の発生を効果的に抑制することができ
る。According to a sixth aspect of the present invention, it is preferable that the connection portion in the bonding pad is formed of a curved portion which is gradually enlarged by a curve toward the band-shaped pattern. Thereby, the concentrated stress at the connection portion can be reduced, and the generation of cracks can be effectively suppressed.
【００２０】請求項７の発明のように，上記ボンディン
グパッドは，半円体または半楕円体であることが好まし
い。半円体は，円の中心を通る直線で半分に切断した形
状である。半楕円は，楕円の短軸又は長軸のいずれかで
半分に切断した形状である。ボンディングパッドが半円
または半楕円であることにより，ボンディングパッドに
おける上記帯状パターンと接続する部分だけでなく，ボ
ンディングパッドの全体が曲線により形成されることに
なるため，ボンディングパッドの全体に亀裂が発生しに
くい形状となる。ボンディングパッド全体に亀裂が発生
することを効果的に抑制することができる。ボンディン
グパッドが半楕円の場合，ボンディングパッドは，半楕
円の長軸が帯状パターンの幅方向に沿うように配置され
ていることが好ましい。これにより，ボンディングパッ
ドを多数配置することができる。Preferably, the bonding pad has a semicircular shape or a semielliptical shape. A semicircle has a shape cut in half by a straight line passing through the center of the circle. A semi-ellipse is a shape cut in half by either the short axis or the long axis of the ellipse. When the bonding pad is semicircular or semi-elliptical, not only the portion of the bonding pad connected to the above-mentioned band-shaped pattern, but also the entire bonding pad is formed by a curve, so that the entire bonding pad is cracked. It becomes a shape that is difficult to do. The generation of cracks in the entire bonding pad can be effectively suppressed. When the bonding pad is semi-elliptical, it is preferable that the bonding pad is arranged such that the major axis of the semi-ellipse is along the width direction of the band-shaped pattern. Thereby, a large number of bonding pads can be arranged.
【００２１】請求項８の発明のように，上記ボンディン
グパッドは，上記帯状パターンの側に位置し該帯状パタ
ーンに向かって幅広に広がる曲線部と，上記帯状パター
ンと反対側に位置する長尺部とからなることが好まし
い。これにより，ボンディングパッドにおける帯状パタ
ーンとの接続端部の応力集中を緩和でき，亀裂発生を抑
制することができる。According to the present invention, the bonding pad includes a curved portion located on the side of the band-shaped pattern and widened toward the band-shaped pattern, and a long portion located on the side opposite to the band-shaped pattern. And preferably As a result, the stress concentration at the connection end of the bonding pad with the belt-shaped pattern can be reduced, and the occurrence of cracks can be suppressed.
【００２２】請求項９の発明は，電子部品を搭載するた
めの搭載用凹部と，該搭載用凹部の側壁に設けた壁面パ
ターンと，該壁面パターンと接続したボンディングパッ
ドとを有する電子部品搭載用基板において，上記ボンデ
ィングパッドは，曲線部を有することである。According to a ninth aspect of the present invention, there is provided an electronic component mounting device having a mounting recess for mounting an electronic component, a wall pattern provided on a side wall of the mounting recess, and a bonding pad connected to the wall pattern. In the substrate, the bonding pad has a curved portion.
【００２３】本発明は，上記請求項１〜８の発明のよう
な帯状パターンがなく，.壁面パターンとボンディング
パッドとが直接接続している。ボンディングパッドの曲
線部は直線部に比べて，応力が局部に集中しにくい。こ
のため，ボンディングパッドに応力集中による亀裂が生
じにくくなる。また，耐熱衝撃性も向上する。したがっ
て，壁面パターンとボンディングパッドとの間の電気的
接続性がより一層確保される。According to the present invention, there is no belt-like pattern as in the first to eighth aspects of the present invention, and the wall pattern and the bonding pad are directly connected. In the curved portion of the bonding pad, stress is less likely to concentrate on a local portion than in the straight portion. For this reason, cracks due to stress concentration are less likely to occur in the bonding pad. Also, the thermal shock resistance is improved. Therefore, electrical connectivity between the wall pattern and the bonding pad is further ensured.
【００２４】請求項１０の発明のように，上記ボンディ
ングパッドにおける少なくとも上記壁面パターンと接続
する接続部分は，曲線部であることが好ましい。これに
より，上記壁面パターンと交わる部分の応力集中を緩和
でき，亀裂の発生を抑制することができる。According to a tenth aspect of the present invention, it is preferable that at least a connection portion of the bonding pad connected to the wall pattern is a curved portion. As a result, stress concentration at a portion intersecting with the wall surface pattern can be reduced, and generation of a crack can be suppressed.
【００２５】請求項１１の発明のように，上記ボンディ
ングパッドにおける上記接続部分は，上記壁面パターン
に向けて曲線によって徐々に拡大している曲線部からな
ることが好ましい。これにより，この接続部分の集中応
力を緩和でき，亀裂の発生を効果的に抑制することがで
きる。[0025] As in the eleventh aspect of the present invention, it is preferable that the connection portion in the bonding pad is formed of a curved portion gradually expanding by a curve toward the wall surface pattern. Thereby, the concentrated stress at the connection portion can be reduced, and the generation of cracks can be effectively suppressed.
【００２６】請求項１２の発明のように，上記ボンディ
ングパッドは，半円体または半楕円体であることが好ま
しい。これにより，ボンディングパッドの亀裂発生を効
果的に抑制することができる。As in the twelfth aspect of the present invention, the bonding pad is preferably a semicircle or a semiellipse. Thereby, the occurrence of cracks in the bonding pad can be effectively suppressed.
【００２７】請求項１３の発明のように，上記ボンディ
ングパッドは，上記壁面パターンの側に位置し該壁面パ
ターンに向かって幅広に広がる曲線部と，上記壁面パタ
ーンと反対側に位置する長尺部とからなることが好まし
い。これにより，ボンディングパッドにおける帯状パタ
ーンとの接続端部の亀裂を抑制することができる。According to a thirteenth aspect of the present invention, the bonding pad includes a curved portion located on the side of the wall pattern and widened toward the wall pattern, and a long portion located on the opposite side to the wall pattern. And preferably Thereby, the crack at the connection end of the bonding pad with the strip pattern can be suppressed.
【００２８】[0028]
【発明の実施の形態】実施形態例１ 本発明の実施形態に係る電子部品搭載用基板について図
１〜図４を用いて説明する。本例の電子部品搭載用基板
は，図１に示すごとく，電子部品を搭載するための搭載
用凹部７と，搭載用凹部７の側壁に設けた壁面パターン
６と，壁面パターン６と接続したボンディングパッド５
とを有する。壁面パターン６とボンディングパッド５と
の間は，搭載用凹部７の開口段部２１に沿って延びる帯
状パターン１により接続されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 An electronic component mounting board according to an embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, the electronic component mounting board of this embodiment has a mounting recess 7 for mounting an electronic component, a wall pattern 6 provided on a side wall of the mounting recess 7, and a bonding connected to the wall pattern 6. Pad 5
And The wall pattern 6 and the bonding pad 5 are connected by the strip pattern 1 extending along the opening step 21 of the mounting recess 7.
【００２９】帯状パターン１は，隣接するボンディング
パッド５の間を連結している。帯状パターン１は，搭載
用凹部７の開口段部２１の全部を被覆して形成されてい
る。壁面パターン６は，搭載用凹部７の全面を被覆して
いる。壁面パターン６は，電子部品搭載用基板の内部の
導体パターン３２と接続している。The strip pattern 1 connects adjacent bonding pads 5. The band-shaped pattern 1 is formed so as to cover the entire opening step 21 of the mounting recess 7. The wall pattern 6 covers the entire surface of the mounting recess 7. The wall pattern 6 is connected to the conductor pattern 32 inside the electronic component mounting board.
【００３０】帯状パターン１の幅Ｍは５０μｍである。
ボンディングパッド５のピッチＬは１５０μｍであり，
帯状パターン１は，隣接するボンディングパッド５の間
を連結している。ボンディングパッド５は，幅が５０μ
ｍで，長さが６００μｍの短冊形状であり，ピッチ１５
０μｍの間隔に設けられている。The width M of the strip pattern 1 is 50 μm.
The pitch L of the bonding pads 5 is 150 μm,
The strip pattern 1 connects adjacent bonding pads 5. The bonding pad 5 has a width of 50 μm.
m, a strip shape with a length of 600 μm, pitch 15
They are provided at intervals of 0 μm.
【００３１】図２に示す電子部品搭載用基板は，複数の
絶縁基板４０および導体パターン３２を積層した多段の
スタジアム構造を有する多層基板４からなる。各絶縁基
板４０は，搭載用凹部７に階段状に開口する開口部７０
を有している。多層基板４の表面には，上記の壁面パタ
ーン６と接続しているボンディングパッド５の他に，導
体パターン３１と接続しているボンディングパッド３５
が設けられている。ボンディングパッド３５は，ボンデ
ィングパッド５の間に配置されている。壁面パターン６
は接地回路であり，導体パターン３１は信号回路であ
る。図３に示すごとく，搭載用凹部７には電子部品７９
が搭載されている。搭載された電子部品７９は，ボンデ
ィングワイヤー７８により，ボンディングパッド５，３
５と電気的に接続される。The electronic component mounting substrate shown in FIG. 2 comprises a multilayer substrate 4 having a multi-stage stadium structure in which a plurality of insulating substrates 40 and conductor patterns 32 are laminated. Each insulating substrate 40 has an opening 70 that opens in a step-like manner in the mounting recess 7.
have. On the surface of the multilayer substrate 4, in addition to the bonding pads 5 connected to the wall pattern 6, bonding pads 35 connected to the conductor pattern 31 are provided.
Is provided. The bonding pads 35 are arranged between the bonding pads 5. Wall pattern 6
Is a ground circuit, and the conductor pattern 31 is a signal circuit. As shown in FIG. 3, the electronic component 79 is provided in the mounting recess 7.
Is installed. The mounted electronic component 79 is connected to the bonding pads 5 and 3 by the bonding wire 78.
5 is electrically connected.
【００３２】次に，上記電子部品搭載用基板の製造方法
について，図１，図２，図４を用いて説明する。図４
は，壁面パターンと接続するボンディングパッドの形成
工程を示す図である。同図において，左側の図４（Ａ）
〜（Ｆ）は，上記形成工程におけるボンディングパッド
形成部の断面図であり，右側の図４（ａ）〜（ｆ）はそ
の平面図である。Next, a method of manufacturing the electronic component mounting board will be described with reference to FIGS. FIG.
FIG. 4 is a view showing a process of forming a bonding pad connected to a wall surface pattern. In the figure, FIG.
4 (F) to 4 (F) are cross-sectional views of the bonding pad forming portion in the above forming step, and FIGS. 4 (a) to 4 (f) on the right are plan views thereof.
【００３３】まず，ガラスエポキシ樹脂からなる絶縁基
板に銅箔を貼着し，搭載用凹部形成用の開口部７０及び
ビアホールを穿設する。次に，銅箔をエッチングして内
部用の導体パターンを形成する。次に，図２に示すごと
く，絶縁基板４０を必要枚数積層し圧着して多層基板４
を得る。First, a copper foil is adhered to an insulating substrate made of a glass epoxy resin, and an opening 70 for forming a mounting concave portion and a via hole are formed. Next, the copper foil is etched to form an internal conductor pattern. Next, as shown in FIG.
Get.
【００３４】次に，図４（Ａ），図４（ａ），図１に示
すごとく，多層基板４の表面の銅箔をエッチングして，
外部用の導体パターン３１，ボンディングパッド５，３
５及び帯状パターン１を形成する。このとき，ボンディ
ングパッド５，３５は，仕上がり形状よりも若干大きい
サイズとすることが好ましい。後工程のエッチングの際
にボンディングパッドの周囲が削られても，ワイヤーボ
ンディングのための十分な面積を確保するためである。Next, as shown in FIGS. 4A, 4A and 1, the copper foil on the surface of the multilayer substrate 4 is etched,
External conductor pattern 31, bonding pads 5, 3
5 and a band-shaped pattern 1 are formed. At this time, it is preferable that the bonding pads 5 and 35 have a size slightly larger than the finished shape. This is to ensure a sufficient area for wire bonding even if the periphery of the bonding pad is shaved during etching in a later step.
【００３５】次に，図４（Ｂ），図４（ｂ）に示すごと
く，無電解銅メッキを施して，開口部７０及びビアホー
ルの内部を含めて多層基板４の全面に薄層銅メッキ層５
１を形成する。開口部７０の壁面に形成された薄層銅メ
ッキ層５１は壁面パターン６となる。Next, as shown in FIGS. 4 (B) and 4 (b), electroless copper plating is performed, and a thin copper plating layer is formed on the entire surface of the multilayer substrate 4 including the opening 70 and the inside of the via hole. 5
Form one. The thin copper plating layer 51 formed on the wall surface of the opening 70 becomes the wall pattern 6.
【００３６】次に，図４（Ｃ），図４（ｃ）に示すごと
く，薄層銅メッキ層５１における各種パターンを形成し
ていない部分を，ソフトエッチングにより除去する。次
に，図４（Ｄ），図４（ｄ）に示すごとく，電解銅メッ
キを施して薄層銅メッキ層５１の表面に厚膜メッキ層５
２を形成する。Next, as shown in FIGS. 4C and 4C, portions of the thin copper plating layer 51 where various patterns are not formed are removed by soft etching. Next, as shown in FIGS. 4D and 4D, electrolytic copper plating is applied to the surface of the thin copper plating layer 51 to form a thick film plating layer 5 on the surface thereof.
Form 2
【００３７】次に，図４（Ｅ），図４（ｅ）に示すごと
く，多層基板４の表面に，ボンディングパッド５，３５
及び帯状パターン１を露出させたまま，ソルダーレジス
ト８を被覆する。露出させたボンディングパッド５，３
５及び帯状パターン１の表面に，ニッケル−金メッキ膜
５３を形成する。その後，必要に応じて半田ボールの接
合，導体ピンの装着などを行う。以上により，電子部品
搭載用基板を得る。Next, as shown in FIGS. 4E and 4E, bonding pads 5 and 35 are formed on the surface of the multilayer substrate 4.
Then, the solder resist 8 is covered while the strip pattern 1 is exposed. Exposed bonding pads 5,3
A nickel-gold plating film 53 is formed on the surface of the band 5 and the belt-shaped pattern 1. After that, bonding of solder balls, mounting of conductive pins, and the like are performed as necessary. Thus, a substrate for mounting electronic components is obtained.
【００３８】次に，本例の作用および効果について説明
する。本例においては，図１に示すごとく，応力が集中
しやすい開口段部２１は，壁面パターン６と帯状パター
ン１により被覆されている。それゆえ，開口段部２１が
補強され，パターン侵食を抑制することができる。した
がって，本例によれば，壁面パターン６とボンディング
パッド５との間の電気的接続性が確保され，電気特性の
信頼性が向上する。Next, the operation and effect of this embodiment will be described. In this example, as shown in FIG. 1, the opening step portion 21 where stress tends to concentrate is covered with the wall surface pattern 6 and the band-shaped pattern 1. Therefore, the opening step 21 is reinforced and the pattern erosion can be suppressed. Therefore, according to the present example, electrical connectivity between the wall surface pattern 6 and the bonding pad 5 is ensured, and the reliability of electrical characteristics is improved.
【００３９】実施形態例２ 本例においては，図５に示すごとく，ボンディングパッ
ド５における，帯状パターン１と接続している接続端部
２００の幅Ａが１１０μｍであり，基板周縁側端部２５
０の幅ａは５０μｍである。その他は，実施形態例１と
同様である。ボンディングパッド５における，帯状パタ
ーン１と接続している接続端部２００の幅Ａは，基板周
縁側端部２５０の幅ａよりも大きい。そのため，接続端
部２００がエッチングの際に侵食されたとしても接続端
部２００に十分な幅を残すことができ，ボンディングパ
ッド５と帯状パターン１との電気的接続信頼性が更に向
上する。その他，本例においても，実施形態例１と同様
の効果を発揮することができる。Embodiment 2 In this embodiment, as shown in FIG. 5, the width A of the connection end 200 of the bonding pad 5 connected to the belt-shaped pattern 1 is 110 μm, and the peripheral edge 25
The width a of 0 is 50 μm. Other configurations are the same as those of the first embodiment. The width A of the connection end 200 of the bonding pad 5 connected to the strip pattern 1 is larger than the width a of the peripheral edge 250 of the substrate. Therefore, even if the connection end portion 200 is eroded during etching, a sufficient width can be left at the connection end portion 200, and the electrical connection reliability between the bonding pad 5 and the strip pattern 1 is further improved. In addition, in this embodiment, the same effects as those of the first embodiment can be exhibited.
【００４０】実施形態例３ 本例は，図５に示すごとく，ボンディングパッド５が，
帯状パターン１に向かって幅広に広がる曲線部５７と，
帯状パターン１と反対側である基板周縁側に位置する長
尺部５６とからなる。帯状パターン１と接続している接
続端部２００の幅Ａが１１０μｍであり，基板周縁側端
部２５０の幅ａは５０μｍである。その他は，実施形態
例２と同様である。本例においては，ボンディングパッ
ド５の外形線における帯状パターン１の外形線と接続す
る接続部分５８が，曲線からなるため，その部分に応力
が集中しにくく，亀裂発生を効果的に抑制することがで
きる。Embodiment 3 In this embodiment, as shown in FIG.
A curved portion 57 widening toward the belt-shaped pattern 1;
It is composed of a strip-shaped pattern 1 and a long portion 56 located on the peripheral side of the substrate opposite to the strip-shaped pattern 1. The width A of the connection end 200 connected to the belt-shaped pattern 1 is 110 μm, and the width a of the peripheral edge 250 of the substrate is 50 μm. Others are the same as the second embodiment. In this example, since the connecting portion 58 connected to the outer shape of the band-shaped pattern 1 in the outer shape of the bonding pad 5 is formed of a curved line, stress is less likely to concentrate on that portion, and crack generation is effectively suppressed. it can.
【００４１】実施形態例４ 本例は，図６に示すごとく，ボンディングパッド５の形
状が半円であり，その他の点は実施形態例２と同様であ
る。ボンディングパッド５の接続端部２００は帯状パタ
ーン１と接続している。ボンディングパッド５は，円の
中心を通る直線で半分に切断した形状，すなわち，半円
である。ボンディングパッド５の接続端部２００は，円
の中心を通る直線である。帯状パターン１には，複数の
ボンディングパッド５が配列している。本例において
は，ボンディングパッド５が半円であり，すべての外形
線が曲線からなる。このため，ボンディングパッド５
は，その形状から応力集中が生じにくい。このため，亀
裂が発生しにくく，耐熱衝撃性も優れている。したがっ
て，ボンディングパッド５と壁面パターン１との接続信
頼性が高い。Embodiment 4 In this embodiment, as shown in FIG. 6, the shape of the bonding pad 5 is semicircular, and the other points are the same as those in Embodiment 2. The connection end 200 of the bonding pad 5 is connected to the strip pattern 1. The bonding pad 5 has a shape cut in half by a straight line passing through the center of the circle, that is, a semicircle. The connection end 200 of the bonding pad 5 is a straight line passing through the center of the circle. A plurality of bonding pads 5 are arranged on the strip pattern 1. In this example, the bonding pad 5 is semicircular, and all the outlines are curved. Therefore, the bonding pad 5
Is less likely to cause stress concentration due to its shape. For this reason, cracks are hardly generated and the thermal shock resistance is excellent. Therefore, the connection reliability between the bonding pad 5 and the wall pattern 1 is high.
【００４２】実施形態例５ 本例は，図７に示すごとく，ボンディングパッド５の形
状が半楕円であり，その他の点は実施形態例４と同様で
ある。ボンディングパッド５は，楕円の短軸に沿って半
分に切断した形状，すなわち半楕円体である。ボンディ
ングパッド５の接続端部２００は，楕円の短軸である。
ボンディングパッド５の長さＢは，楕円の長軸の半分の
大きさである。Embodiment 5 In this embodiment, as shown in FIG. 7, the shape of the bonding pad 5 is semi-elliptical, and the other points are the same as in Embodiment 4. The bonding pad 5 has a shape cut in half along the minor axis of the ellipse, that is, a semi-ellipsoid. The connection end 200 of the bonding pad 5 is the short axis of the ellipse.
The length B of the bonding pad 5 is half the length of the major axis of the ellipse.
【００４３】本例においても，実施形態例４と同様に，
ボンディングパッド５に応力集中が生じにくく，壁面パ
ターン６との接続信頼性が高い。また，ボンディングパ
ッドは，半楕円の長軸が帯状パターンの幅方向に沿うよ
うに複数配置されているため，帯状パターン１に沿って
ボンディングパッドを多数配置することができる。Also in this embodiment, similar to the fourth embodiment,
Stress concentration hardly occurs on the bonding pad 5 and the connection reliability with the wall pattern 6 is high. Further, since a plurality of bonding pads are arranged so that the major axis of the semi-ellipse extends along the width direction of the band-shaped pattern, a large number of bonding pads can be arranged along the band-shaped pattern 1.
【００４４】実施形態例６ 本例は，図８，図９に示すごとく，帯状パターンがな
く，壁面パターン６とボンディングパッド５とが直接接
続している。ボンディングパッド５は，壁面パターン６
に向かって幅広に広がる曲線部５７と，壁面パターン６
と反対側に位置する長尺体５６とからなり，その形状は
実施形態例３と同様である。ボンディングパッド５のピ
ッチＬは１５０μｍである。本例の電子部品搭載用基板
は，実施形態例１と同様に，複数の絶縁基板４０及び導
体パターン３２を積層した多層基板４からなる。搭載用
凹部７は，上方にいくに従って広く開口するスタジアム
構造である。Embodiment 6 In this embodiment, as shown in FIGS. 8 and 9, there is no strip pattern, and the wall pattern 6 and the bonding pad 5 are directly connected. The bonding pad 5 has a wall pattern 6
Curved portion 57 widening toward the wall and wall pattern 6
And a long body 56 located on the opposite side of the third embodiment, and its shape is the same as that of the third embodiment. The pitch L of the bonding pads 5 is 150 μm. As in the first embodiment, the electronic component mounting board of the present embodiment includes a multilayer board 4 in which a plurality of insulating boards 40 and conductor patterns 32 are stacked. The mounting recess 7 has a stadium structure that opens wider as it goes upward.
【００４５】ボンディングパッド５の外形線における壁
面パターン６の外形線と接続する接続部分５９に応力が
集中しやすい。本例においては，このような応力集中が
生じやすい接続部分５９を，曲線部５７により接続して
いる。このため，接続部分５９の応力が緩和され，亀裂
の発生を抑制することができる。このため，ボンディン
グパッド５と壁面パターン６との接続信頼性が高い。The stress tends to concentrate on the connection portion 59 connected to the outer shape of the wall surface pattern 6 in the outer shape of the bonding pad 5. In this example, the connection portions 59 where such stress concentration is likely to occur are connected by the curved portions 57. For this reason, the stress of the connection portion 59 is alleviated, and the occurrence of cracks can be suppressed. Therefore, the connection reliability between the bonding pad 5 and the wall pattern 6 is high.
【００４６】実施形態例７ 本例は，図１０に示すごとく，ボンディングパッド５が
半円体であり，その形状は実施形態例４のボンディング
パッド５と同じである。本例のボンディングパッド５の
形状は半円であるため，壁面パターン６との接続部分５
９における応力集中を抑制でき，両者の電位接続信頼性
が高い。Embodiment 7 In this embodiment, as shown in FIG. 10, the bonding pad 5 is semicircular, and the shape is the same as that of the bonding pad 5 of Embodiment 4. Since the shape of the bonding pad 5 in this example is a semicircle, the connection portion 5 with the wall pattern 6 is formed.
9 can be suppressed and the potential connection reliability between the two is high.
【００４７】実施形態例８ 本例は，図１１に示すごとく，ボンディングパッド５が
半楕円体であり，その形状は実施形態例５のボンディン
グパッド５と同じである。本例のボンディングパッド５
の形状は半楕円であるため，壁面パターン６との接続部
分５９における応力集中を抑制でき，両者の電位接続信
頼性が高い。Embodiment 8 In this embodiment, as shown in FIG. 11, the bonding pad 5 is a semi-ellipsoid, and the shape is the same as the bonding pad 5 of Embodiment 5. Bonding pad 5 of this example
Is semi-elliptical, stress concentration at the connecting portion 59 with the wall pattern 6 can be suppressed, and the potential connection reliability between the two is high.
【００４８】[0048]
【発明の効果】本発明によれば，電気特性が高く，かつ
壁面パターンとボンディングパッドとの電気接続信頼性
に優れた電子部品搭載用基板を提供することができる。According to the present invention, it is possible to provide an electronic component mounting board having high electric characteristics and excellent electric connection reliability between the wall pattern and the bonding pad.
【図１】実施形態例１の電子部品搭載用基板の要部斜視
図。FIG. 1 is a perspective view of a main part of an electronic component mounting board according to a first embodiment.
【図２】実施形態例１の電子部品搭載用基板の斜視図。FIG. 2 is a perspective view of an electronic component mounting board according to the first embodiment.
【図３】実施形態例１の電子部品搭載用基板の平面図。FIG. 3 is a plan view of the electronic component mounting board according to the first embodiment.
【図４】実施形態例１におけるボンディングパッドの形
成方法を示すための，多層基板の断面図（Ａ）〜
（Ｆ），及び多層基板の平面図（ａ）〜（ｆ）。FIGS. 4A to 4C are cross-sectional views of a multi-layer substrate for illustrating a method of forming a bonding pad according to the first embodiment;
(F) and plan views (a) to (f) of the multilayer substrate.
【図５】実施形態例２，３の電子部品搭載用基板の要部
斜視図。FIG. 5 is an essential part perspective view of an electronic component mounting board according to the second and third embodiments.
【図６】実施形態例４の電子部品搭載用基板の要部斜視
図。FIG. 6 is a perspective view of a main part of an electronic component mounting board according to a fourth embodiment.
【図７】実施形態例５の電子部品搭載用基板の要部斜視
図。FIG. 7 is an essential part perspective view of an electronic component mounting board according to a fifth embodiment;
【図８】実施形態例６の電子部品搭載用基板の斜視図。FIG. 8 is a perspective view of an electronic component mounting board according to a sixth embodiment.
【図９】実施形態例６の電子部品搭載用基板の要部斜視
図。FIG. 9 is a perspective view of a main part of an electronic component mounting board according to a sixth embodiment.
【図１０】実施形態例７の電子部品搭載用基板の要部斜
視図。FIG. 10 is a perspective view of a main part of an electronic component mounting board according to a seventh embodiment.
【図１１】実施形態例８の電子部品搭載用基板の要部斜
視図。FIG. 11 is a perspective view of a main part of an electronic component mounting board according to an eighth embodiment.
【図１２】従来例の電子部品搭載用基板の要部斜視図。FIG. 12 is a perspective view of a main part of a conventional electronic component mounting board.
１．．．帯状パターン， ２１．．．開口段部， ２００．．．接続端部， ３１，３２．．．導体パターン， ３５，５．．．ボンディングパッド， ４．．．多層基板， ５４．．．長尺部， ５６．．．長尺部， ５７．．．曲線部， ５５．．．曲線部 ５８，５９．．．接続部分， ６．．．壁面パターン ７．．．搭載用凹部， 1. . . Band-like pattern, 21. . . Opening step, 200. . . Connection ends, 31, 32. . . Conductor pattern, 35,5. . . 3. bonding pad; . . Multilayer substrate, 54. . . Long part, 56. . . Long part, 57. . . Curved part, 55. . . Curved portions 58, 59. . . Connection part, 6. . . Wall pattern 7. . . Mounting recess,
Claims (13)
と，該搭載用凹部の側壁に設けた壁面パターンと，該壁
面パターンと接続したボンディングパッドとを有する電
子部品搭載用基板において，上記壁面パターンと上記ボ
ンディングパッドとの間は，搭載用凹部の開口段部に沿
って延びる帯状パターンにより接続されていることを特
徴とする電子部品搭載用基板。An electronic component mounting substrate comprising: a mounting recess for mounting an electronic component; a wall pattern provided on a side wall of the mounting recess; and a bonding pad connected to the wall pattern. An electronic component mounting substrate, wherein the pattern and the bonding pad are connected by a band-shaped pattern extending along an opening step of the mounting recess.
は，隣接するボンディングパッドの間を連結しているこ
とを特徴とする電子部品搭載用基板。2. The electronic component mounting board according to claim 1, wherein the strip-shaped pattern connects between adjacent bonding pads.
ターンは，搭載用凹部の開口段部の全周を被覆して形成
されていることを特徴とする電子部品搭載用基板。3. The electronic component mounting board according to claim 1, wherein the belt-shaped pattern is formed so as to cover the entire circumference of the stepped portion of the mounting recess.
上記ボンディングパッドは，曲線部を有することを特徴
とする電子部品搭載用基板。4. The method according to claim 1, wherein:
The electronic component mounting substrate according to claim 1, wherein the bonding pad has a curved portion.
上記ボンディングパッドにおける少なくとも上記帯状パ
ターンと接続する接続部分は，曲線部であることを特徴
とする電子部品搭載用基板。5. The method according to claim 1, wherein:
An electronic component mounting substrate, wherein at least a connection portion of the bonding pad connected to the band-shaped pattern is a curved portion.
ッドにおける上記接続部分は，上記帯状パターンに向け
て曲線によって徐々に拡大している曲線部からなること
を特徴とする電子部品搭載用基板。6. The electronic component mounting substrate according to claim 5, wherein the connection portion of the bonding pad is formed by a curved portion gradually expanding by a curve toward the band-shaped pattern.
ィングパッドは，半円体または半楕円体であることを特
徴とする電子部品搭載用基板。7. The electronic component mounting board according to claim 4, wherein the bonding pad is a semicircle or a semiellipse.
ィングパッドは，上記帯状パターンの側に位置し該帯状
パターンに向かって幅広に広がる曲線部と，上記帯状パ
ターンと反対側に位置する長尺部とからなることを特徴
とする電子部品搭載用基板。8. The bonding pad according to claim 4, wherein the bonding pad is located on a side of the band-shaped pattern and widened toward the band-shaped pattern, and a long portion located on a side opposite to the band-shaped pattern. A substrate for mounting electronic components, comprising:
と，該搭載用凹部の側壁に設けた壁面パターンと，該壁
面パターンと接続したボンディングパッドとを有する電
子部品搭載用基板において，上記ボンディングパッド
は，曲線部を有することを特徴とする電子部品搭載用基
板。9. An electronic component mounting substrate comprising: a mounting recess for mounting an electronic component; a wall pattern provided on a side wall of the mounting recess; and a bonding pad connected to the wall pattern. The pad has a curved portion, and is a substrate for mounting electronic components.
パッドにおける少なくとも上記壁面パターンと接続する
接続部分は，曲線部であることを特徴とする電子部品搭
載用基板。10. The electronic component mounting substrate according to claim 9, wherein at least a connection portion of the bonding pad connected to the wall pattern is a curved portion.
ンディングパッドにおける上記接続部分は，上記壁面パ
ターンに向けて曲線によって徐々に拡大している曲線部
からなることを特徴とする電子部品搭載用基板。11. The electronic component mounting board according to claim 9, wherein the connection portion of the bonding pad is formed by a curved portion gradually expanding by a curve toward the wall surface pattern.
て，上記ボンディングパッドは，半円体または半楕円体
であることを特徴とする電子部品搭載用基板。12. The electronic component mounting board according to claim 9, wherein the bonding pad is a semicircle or a semiellipse.
て，上記ボンディングパッドは，上記壁面パターンの側
に位置し該壁面パターンに向かって幅広に広がる曲線部
と，上記壁面パターンと反対側に位置する長尺部とから
なることを特徴とする電子部品搭載用基板。13. The bonding pad according to claim 9, wherein the bonding pad is located on a side of the wall pattern and widened toward the wall pattern, and a curved portion is provided on a side opposite to the wall pattern. A substrate for mounting an electronic component, comprising: a long portion that is positioned.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001052472A JP2001319945A (en) | 2000-03-02 | 2001-02-27 | Board for mounting electronic part |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000-57267 | 2000-03-02 | ||
| JP2000057267 | 2000-03-02 | ||
| JP2001052472A JP2001319945A (en) | 2000-03-02 | 2001-02-27 | Board for mounting electronic part |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001319945A true JP2001319945A (en) | 2001-11-16 |
Family
ID=26586616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001052472A Pending JP2001319945A (en) | 2000-03-02 | 2001-02-27 | Board for mounting electronic part |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001319945A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004265956A (en) * | 2003-02-26 | 2004-09-24 | Ibiden Co Ltd | Multilayer printed wiring board |
| US7894203B2 (en) | 2003-02-26 | 2011-02-22 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| JPWO2015129415A1 (en) * | 2014-02-27 | 2017-03-30 | シャープ株式会社 | Semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6344745A (en) * | 1986-08-11 | 1988-02-25 | Ibiden Co Ltd | Circuit board for mounting of electronic component |
| JPH0774473A (en) * | 1993-09-01 | 1995-03-17 | Ibiden Co Ltd | Substrate for mounting electronic parts |
| JPH08181271A (en) * | 1994-12-26 | 1996-07-12 | Oki Electric Ind Co Ltd | Semiconductor device package |
-
2001
- 2001-02-27 JP JP2001052472A patent/JP2001319945A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6344745A (en) * | 1986-08-11 | 1988-02-25 | Ibiden Co Ltd | Circuit board for mounting of electronic component |
| JPH0774473A (en) * | 1993-09-01 | 1995-03-17 | Ibiden Co Ltd | Substrate for mounting electronic parts |
| JPH08181271A (en) * | 1994-12-26 | 1996-07-12 | Oki Electric Ind Co Ltd | Semiconductor device package |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004265956A (en) * | 2003-02-26 | 2004-09-24 | Ibiden Co Ltd | Multilayer printed wiring board |
| JP4493923B2 (en) * | 2003-02-26 | 2010-06-30 | イビデン株式会社 | Printed wiring board |
| US7894203B2 (en) | 2003-02-26 | 2011-02-22 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| JPWO2015129415A1 (en) * | 2014-02-27 | 2017-03-30 | シャープ株式会社 | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4178880B2 (en) | Module parts | |
| US7489223B2 (en) | Inductor and method of manufacturing the same | |
| TWI446847B (en) | Wiring board, method for manufacturing the same, and semiconductor package | |
| US20100282502A1 (en) | Multilayer printed wiring board | |
| JP2010080968A (en) | Method of manufacturing module component | |
| JP2002016183A (en) | Circuit board for semiconductor package and manufacturing method thereof | |
| JP5249870B2 (en) | Wiring circuit board and manufacturing method thereof | |
| KR20040076164A (en) | A package substrate for electrolytic leadless plating, and its manufacturing method | |
| US10531569B2 (en) | Printed circuit board and method of fabricating the same | |
| TWI397358B (en) | Wire bonding substrate and fabrication thereof | |
| JP2009272559A (en) | Printed circuit board and method of manufacturing same | |
| JP2001319945A (en) | Board for mounting electronic part | |
| JP3770895B2 (en) | Manufacturing method of wiring board using electrolytic plating | |
| US20040050708A1 (en) | Plating method for PCB | |
| KR20160126311A (en) | Semiconductor package and manufacturing method thereof | |
| US11205632B2 (en) | Wiring substrate and semiconductor device | |
| JP2004221404A (en) | Wiring board, its manufacturing method, semiconductor device, electronic module and electronic apparatus | |
| JP4560970B2 (en) | Electronic component mounting board | |
| JP2000091722A (en) | Printed wiring board and its manufacture | |
| US6770979B2 (en) | Semiconductor package and substrate thereof | |
| JP2005340676A (en) | Semiconductor device | |
| JP4187339B2 (en) | Electronic component mounting board | |
| JP2000244091A (en) | Electronic part mounting board | |
| JP2734625B2 (en) | Method for manufacturing multilayer wiring board | |
| JP2004111544A (en) | Multilayer wiring board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080122 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100210 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100216 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100413 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100518 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100705 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20100817 |