JP2001267914A5

JP2001267914A5 -

Info

Publication number: JP2001267914A5
Application number: JP2000076341A
Authority: JP
Filing date: 2000-03-14
Publication date: 2004-12-24
Anticipated expiration: 2020-03-14

Description

【発明の名称】ＰＬＬ回路及びそれを構成する半導体集積回路並びに無線通信機器Patent application title: PLL circuit, semiconductor integrated circuit comprising the same, and wireless communication device

Claims

基準信号を分周する第１分周手段と、
入力電圧レベルに応じて発振周波数が変わる電圧制御発振器と、
上記電圧制御発振器の出力信号を分周する第２分周手段と、
上記第１分周手段の出力信号と上記第２分周手段の出力信号との位相を比較する位相比較手段とを具備して成り、
上記位相比較手段の比較結果に基づいて上記電圧制御発振器の発振周波数が制御され、
上記基準信号の入力経路に、上記基準信号の周波数通過帯域を制限するための周波数通過帯域制限手段を有することを特徴とするＰＬＬ回路。First dividing means for dividing the reference signal;
A voltage controlled oscillator whose oscillation frequency changes according to the input voltage level,
Second dividing means for dividing an output signal of the voltage controlled oscillator;
Become comprises a phase comparator for comparing the phases of the output signals of the second division means of said first frequency dividing means,
The oscillation frequency of the voltage controlled oscillator is controlled based on the comparison result of the phase comparison means,
The input path of the reference signal, PLL circuit characterized by having a frequency pass band limiting means for limiting a frequency pass band of the reference signal.

基準信号を分周する第１分周手段と、
電圧レベルに応じて発振周波数が変わる電圧制御発振器の出力信号を分周する第２分周手段と、
上記第１分周手段の出力信号と上記第２分周手段の出力信号との位相を比較する位相比較手段と、
上記第１および第２分周手段並びに上記位相比較手段が一括形成された一つの半導体基板とを具備して成り、
上記第１および第２分周手段、上記電圧制御発振器、並びに上記位相比較手段はＰＬＬ回路を構成し、
上記基準信号の入力経路に、上記基準信号の周波数通過帯域を制限するための周波数通過帯域制限手段を有することを特徴とする半導体集積回路。First dividing means for dividing the reference signal;
Second dividing means for dividing an output signal of a voltage controlled oscillator whose oscillation frequency changes according to a voltage level;
Phase comparison means for comparing the phase of the output signal of the first dividing means and the output signal of the second dividing means;
Made by and a single semiconductor substrate on which the first and second division means and said phase comparison means is collectively formed,
The first and second frequency dividing means, the voltage controlled oscillator, and the phase comparing means constitute a PLL circuit,
The semiconductor integrated circuit according to claim to the input path of the reference signal, that has a frequency pass band limiting means for limiting a frequency pass band of the reference signal.

ハイパスフィルタを含んで上記周波数通過帯域制限手段を構成することを特徴とする請求項２記載の半導体集積回路。 3. A semiconductor integrated circuit according to claim 2 , wherein said frequency pass band limiting means is configured to include a high pass filter.

周波数通過帯域を変更可能な可変フィルタを含んで上記周波数通過帯域制限手段を構成することを特徴とする請求項２記載の半導体集積回路。 3. The semiconductor integrated circuit according to claim 2 , wherein said frequency pass band limiting means is configured to include a variable filter capable of changing a frequency pass band.

発振手段と、上記発振手段で発振された信号と受信された高周波信号とを混合するためのミキサーとを具備して成り、
上記発振手段は、請求項２乃至４の何れか１項記載の半導体集積回路を含んで成ることを特徴とする無線通信機器。 Made by including an oscillator means and a mixer for mixing the high-frequency signal received as a signal oscillated by the oscillating means,
A wireless communication device comprising the semiconductor integrated circuit according to any one of claims 2 to 4, wherein the oscillation means comprises the semiconductor integrated circuit according to any one of claims 2 to 4.