JP2001267384A - Measurement method of pseudo-mosfet - Google Patents
Measurement method of pseudo-mosfetInfo
- Publication number
- JP2001267384A JP2001267384A JP2000071452A JP2000071452A JP2001267384A JP 2001267384 A JP2001267384 A JP 2001267384A JP 2000071452 A JP2000071452 A JP 2000071452A JP 2000071452 A JP2000071452 A JP 2000071452A JP 2001267384 A JP2001267384 A JP 2001267384A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- soi
- thin film
- film
- pseudo
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、擬似ＭＯＳＦＥＴ
を用いてＳＯＩ基板のＩｄ−Ｖｇ特性を測定する方法に
関する。The present invention relates to a pseudo MOSFET.
And a method for measuring the Id-Vg characteristics of an SOI substrate using the method.
【０００２】[0002]
【従来の技術】近年、低消費電力で高速処理性能に優れ
るＳＯＩ基板（Silicon-On-Insulator）を用いた様々な
デバイスが実用化されるに至り、そのＳＯＩ基板の品質
評価は重視されてきている。数あるＳＯＩ基板評価法の
中において、擬似ＭＯＳＦＥＴ（Pseudo Metal-Oxide-S
emiconductor Field Effect Transistor、別称Point Co
ntact Transistor）を用いた評価方法は、擬似ＭＯＳＦ
ＥＴが簡易な構造であるために、簡便な評価手段として
注目されている。2. Description of the Related Art In recent years, various devices using an SOI substrate (Silicon-On-Insulator) having low power consumption and excellent high-speed processing performance have been put to practical use, and quality evaluation of the SOI substrate has been emphasized. I have. Among various SOI substrate evaluation methods, a pseudo MOSFET (Pseudo Metal-Oxide-S
emiconductor Field Effect Transistor, also known as Point Co
ntact Transistor) is a pseudo-MOSF
ET has attracted attention as a simple evaluation means because of its simple structure.
【０００３】擬似ＭＯＳＦＥＴは、ＳＯＩ基板構造をそ
のまま利用するので、図７に示すように通常ＭＯＳＦＥ
Ｔとは構造が少し異なり、ＳＯＩ基板１を金属板３上に
設置し電気的に金属板３とシリコン基板２を接触させる
ことでゲート電極の役割を果たすシリコン基板２と、ゲ
ート酸化膜の役割を果たす埋込絶縁膜４と、ＳＯＩ薄膜
６の表面にそれぞれ接触させるドレインプローブ７とソ
ースプローブ８で構成される。擬似ＭＯＳＦＥＴを用い
てＳＯＩ基板を評価するときには、ソースプローブ８を
接地し、ドレインプローブ７に一定のドレイン電圧Ｖｄ
を印加し、金属板３に印加するゲート電圧Ｖｇを変化さ
せる。このときのドレイン電流Ｉｄが変化するときの特
性（以下、この特性を「Ｉｄ−Ｖｇ特性」という。）に
よりＳＯＩ基板が評価される。Since the pseudo MOSFET uses the SOI substrate structure as it is, as shown in FIG.
The structure is slightly different from that of T. The SOI substrate 1 is placed on the metal plate 3, and the metal plate 3 and the silicon substrate 2 are electrically contacted to each other. And a drain probe 7 and a source probe 8 which are respectively in contact with the surface of the SOI thin film 6. When evaluating the SOI substrate using the pseudo MOSFET, the source probe 8 is grounded, and the drain probe 7 is supplied with a constant drain voltage Vd.
To change the gate voltage Vg applied to the metal plate 3. The SOI substrate is evaluated based on the characteristics when the drain current Id changes at this time (hereinafter, these characteristics are referred to as “Id-Vg characteristics”).
【０００４】[0004]
【発明が解決しようとする課題】しかし、上記擬似ＭＯ
ＳＦＥＴを用いた測定では、図６に示すように、繰返し
測定において、Ｉｄ−Ｖｇ特性が徐々にシフトし再現性
の良い値が得られない不具合があった。この現象を鋭意
検討の結果、この不具合は測定回数が増えるに従ってＳ
ＯＩ薄膜６の表面に図８に示すような自然酸化膜９が形
成され、徐々に厚くなることで生じることがわかった。
またＳＯＩ薄膜６表面に汚れが付着することによっても
Ｉｄ−Ｖｇ特性が変動することを見出した。However, the above pseudo MO
In the measurement using the SFET, as shown in FIG. 6, in the repetitive measurement, the Id-Vg characteristics gradually shifted, and a value with good reproducibility was not obtained. As a result of diligent study of this phenomenon, this defect has been found to increase as the number of measurements increases.
It was found that a natural oxide film 9 as shown in FIG. 8 was formed on the surface of the OI thin film 6 and gradually increased in thickness.
Further, it has been found that the Id-Vg characteristics fluctuate even when dirt adheres to the surface of the SOI thin film 6.
【０００５】本発明の目的は、擬似ＭＯＳＦＥＴを用い
てＳＯＩ基板を評価するときにＩｄ−Ｖｇ特性を精度良
く測定できる方法を提供することにある。本発明の別の
目的は、経時変化による影響を最小限にして再現性の良
い値が得られる擬似ＭＯＳＦＥＴの測定方法を提供する
ことにある。An object of the present invention is to provide a method for accurately measuring the Id-Vg characteristic when evaluating an SOI substrate using a pseudo MOSFET. Another object of the present invention is to provide a method of measuring a pseudo MOSFET in which a value with good reproducibility can be obtained by minimizing the influence of a change over time.
【０００６】[0006]
【課題を解決するための手段】請求項１に係る発明は、
図１に示すように、擬似ＭＯＳＦＥＴを用いてＳＯＩ基
板のＩｄ−Ｖｇ特性を測定する方法において、ＳＯＩ基
板１０のＳＯＩ薄膜１３表面に厚さ１ｎｍ〜１μｍの絶
縁膜１６を形成した後、ドレインプローブ１７及びソー
スプローブ１８をそれぞれ絶縁膜１６に突刺してＳＯＩ
薄膜１３に直接接触した状態でＩｄ−Ｖｇ特性を測定す
ることを特徴とする擬似ＭＯＳＦＥＴの測定方法であ
る。請求項１に係る発明では、ＳＯＩ基板１０のＳＯＩ
薄膜１３表面に厚さ１ｎｍ〜１μｍの絶縁膜１６を形成
した後、プローブ１７，１８を絶縁膜１６に突刺し、直
接ＳＯＩ薄膜１３と接触させる。測定前にあらかじめ絶
縁膜１６を形成することにより、ＳＯＩ薄膜１３中の絶
縁膜１６近傍に形成されるチャネル中の電子及びホール
は、絶縁膜１６がない時に比べて自然酸化の進行や汚れ
などの表面の電気的不安定要因の影響を受けないことか
ら、再現性の良い測定値が得られる。The invention according to claim 1 is
As shown in FIG. 1, in a method for measuring the Id-Vg characteristics of an SOI substrate using a pseudo MOSFET, after forming an insulating film 16 having a thickness of 1 nm to 1 μm on the surface of an SOI thin film 13 of an SOI substrate 10, a drain probe is formed. 17 and the source probe 18 are pierced into the insulating film 16 respectively, and the SOI
This is a method for measuring a pseudo MOSFET, wherein the Id-Vg characteristic is measured in a state of being in direct contact with the thin film 13. According to the first aspect of the present invention, the SOI
After an insulating film 16 having a thickness of 1 nm to 1 μm is formed on the surface of the thin film 13, probes 17 and 18 are pierced into the insulating film 16 and directly contact the SOI thin film 13. By forming the insulating film 16 in advance before the measurement, electrons and holes in the channel formed near the insulating film 16 in the SOI thin film 13 are more likely to undergo natural oxidation and contamination than in the case where the insulating film 16 is not provided. Since it is not affected by the surface electrical instability factor, a measurement value with good reproducibility can be obtained.
【０００７】請求項２に係る発明は、図３に示すよう
に、擬似ＭＯＳＦＥＴを用いてＳＯＩ基板のＩｄ−Ｖｇ
特性を測定する方法において、ＳＯＩ基板１０のＳＯＩ
薄膜１３表面に厚さ２ｎｍ〜１μｍの絶縁膜１６を形成
し、絶縁膜１６表面に所定のパターンのレジスト層２９
を形成し、レジスト層２９をマスクにして絶縁膜１６を
エッチングし、レジスト層２９を除去してＳＯＩ基板１
０を洗浄し、絶縁膜１６をマスクにしてエッチングによ
り表出したＳＯＩ薄膜１３表面に金属を堆積して一対の
電極３４を形成した後、一対の電極３４にドレインプロ
ーブ１７及びソースプローブ１８をそれぞれ接触した状
態でＩｄ−Ｖｇ特性を測定することを特徴とする擬似Ｍ
ＯＳＦＥＴの測定方法である。請求項２に係る発明で
は、上記方法によりＳＯＩ薄膜１３表面に金属を堆積さ
せて一対の電極３４を形成することにより、ＳＯＩ薄膜
１３表面の自然酸化膜の形成に起因する経時変化による
影響を受けずに測定できる。請求項３に係る発明は、請
求項１又は２係る発明であって、絶縁膜が自然酸化膜、
化学酸化膜又は熱酸化膜である擬似ＭＯＳＦＥＴの測定
方法である。According to a second aspect of the present invention, as shown in FIG. 3, the Id-Vg
In the method for measuring the characteristics, the SOI
An insulating film 16 having a thickness of 2 nm to 1 μm is formed on the surface of the thin film 13, and a resist pattern 29 having a predetermined pattern is formed on the surface of the insulating film 16.
Is formed, the insulating film 16 is etched using the resist layer 29 as a mask, the resist layer 29 is removed, and the SOI substrate 1 is removed.
Then, a metal is deposited on the surface of the SOI thin film 13 exposed by etching using the insulating film 16 as a mask to form a pair of electrodes 34, and then the drain probe 17 and the source probe 18 are respectively applied to the pair of electrodes 34. Pseudo M characterized by measuring the Id-Vg characteristic in a contact state
This is a method for measuring an OSFET. According to the second aspect of the present invention, by depositing a metal on the surface of the SOI thin film 13 by the above method to form a pair of electrodes 34, the metal is affected by a change with time due to the formation of a natural oxide film on the surface of the SOI thin film 13. Can be measured without The invention according to claim 3 is the invention according to claim 1 or 2, wherein the insulating film is a natural oxide film,
This is a method for measuring a pseudo MOSFET which is a chemical oxide film or a thermal oxide film.
【０００８】[0008]
【発明の実施の形態】次に本発明の実施の形態について
説明する。本発明の第１の実施の形態を図１に基づいて
説明する。図１に示すように、ＳＯＩ基板１０は埋込絶
縁膜１２をシリコン基板１１と単結晶シリコン膜からな
るＳＯＩ薄膜１３でサンドイッチ上に挟み込んだ構造を
有する。擬似ＭＯＳＦＥＴは、図１に示すように、ＳＯ
Ｉ基板１０を金属板１４上に設置し電気的に金属板１４
とシリコン基板１１を接触させることでゲート電極の役
割を果たすシリコン基板１１と、ゲート酸化膜の役割を
果たす埋込絶縁膜１２と、ＳＯＩ薄膜１３の表面にそれ
ぞれ接触させるドレインプローブ１７とソースプローブ
１８で構成される。Next, an embodiment of the present invention will be described. A first embodiment of the present invention will be described with reference to FIG. As shown in FIG. 1, the SOI substrate 10 has a structure in which a buried insulating film 12 is sandwiched between a silicon substrate 11 and an SOI thin film 13 made of a single crystal silicon film. The pseudo MOSFET is, as shown in FIG.
I substrate 10 is placed on a metal plate 14 and electrically
A silicon substrate 11 serving as a gate electrode by making contact with the silicon substrate 11, a buried insulating film 12 serving as a gate oxide film, and a drain probe 17 and a source probe 18 contacting the surface of the SOI thin film 13, respectively. It consists of.
【０００９】この実施の形態における特徴ある構成は、
ＳＯＩ基板１０のＳＯＩ薄膜１３表面に厚さ１ｎｍ〜１
μｍの絶縁膜１６を形成した後、ドレインプローブ１７
及びソースプローブ１８をそれぞれ絶縁膜１６に突刺し
てＳＯＩ薄膜１３に直接接触した状態で測定することに
ある。ベアな状態のＳＯＩ薄膜は活性なためＩｄ−Ｖｇ
特性を測定している間にも薄膜表面の酸化が進行した
り、薄膜表面が汚染され易い。このようなＳＯＩ薄膜は
その表面が電気的に不安定であるため、Ｉｄ−Ｖｇ特性
を繰返し測定した場合、測定値の再現性が悪い。そこで
測定前にＳＯＩ薄膜１３の表面に厚さ１ｎｍ〜１μｍの
絶縁膜１６を形成することでＳＯＩ薄膜１３表面を安定
させ、更にプローブ１７，１８を絶縁膜１６に突刺すの
でＳＯＩ薄膜１３表面を表出することなく測定できる。
絶縁膜１６の厚さが１ｎｍ未満であると自然酸化が進行
するためＩｄ−Ｖｇ特性変動を生じ、１μｍを越えると
ＳＯＩ薄膜１３にプローブ１７，１８を突刺してもＳＯ
Ｉ薄膜に接触させることが困難となる。絶縁膜１６の好
ましい厚さは１０〜１００ｎｍである。The characteristic configuration of this embodiment is as follows.
The thickness of the SOI thin film 13 on the SOI substrate 10 is 1 nm to 1 nm.
After forming the insulating film 16 of μm, the drain probe 17 is formed.
And the source probe 18 is pierced into the insulating film 16 and is directly contacted with the SOI thin film 13 for measurement. Since the bare SOI thin film is active, Id-Vg
Oxidation of the thin film surface progresses during the measurement of the characteristics, and the thin film surface is easily contaminated. Since the surface of such an SOI thin film is electrically unstable, when the Id-Vg characteristics are repeatedly measured, the reproducibility of the measured values is poor. Therefore, the surface of the SOI thin film 13 is stabilized by forming an insulating film 16 having a thickness of 1 nm to 1 μm on the surface of the SOI thin film 13 before measurement. Can be measured without exposing.
If the thickness of the insulating film 16 is less than 1 nm, spontaneous oxidation proceeds, causing fluctuations in Id-Vg characteristics.
It is difficult to make contact with the I thin film. The preferred thickness of the insulating film 16 is 10 to 100 nm.
【００１０】この実施の形態では図２に示されるＩｄ−
Ｖｇ特性の測定装置１９が用いられる。基台２１にはス
タンド２２ａが立設され、このスタンド２２ａには支柱
２２ｂが上下動可能に挿入される。支柱２２ｂはスタン
ド２２ａの側部に設けられたねじ２２ｃにより所定の高
さに固定されるようになっている。支柱２２ｂには腕部
２３がピン２４により回転可能に支持される。腕部２３
の一端には一対のドレインプローブ１７及びソースプロ
ーブ１８が固定され、その他端には重り２６が摺動可能
に設けられる。両プローブ１７，１８はそれぞれの先端
が同一高さになるように固定される。図２では便宜上、
１つのプローブのみ示している。腕部２３の一端の上部
には分銅２７を載せるための皿２８が設けられる。図示
しないが、支柱に２本の腕部を回転可能に取付け、これ
らの腕部のそれぞれにドレインプローブ及びソースプロ
ーブを設けて、各腕部を互いに独立させてもよい。プロ
ーブ１７と１８の間及び金属板１４とソースプローブ１
８の間には、図示しないが、電圧源、電流計及び電圧計
がそれぞれ接続される。In this embodiment, Id- shown in FIG.
A Vg characteristic measuring device 19 is used. A stand 22a is erected on the base 21, and a column 22b is inserted into the stand 22a so as to be vertically movable. The support 22b is fixed at a predetermined height by screws 22c provided on the side of the stand 22a. The arm 23 is rotatably supported by the pin 22 on the support 22b. Arm 23
A pair of a drain probe 17 and a source probe 18 are fixed to one end, and a weight 26 is slidably provided at the other end. Both probes 17 and 18 are fixed so that their tips are at the same height. In FIG. 2, for convenience,
Only one probe is shown. A plate 28 on which a weight 27 is placed is provided above one end of the arm 23. Although not shown, two arms may be rotatably attached to the column, and a drain probe and a source probe may be provided for each of these arms so that the arms are independent of each other. Between the probes 17 and 18 and between the metal plate 14 and the source probe 1
Although not shown, a voltage source, an ammeter, and a voltmeter are connected between the terminals 8.
【００１１】このような構造を有する測定装置１９でド
レイン電流Ｉｄ及びゲート電圧Ｖｇを測定するには、先
ずねじ２２ｃを弛めて支柱２２ｂをスタンド２２ａから
引出し、仮に固定する。次いで分銅２７を載せていない
状態で重り２６を水平に移動して腕部２３が水平になる
ように調節する。次に擬似ＭＯＳＦＥＴをプローブ１７
及び１８の下方に配置した後、ねじ２２ｃを弛めて支柱
２２ｂを少しずつ降下させ、プローブ１７及び１８の各
先端を絶縁膜１６の表面に接触した状態でねじ２２ｃを
締めて支柱２２ｂを固定する。この状態で、絶縁膜１６
の厚さに応じて適切な分銅２７を選択し、皿２８に載せ
る。分銅２７の重さで腕部２３が図２の矢印方向へ傾き
ドレインプローブ１７及びソースプローブ１８が絶縁膜
１６に突刺さりＳＯＩ薄膜１３に接触する。ドレイン電
流Ｉｄ及びゲート電圧Ｖｇの測定は、ソースプローブ１
８を接地し、ドレインプローブ１７に一定のドレイン電
圧Ｖｄを印加し、金属板１４に印加するゲート電圧Ｖｇ
を変化させたときのドレイン電流Ｉｄの変化状況を記録
することにより行われる。In order to measure the drain current Id and the gate voltage Vg with the measuring device 19 having such a structure, first, the screw 22c is loosened and the column 22b is pulled out from the stand 22a and temporarily fixed. Next, the weight 26 is moved horizontally without the weight 27 placed thereon, so that the arm 23 is adjusted to be horizontal. Next, the pseudo MOSFET is connected to the probe 17.
After disposing the lower end of the probes 22 and 18, the screws 22c are loosened to lower the support 22b little by little. The screws 22c are tightened while the tips of the probes 17 and 18 are in contact with the surface of the insulating film 16 to fix the support 22b. I do. In this state, the insulating film 16
An appropriate weight 27 is selected according to the thickness of the plate and placed on the plate 28. The arm 23 tilts in the direction of the arrow in FIG. 2 due to the weight of the weight 27, and the drain probe 17 and the source probe 18 pierce the insulating film 16 and come into contact with the SOI thin film 13. The measurement of the drain current Id and the gate voltage Vg is performed by using the source probe 1
8 is grounded, a constant drain voltage Vd is applied to the drain probe 17, and a gate voltage Vg applied to the metal plate 14 is applied.
This is performed by recording the state of change of the drain current Id when is changed.
【００１２】次に、本発明の第２の実施の形態を図３に
基づいて説明する。図３において、図１と同一符号は同
一構成要素を示す。先ずＳＯＩ基板１０（図３（ａ））
の表面に厚さ２〜５ｎｍの絶縁膜１６を形成し（図３
（ｂ））、この絶縁膜１６の表面にフォトリソグラフィ
によりパターニングしたレジスト層２９を形成する（図
３（ｃ）及び（ｄ））。ここでレジスト層２９は上記絶
縁膜１６の表面にラミネータを用いて感光性ドライフィ
ルム３１を積層した後に、このフィルム３１上にフィル
ムマスク３２を置き（図３（ｃ））、中心波長２５４ｎ
ｍの紫外線３３を照射して露光することにより、所定の
パターンに形成される（図３（ｄ））。絶縁膜１６の厚
さが２ｎｍ未満であるとＳＯＩ薄膜表面の化学的安定化
が不十分なため、Ｉｄ−Ｖｇ特性変動を生じ、１μｍを
越えると表面酸化膜形成のために必要な時間がかかり過
ぎ、コストが増大する。絶縁膜１６の好ましい厚さは１
０〜５００ｎｍである。Next, a second embodiment of the present invention will be described with reference to FIG. 3, the same reference numerals as those in FIG. 1 denote the same components. First, the SOI substrate 10 (FIG. 3A)
An insulating film 16 having a thickness of 2 to 5 nm is formed on the surface of FIG.
(B)) A resist layer 29 patterned by photolithography is formed on the surface of the insulating film 16 (FIGS. 3C and 3D). Here, as for the resist layer 29, after laminating a photosensitive dry film 31 on the surface of the insulating film 16 using a laminator, a film mask 32 is placed on the film 31 (FIG. 3C), and the center wavelength 254n.
A predetermined pattern is formed by irradiating and irradiating m ultraviolet rays 33 (FIG. 3D). If the thickness of the insulating film 16 is less than 2 nm, the chemical stability of the surface of the SOI thin film is insufficient, so that the Id-Vg characteristic fluctuates. Cost increases. The preferred thickness of the insulating film 16 is 1
0 to 500 nm.
【００１３】次いで絶縁膜を異方性エッチングによりパ
ターニングし（図３（ｅ）及び（ｆ））、レジスト層２
９を除去した後に（図３（ｇ））、基板１０を洗浄す
る。次に基板１０の表面の垂直方向から金属（例えばＡ
ｌやＮｉなど）を基板１０に堆積し（図３（ｈ））、一
対の電極３４を形成する（図３（ｉ））。この堆積方法
としてはＣＶＤ法（Chemical Vapor Deposition）、ス
パッタリングなどのＰＶＤ法（Physical Vapor Deposit
ion）等が挙げられる。このように形成されたＳＯＩ基
板１０を金属板１４上に接地し、ＳＯＩ薄膜１３表面に
形成された一対の電極３４にドレインプローブ１７及び
ソースプローブ１８をそれぞれ接触させて、第１の実施
の形態と同様にＳＯＩ基板１０のＩｄ−Ｖｇ特性を測定
する（図３（ｊ））。これによりＳＯＩ薄膜は表出せ
ず、かつ電極が確保されているため、再現性よく測定す
ることができる。なお、本発明の絶縁膜１６はＳＯＩ基
板を空気中に放置して形成した自然酸化膜でも、硫酸化
過水のような酸化剤を用いて形成した化学酸化膜でも、
熱酸化によって形成した熱酸化膜でもよい。Next, the insulating film is patterned by anisotropic etching (FIGS. 3E and 3F).
After removing 9 (FIG. 3G), the substrate 10 is washed. Next, a metal (for example, A
1 and Ni) are deposited on the substrate 10 (FIG. 3H) to form a pair of electrodes 34 (FIG. 3I). As this deposition method, a CVD method (Chemical Vapor Deposition), a PVD method such as a sputtering method (Physical Vapor Deposit) is used.
ion) and the like. The SOI substrate 10 thus formed is grounded on a metal plate 14, and the drain probe 17 and the source probe 18 are brought into contact with a pair of electrodes 34 formed on the surface of the SOI thin film 13, respectively, according to the first embodiment. Similarly, the Id-Vg characteristic of the SOI substrate 10 is measured (FIG. 3 (j)). Thus, the SOI thin film cannot be exposed and the electrodes are secured, so that the measurement can be performed with good reproducibility. The insulating film 16 of the present invention may be a natural oxide film formed by leaving the SOI substrate in the air or a chemical oxide film formed using an oxidizing agent such as sulfated peroxide.
A thermal oxide film formed by thermal oxidation may be used.
【００１４】[0014]
【実施例】次に本発明の実施例を比較例とともに説明す
る。 ＜実施例１＞擬似ＭＯＳＦＥＴとしてＳＯＩ薄膜がｐ型
であるＳＩＭＯＸ技術により作成されたＳＯＩ基板を用
意した。このＳＯＩ基板を炉内に入れ、５％酸素＋窒素
混合ガス雰囲気中で温度８５０℃、２７分保持してＳＯ
Ｉ基板のＳＯＩ薄膜表面に厚さ３ｎｍの熱酸化膜からな
る絶縁膜を形成した。次に図２に示す測定装置を用い、
太さφ１．０ｍｍ、先端加工Ｒ１２．５μｍのタングス
テン製のドレインプローブ及びソースプローブに１ｇの
分銅をそれぞれ載せて、両プローブを絶縁膜表面に突刺
し、プローブをＳＯＩ薄膜に直接接触させた状態で、Ｉ
ｄ−Ｖｇ特性を測定した。この測定は大気雰囲気下で、
１０分間隔で４回行った。Next, examples of the present invention will be described together with comparative examples. <Example 1> An SOI substrate prepared by a SIMOX technique in which an SOI thin film is a p-type was prepared as a pseudo MOSFET. This SOI substrate was placed in a furnace and kept at a temperature of 850 ° C. for 27 minutes in a 5% oxygen + nitrogen mixed gas atmosphere.
An insulating film made of a thermal oxide film having a thickness of 3 nm was formed on the surface of the SOI thin film of the I substrate. Next, using the measuring device shown in FIG.
A 1 g weight is placed on each of a tungsten drain probe and a source probe having a diameter of 1.0 mm and a tip processing R of 12.5 μm, and both probes are pierced into the insulating film surface, and the probes are brought into direct contact with the SOI thin film. , I
The d-Vg characteristics were measured. This measurement was performed in an air atmosphere.
Performed 4 times at 10 minute intervals.
【００１５】＜実施例２＞実施例１と同一のＳＯＩ基板
を用意し、このＳＯＩ基板を炉内に入れ、１００％酸素
ガス雰囲気中で温度８５０℃、４５分保持してＳＯＩ基
板のＳＯＩ薄膜表面に厚さ１０ｎｍの熱酸化膜からなる
絶縁膜を形成した。次に実施例１と同一の装置を用い
て、太さφ１．０ｍｍ、先端加工Ｒ２．５μｍのタング
ステン製のドレインプローブ及びソースプローブに５０
ｇの分銅をそれぞれ載せ、両プローブを絶縁膜表面に突
刺し、プローブをＳＯＩ薄膜に直接接触させた状態でＩ
ｄ−Ｖｇ特性を測定した。この測定は大気雰囲気下、１
０分間隔で４回行った。Example 2 An SOI substrate identical to that of Example 1 was prepared, and this SOI substrate was placed in a furnace and kept at a temperature of 850 ° C. for 45 minutes in a 100% oxygen gas atmosphere. An insulating film made of a thermal oxide film having a thickness of 10 nm was formed on the surface. Next, using the same apparatus as in Example 1, a drain probe and a source probe made of tungsten having a diameter of 1.0 mm and a tip end of 2.5 μm were used.
g of weight is placed on each, the probes are pierced into the surface of the insulating film, and the probes are directly contacted with the SOI thin film.
The d-Vg characteristics were measured. This measurement was performed in an air atmosphere.
Performed 4 times at 0 minute intervals.
【００１６】＜比較例１＞実施例１と同一のＳＯＩ基板
を用意し、この基板を硫酸化過水で洗浄した後、フッ酸
で洗浄し、ＳＯＩ薄膜表面の自然酸化膜を除去した。実
施例１と同一の装置を用いて、太さφ１．０ｍｍ、先端
加工Ｒ１２．５μｍのタングステン製のドレインプロー
ブ及びソースプローブに２０ｇの分銅をそれぞれ載せ、
両プローブをベアなＳＯＩ薄膜表面に接触させた状態で
Ｉｄ−Ｖｇ特性を測定した。この測定はフッ酸洗浄後、
１時間以内で大気雰囲気下、１０分間隔で５回行った。Comparative Example 1 The same SOI substrate as in Example 1 was prepared, and the substrate was washed with sulfated hydrogen peroxide and then with hydrofluoric acid to remove a natural oxide film on the surface of the SOI thin film. Using the same apparatus as in Example 1, a weight of 20 g was placed on each of a tungsten drain probe and a source probe each having a diameter of 1.0 mm and a tip processing R of 12.5 μm,
The Id-Vg characteristics were measured with both probes in contact with the bare SOI thin film surface. This measurement is performed after cleaning with hydrofluoric acid.
The test was performed five times at intervals of 10 minutes in an air atmosphere within one hour.
【００１７】＜比較評価＞実施例１，２及び比較例１の
各測定はドレイン電圧を１．０ボルトに固定し、ゲート
電圧を−４ボルトから２ボルトに変化させたときのドレ
イン電流を求めることにより行った。実施例１のＩｄ−
Ｖｇ特性図を図４に、実施例２のＩｄ−Ｖｇ特性図を図
５に、比較例１のＩｄ−Ｖｇ特性図を図６にそれぞれ示
す。比較例１では図６より明らかなように測定値にばら
つきがあり、時間が経つにつれてＳＯＩ薄膜の表面に自
然酸化膜が形成されたことに伴うＩｄ−Ｖｇ特性の変動
が見られた。これに対して、実施例１及び２では図４及
び図５より明らかなように経時変化による影響は殆ど見
られず、Ｉｄ−Ｖｇ特性はほぼ一定であった。<Comparative Evaluation> In each measurement of Examples 1 and 2 and Comparative Example 1, the drain current is obtained when the drain voltage is fixed at 1.0 volt and the gate voltage is changed from -4 volts to 2 volts. It was done by doing. Id of Example 1
FIG. 4 shows a Vg characteristic diagram, FIG. 5 shows an Id-Vg characteristic diagram of Example 2, and FIG. 6 shows an Id-Vg characteristic diagram of Comparative Example 1. As is clear from FIG. 6, in Comparative Example 1, the measured values fluctuated, and the Id-Vg characteristics fluctuated over time due to the formation of a natural oxide film on the surface of the SOI thin film. On the other hand, in Examples 1 and 2, as is clear from FIGS. 4 and 5, almost no influence due to the change with time was observed, and the Id-Vg characteristics were almost constant.
【００１８】[0018]
【発明の効果】以上述べたように、本発明によれば、擬
似ＭＯＳＦＥＴを用いてのＳＯＩ基板のＩｄ−Ｖｇ特性
を、ＳＯＩ薄膜表面に厚さ１ｎｍ〜１μｍの絶縁膜を形
成した後、ドレインプローブ及びソースプローブをそれ
ぞれ絶縁膜に突刺してＳＯＩ薄膜に直接接触した状態で
測定するか、或いはＳＯＩ薄膜表面に厚さ２ｎｍ〜１μ
ｍの絶縁膜を形成し、絶縁膜表面に所定のパターンのレ
ジスト層を形成し、レジスト層をマスクにして絶縁膜を
エッチングし、レジスト層を除去してＳＯＩ基板を洗浄
し、絶縁膜をマスクにしてエッチングにより表出したＳ
ＯＩ薄膜表面に金属を堆積して一対の電極を形成した
後、一対の電極にドレインプローブ及びソースプローブ
をそれぞれ接触した状態で測定することにより、ＳＯＩ
薄膜の表面状態の影響を受けずに測定できるため再現性
よくＩｄ−Ｖｇ特性を測定することができる。この結
果、Ｉｄ−Ｖｇ特性における経時変化による影響を最小
限にすることができる。As described above, according to the present invention, the Id-Vg characteristics of an SOI substrate using a pseudo MOSFET are measured by forming an insulating film having a thickness of 1 nm to 1 μm on the surface of an SOI thin film and then forming a drain. The probe and the source probe are respectively pierced into the insulating film and measured in a state of directly contacting the SOI thin film, or the thickness is 2 nm to 1 μm on the surface of the SOI thin film.
m, an insulating film having a predetermined pattern is formed on the surface of the insulating film, the insulating film is etched using the resist layer as a mask, the resist layer is removed, the SOI substrate is washed, and the insulating film is masked. S expressed by etching
After a metal is deposited on the surface of the OI thin film to form a pair of electrodes, measurement is performed with the drain probe and the source probe in contact with the pair of electrodes, respectively.
Since the measurement can be performed without being affected by the surface state of the thin film, the Id-Vg characteristics can be measured with good reproducibility. As a result, it is possible to minimize the influence of the change over time on the Id-Vg characteristics.
【図１】本発明第１の実施の形態における擬似ＭＯＳＦ
ＥＴの断面図。FIG. 1 shows a pseudo MOSF according to a first embodiment of the present invention.
Sectional drawing of ET.
【図２】この実施の形態における測定装置の構成図。FIG. 2 is a configuration diagram of a measuring device according to the embodiment.
【図３】本第２の実施の形態における擬似ＭＯＳＦＥＴ
の製造方法を工程順に示す断面図。FIG. 3 is a pseudo MOSFET according to the second embodiment.
Sectional drawing which shows the manufacturing method of FIG.
【図４】実施例１におけるＩｄ−Ｖｇ特性図FIG. 4 is an Id-Vg characteristic diagram in Example 1.
【図５】実施例２におけるＩｄ−Ｖｇ特性図FIG. 5 is an Id-Vg characteristic diagram in Example 2.
【図６】比較例１におけるＩｄ−Ｖｇ特性図FIG. 6 is an Id-Vg characteristic diagram in Comparative Example 1.
【図７】従来例を示す図１に対応する断面図。FIG. 7 is a sectional view showing a conventional example and corresponding to FIG.
【図８】自然酸化膜が形成された図７に対応する断面
図。FIG. 8 is a sectional view corresponding to FIG. 7 in which a natural oxide film is formed.
１０ ＳＯＩ基板 １３ ＳＯＩ薄膜 １６ 絶縁膜 １７ ドレインプローブ １８ ソースプローブ ２９ レジスト層 ３４ 電極 Reference Signs List 10 SOI substrate 13 SOI thin film 16 Insulating film 17 Drain probe 18 Source probe 29 Resist layer 34 Electrode
Claims (3)
Ｉｄ−Ｖｇ特性を測定する方法において、 前記ＳＯＩ基板(10)のＳＯＩ薄膜(13)表面に厚さ１ｎｍ
〜１μｍの絶縁膜(16)を形成した後、ドレインプローブ
(17)及びソースプローブ(18)をそれぞれ前記絶縁膜(16)
に突刺して前記ＳＯＩ薄膜(13)に直接接触した状態で前
記Ｉｄ−Ｖｇ特性を測定することを特徴とする擬似ＭＯ
ＳＦＥＴの測定方法。1. A method for measuring the Id-Vg characteristics of an SOI substrate using a pseudo MOSFET, wherein the SOI thin film (13) of the SOI substrate (10) has a thickness of 1 nm.
After forming an insulating film (16) of ~ 1 μm, drain probe
(17) and the source probe (18) respectively the insulating film (16)
And measuring the Id-Vg characteristic in a state of directly contacting the SOI thin film (13) by piercing the SOI thin film (13).
SFET measurement method.
Ｉｄ−Ｖｇ特性を測定する方法において、 前記ＳＯＩ基板(10)のＳＯＩ薄膜(13)表面に厚さ２ｎｍ
〜１μｍの絶縁膜(16)を形成し、 前記絶縁膜(16)表面に所定のパターンのレジスト層(29)
を形成し、 前記レジスト層(29)をマスクにして前記絶縁膜(16)をエ
ッチングし、 前記レジスト層(29)を除去して前記ＳＯＩ基板(10)を洗
浄し、 前記絶縁膜(16)をマスクにしてエッチングにより表出し
た前記ＳＯＩ薄膜(13)表面に金属を堆積して一対の電極
(34)を形成した後、 前記一対の電極(34)にドレインプローブ(17)及びソース
プローブ(18)をそれぞれ接触した状態で前記Ｉｄ−Ｖｇ
特性を測定することを特徴とする擬似ＭＯＳＦＥＴの測
定方法。2. A method for measuring the Id-Vg characteristics of an SOI substrate using a pseudo MOSFET, wherein the SOI thin film (13) of the SOI substrate (10) has a thickness of 2 nm.
Forming an insulating film (16) of about 1 μm, a resist pattern (29) having a predetermined pattern on the surface of the insulating film (16);
The insulating film (16) is etched using the resist layer (29) as a mask, the resist layer (29) is removed and the SOI substrate (10) is washed, and the insulating film (16) is formed. A metal is deposited on the surface of the SOI thin film (13) exposed by etching using
After forming (34), the Id-Vg in a state where the drain probe (17) and the source probe (18) are in contact with the pair of electrodes (34), respectively.
A method for measuring a pseudo MOSFET, comprising measuring characteristics.
は熱酸化膜である請求項１又は２記載の擬似ＭＯＳＦＥ
Ｔの測定方法。3. The pseudo-MOSFE according to claim 1, wherein the insulating film is a natural oxide film, a chemical oxide film or a thermal oxide film.
Method for measuring T.
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|---|---|---|---|
| JP2000071452A JP2001267384A (en) | 2000-03-15 | 2000-03-15 | Measurement method of pseudo-mosfet |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000071452A JP2001267384A (en) | 2000-03-15 | 2000-03-15 | Measurement method of pseudo-mosfet |
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|---|---|
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ID=18590037
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