JP2001230363A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
JP2001230363A
JP2001230363A JP2000035295A JP2000035295A JP2001230363A JP 2001230363 A JP2001230363 A JP 2001230363A JP 2000035295 A JP2000035295 A JP 2000035295A JP 2000035295 A JP2000035295 A JP 2000035295A JP 2001230363 A JP2001230363 A JP 2001230363A
Authority
JP
Japan
Prior art keywords
semiconductor device
csp
lead
leads
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000035295A
Other languages
Japanese (ja)
Inventor
Yuuki Yamate
勇樹 山手
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Semiconductor Package and Test Solutions Co Ltd
Original Assignee
Hitachi Hokkai Semiconductor Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Hokkai Semiconductor Ltd, Hitachi Ltd filed Critical Hitachi Hokkai Semiconductor Ltd
Priority to JP2000035295A priority Critical patent/JP2001230363A/en
Publication of JP2001230363A publication Critical patent/JP2001230363A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve a contact property between a connecting terminal of a member for supporting a semiconductor device and a lead of the semiconductor device. SOLUTION: There are provided a tab 1e for supporting a semiconductor chip 2 having a semiconductor integrated circuit formed on its main surface, a plurality of leads 1a that are disposed in the periphery of the tab 1e and provided with a terminal connecting surface 1b exposed in the outer periphery of the rear surface 3a of a sealed portion 3, the sealed portion formed by sealing the semiconductor chip and bonding wires for connecting pads of the semiconductor chip 2 and leads 1a corresponding to them. Since the plurality of leads 1a disposed in the outer periphery of the rear surface 3a of the sealed portion 3 are provided while inclined in a direction perpendicular to their array direction, a CSP 7 can be reliably brought into contact with a mount board or a connecting terminal of a socket when the CSP 7 is mounted on the mount board or the socket. As a result, the contact property of the CSP 7 can be improved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
技術に関し、特に、小形の半導体装置を実装基板やソケ
ットに実装する際のリードと接続端子のコンタクト性向
上に適用して有効な技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor device, and more particularly to a technology which is effective when applied to the improvement of contact between leads and connection terminals when a small semiconductor device is mounted on a mounting board or a socket. .

【０００２】[0002]

【従来の技術】以下に説明する技術は、本発明を研究、
完成するに際し、本発明者によって検討されたものであ
り、その概要は次のとおりである。2. Description of the Related Art The technology described below studies the present invention,
Upon completion, they were examined by the inventor, and the outline is as follows.

【０００３】小形化を図った半導体装置として、ＣＳＰ
（Chip Scale PackageまたはChip Size Package)と呼ば
れるチップサイズまたは半導体チップより若干大きい程
度の小形パッケージが開発されている。[0003] As a miniaturized semiconductor device, CSP is used.
A small package called a (Chip Scale Package or Chip Size Package) having a size slightly larger than a chip size or a semiconductor chip has been developed.

【０００４】前記ＣＳＰでは、種々の構造のものが考案
されているが、封止によって形成された封止部の裏面
（半導体装置実装側の面）に外部端子が設けられる構造
のものとしては、主に、半田ボールなどの外部端子が格
子状に配列されるエリアアレイ形と、リードなどの外部
端子が裏面外周に配列されるペリフェラル形とに分けら
れる。In the CSP, various structures have been devised. As a structure in which external terminals are provided on the back surface (the surface on the semiconductor device mounting side) of a sealing portion formed by sealing, It is mainly classified into an area array type in which external terminals such as solder balls are arranged in a grid pattern, and a peripheral type in which external terminals such as leads are arranged on the outer periphery of the back surface.

【０００５】なお、ペリフェラル形のＣＳＰは、ＱＦＮ
（Quad Flat Non-leaded Package)などとも呼ばれてお
り、このＱＦＮの電気的特性などの検査の際には、ソケ
ット（半導体装置支持部材）に嵌めて検査を行ってい
る。[0005] The peripheral CSP is a QFN.
(Quad Flat Non-leaded Package) or the like. When inspecting the electrical characteristics of the QFN, the QFN is fitted to a socket (semiconductor device supporting member) and inspected.

【０００６】ここで、種々のＣＳＰの構造とその実装技
術については、例えば、日刊工業新聞社１９９９年９月
１日発行、「電子技術１９９９／９月号／Ｖｏｌ．４
１、Ｎｏ．１０、ＣＳＰ／フリップチップ実装技術の最
前線」、１〜１３頁に記載されている。[0006] The structures of various CSPs and their mounting techniques are described in, for example, Nikkan Kogyo Shimbun, September 1, 1999, “Electronic Technology 1999 / September / Vol.
1, No. 10, forefront of CSP / flip chip mounting technology ", pp. 1-13.

【０００７】[0007]

【発明が解決しようとする課題】ところが、前記した技
術のＱＦＮは、スタンドオフ（表面実装における実装基
板側の接続端子と半導体装置の封止部との間の間隔）が
１０μｍ程度と非常に小さなパッケージであるため、Ｑ
ＦＮをソケットにセットした際、ソケットのコンタクト
ピンなどの接続端子のエッジにバリが形成されている
と、ＱＦＮに僅かな位置ずれがあるだけでも、ソケット
のコンタクトピンとＱＦＮのリードとが接触する前にコ
ンタクトピンのバリとＱＦＮの封止部の裏面とが接触し
てしまう。However, the QFN of the above-mentioned technique has a very small standoff (a distance between a connection terminal on the mounting substrate side in surface mounting and a sealing portion of the semiconductor device) of about 10 μm. Because it is a package, Q
If the burrs are formed at the edges of the connection terminals such as the contact pins of the socket when the FN is set in the socket, even if there is only a slight misalignment in the QFN, the contact pins of the socket and the leads of the QFN do not come into contact. In this case, the burrs of the contact pins come into contact with the back surface of the QFN sealing portion.

【０００８】その結果、コンタクトピンとＱＦＮのリー
ドとが接触せずにコンタクト不良を引き起こすことが問
題となる。As a result, there is a problem that the contact pin and the lead of the QFN do not come into contact with each other and cause a contact failure.

【０００９】本発明の目的は、半導体装置支持部材の接
続端子とリードとのコンタクト性の向上を図る半導体装
置の製造方法を提供することにある。It is an object of the present invention to provide a method of manufacturing a semiconductor device for improving the contact between a connection terminal of a semiconductor device support member and a lead.

【００１０】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

【００１１】[0011]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

【００１２】すなわち、本発明の半導体装置の製造方法
は、半導体チップを支持可能なチップ支持部とこれの周
囲に配置された複数のリードとを有するリードフレーム
を準備する工程と、前記リードフレームの前記チップ支
持部と前記半導体チップとを接合する工程と、前記半導
体チップの表面電極とこれに対応する前記リードとを接
続する工程と、前記半導体チップを封止して前記リード
の端子接続面を前記半導体装置実装側の面に露出させて
封止部を形成する工程と、複数の前記リードを前記リー
ドフレームの枠部から分離する工程と、前記半導体装置
を支持可能な半導体装置支持部材の複数の接続端子およ
び前記半導体装置の複数の前記リードのうち、何れか一
方を配列方向と直角を成す方向に対して傾斜させて配置
して前記接続端子と前記リードとを接触させて前記半導
体装置を前記半導体装置支持部材に実装する工程とを有
するものである。That is, in the method of manufacturing a semiconductor device according to the present invention, a step of preparing a lead frame having a chip supporting portion capable of supporting a semiconductor chip and a plurality of leads arranged around the chip supporting portion is provided. Bonding the chip support portion and the semiconductor chip, connecting the surface electrode of the semiconductor chip and the corresponding lead, and sealing the semiconductor chip to form a terminal connection surface of the lead. Forming a sealing portion by exposing the semiconductor device on the semiconductor device mounting side surface, separating a plurality of leads from a frame portion of the lead frame, and forming a plurality of semiconductor device supporting members capable of supporting the semiconductor device. One of the connection terminal and the plurality of leads of the semiconductor device is disposed so as to be inclined with respect to a direction perpendicular to the arrangement direction. And a step of mounting the semiconductor device on the semiconductor device supporting member in contact with said lead.

【００１３】本発明によれば、半導体装置実装時に、半
導体装置支持部材の接続端子と半導体装置のリードとを
確実に接触させることができ、したがって、半導体装置
のコンタクト性の向上を図ることができる。According to the present invention, the connection terminals of the semiconductor device supporting member and the leads of the semiconductor device can be reliably brought into contact with each other when the semiconductor device is mounted, so that the contact properties of the semiconductor device can be improved. .

【００１４】その結果、コンタクト不良による再検査な
どの付帯作業を低減できる。As a result, it is possible to reduce incidental work such as re-inspection due to contact failure.

【００１５】さらに、再検査を低減できるため、検査用
テスタを有効活用することができ、その結果、検査のス
ループットを向上できる。Further, since re-inspection can be reduced, an inspection tester can be effectively used, and as a result, inspection throughput can be improved.

【００１６】[0016]

【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。なお、実施の形態を説明す
るための全図において、同一の機能を有する部材には同
一の符号を付し、その繰り返しの説明は省略する。Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

【００１７】図１は本発明の実施の形態の半導体装置の
製造方法によって組み立てられる半導体装置の構造の一
例を示す図であり、（ａ）は平面図、（ｂ）は側面図、
（ｃ）は底面図、図２は図１に示す半導体装置の構造を
示す断面図、図３は図１に示す半導体装置の製造方法の
実施の形態の一例を示す製造プロセスフロー図、図４は
図１に示す半導体装置の製造方法で用いられるリードフ
レームの構造の一例を示す部分平面図、図５は図１に示
す半導体装置の実装基板への実装状態の一例を示す部分
平面図、図６は図１に示す半導体装置のソケットへの実
装状態の一例を示す部分断面図、図７は図１に示す半導
体装置のソケットへの実装時のパッケージ側のリードと
基板側の接続端子との接触状態の一例を示す図であり、
（ａ）は平面図、（ｂ）は部分断面図である。FIGS. 1A and 1B show an example of a structure of a semiconductor device assembled by a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1A is a plan view, FIG.
FIG. 2C is a bottom view, FIG. 2 is a cross-sectional view showing the structure of the semiconductor device shown in FIG. 1, FIG. 3 is a manufacturing process flow chart showing an example of an embodiment of a method of manufacturing the semiconductor device shown in FIG. FIG. 5 is a partial plan view showing an example of the structure of a lead frame used in the method of manufacturing the semiconductor device shown in FIG. 1, and FIG. 5 is a partial plan view showing an example of a mounting state of the semiconductor device shown in FIG. 6 is a partial cross-sectional view showing an example of a mounting state of the semiconductor device shown in FIG. 1 to the socket, and FIG. 7 is a diagram showing the connection between the package-side lead and the board-side connection terminal when mounting the semiconductor device shown in FIG. It is a diagram showing an example of a contact state,
(A) is a plan view, (b) is a partial sectional view.

【００１８】本実施の形態の半導体装置の製造方法によ
って組み立てられる図１に示す半導体装置は、チップサ
イズまたは半導体チップ２より若干大きい程度の小形
で、かつ表面実装形のＣＳＰ７（ＱＦＮともいう）であ
り、比較的ピン数が少なく、例えば、携帯電子機器や小
形電子機器などに組み込まれる半導体パッケージであ
る。The semiconductor device shown in FIG. 1 assembled by the method of manufacturing a semiconductor device according to the present embodiment is a CSP 7 (also referred to as QFN) having a small chip size or a size slightly larger than the semiconductor chip 2 and a surface mount type. The semiconductor package has a relatively small number of pins and is incorporated in, for example, a portable electronic device or a small electronic device.

【００１９】また、モールドによって形成された封止部
３の半導体装置実装側の面（以降、裏面３ａという）の
外周部に外部端子である複数のリード１ａが並んで配置
されたペリフェラル形（ＱＦＮではボトムリード形とも
いう）のものである。A peripheral type (QFN) in which a plurality of leads 1a as external terminals are arranged side by side on an outer peripheral portion of a semiconductor device mounting side surface (hereinafter referred to as a back surface 3a) of a sealing portion 3 formed by molding. (Also referred to as bottom lead type).

【００２０】図１、図２を用いて前記ＣＳＰ７の構成に
ついて説明すると、主面２ｂに半導体集積回路が形成さ
れた半導体チップ２を支持するタブ１ｅ（チップ支持
部）と、タブ１ｅの周囲に配置され、かつ封止部３の裏
面３ａの外周部に露出する端子接続面１ｂを備えた外部
端子てもある複数のリード１ａと、半導体チップ２を樹
脂封止して形成した封止部３と、半導体チップ２のパッ
ド２ａとこれに対応するリード１ａとを接続するボンデ
ィングワイヤ４とからなり、封止部３の裏面３ａの外周
部に配置された複数のリード１ａが、図１（ｃ）に示す
ように、その配列方向と直角を成す方向に対してそれぞ
れ傾斜して設けられているものである。The configuration of the CSP 7 will be described with reference to FIGS. 1 and 2. A tab 1e (chip supporting portion) for supporting a semiconductor chip 2 having a semiconductor integrated circuit formed on a main surface 2b, and a tub 1e surrounding the tab 1e. A plurality of leads 1a which are arranged and are also external terminals having a terminal connection surface 1b exposed at an outer peripheral portion of a back surface 3a of the sealing portion 3, and a sealing portion 3 formed by resin sealing the semiconductor chip 2. And a plurality of leads 1a arranged on the outer peripheral portion of the back surface 3a of the sealing portion 3 as shown in FIG. 1 (c). The bonding wires 4 connect the pads 2a of the semiconductor chip 2 and the corresponding leads 1a. As shown in FIG. 2), they are provided to be inclined with respect to the direction perpendicular to the arrangement direction.

【００２１】すなわち、本実施の形態のＣＳＰ７では、
封止部３の裏面３ａに設けられた複数のリード１ａがそ
の配列方向と直角を成す方向に対して各辺ごとにそれぞ
れ同一方向に僅かに傾いて配置されており、これによ
り、図５に示す実装基板８（半導体装置支持部材）や図
６に示すソケット９（半導体装置支持部材）にＣＳＰ７
を実装した際に、ＣＳＰ７の各リード１ａとそれらの基
板側の接続端子８ａ，９ｈ（図７参照）との接触を確実
に行うことを可能にするものである。That is, in the CSP 7 of this embodiment,
A plurality of leads 1a provided on the back surface 3a of the sealing portion 3 are slightly inclined in the same direction on each side with respect to a direction perpendicular to the arrangement direction. The CSP 7 is mounted on the mounting substrate 8 (semiconductor device supporting member) shown in FIG.
Is mounted, the leads 1a of the CSP 7 and their connection terminals 8a, 9h (see FIG. 7) on the substrate side can be reliably contacted.

【００２２】なお、それぞれのリード１ａの配列方向と
直角を成す方向に対しての傾斜角度は、非常に小さなも
のである。The inclination angle of each of the leads 1a with respect to the direction perpendicular to the arrangement direction is very small.

【００２３】また、ＣＳＰ７における各リード１ａは、
インナリードとアウタリードとの両者の機能を併せ持っ
たものであり、それぞれの外側端部には、図４に示すリ
ードフレーム１の枠部１ｆから切断分離した際の切断し
ろが残留するため、図１（ａ),（ｃ）に示すように、各
リード１ａの外側端部が封止部３から数十〜数百μｍ程
度突出する構造になっている。Each lead 1a in the CSP 7 is:
1 has both functions of an inner lead and an outer lead, and a margin for cutting when separated from the frame 1f of the lead frame 1 shown in FIG. As shown in (a) and (c), the outer end of each lead 1a projects from the sealing portion 3 by about several tens to several hundreds of micrometers.

【００２４】また、本実施の形態のＣＳＰ７では、図２
に示すように、半導体チップ２がダイボンド材５（例え
ば、樹脂などによるペースト材）によってタブ１ｅに固
定されている。Further, in the CSP 7 of the present embodiment, FIG.
As shown in (1), the semiconductor chip 2 is fixed to the tab 1e by a die bond material 5 (for example, a paste material such as a resin).

【００２５】さらに、本実施の形態のＣＳＰ７には、各
リード１ａの端子接続面１ｂに半田めっき層６が形成さ
れている。Further, in the CSP 7 of the present embodiment, a solder plating layer 6 is formed on the terminal connection surface 1b of each lead 1a.

【００２６】この半田めっき層６は、ＣＳＰ７を図５に
示す実装基板８などに半田実装した際の半田接続強度を
高めるためのものであり、モールドによる樹脂封止を行
った後、各リード１ａに半田めっき処理を行い、半田め
っき層６を形成するものである。This solder plating layer 6 is used to increase the solder connection strength when the CSP 7 is solder-mounted on the mounting board 8 shown in FIG. 5 and the like. Is subjected to a solder plating process to form a solder plating layer 6.

【００２７】なお、半田めっき層６の厚さは、例えば、
１０μｍ程度であり、この半田めっき層６の厚さ分が、
ＣＳＰ７におけるスタンドオフ（表面実装における実装
基板８の接続端子８ａとＣＳＰ７の封止部３との間の間
隔）となる。The thickness of the solder plating layer 6 is, for example,
About 10 μm, and the thickness of the solder plating layer 6 is
This is a standoff in the CSP 7 (an interval between the connection terminal 8a of the mounting board 8 and the sealing portion 3 of the CSP 7 in surface mounting).

【００２８】また、半導体チップ２の表面電極であるパ
ッド２ａと、これに対応するリード１ａのボンディング
面１ｃとを電気的に接続するボンディングワイヤ４は、
例えば、金線やアルミニウム線などである。The bonding wire 4 for electrically connecting the pad 2a, which is the surface electrode of the semiconductor chip 2, to the bonding surface 1c of the corresponding lead 1a is
For example, a gold wire or an aluminum wire is used.

【００２９】さらに、封止部３は、モールド方法による
樹脂封止によって形成され、その際用いられる封止用の
樹脂は、例えば、熱硬化性のエポキシ樹脂などである。Further, the sealing portion 3 is formed by resin sealing by a molding method, and a sealing resin used at this time is, for example, a thermosetting epoxy resin.

【００３０】また、リード１ａやタブ１ｅは、例えば、
Ｃｕ、ＦｅまたはＦｅ−Ｎｉなどによって形成され、そ
の厚さは、例えば、０.1〜０.2ｍｍ程度の薄板材であ
る。The leads 1a and tabs 1e are, for example,
It is formed of Cu, Fe, Fe-Ni, or the like, and has a thickness of, for example, about 0.1 to 0.2 mm.

【００３１】次に、ＣＳＰ７の製造に用いられる図４に
示すリードフレーム１の構成について説明する。リード
フレーム１は、半導体チップ２を支持可能なタブ１ｅ
（チップ支持部）と、タブ１ｅの周囲に配置され、かつ
ＣＳＰ７の封止部３の裏面３ａに露出する端子接続面１
ｂをそれぞれに有するとともに、その配列方向と直角を
成す方向に対して各辺ごとにそれぞれ同一方向に傾斜し
て設けられた複数のリード１ａと、タブ１ｅを支持する
タブ吊りリード１ｄと、各リード１ａやタブ吊りリード
１ｄを支持する枠部１ｆとからなる薄板状の金属板であ
り、１枚のリードフレーム１から複数個のＣＳＰ７を製
造することが可能な短冊状の多連のものである。Next, the configuration of the lead frame 1 shown in FIG. 4 used for manufacturing the CSP 7 will be described. The lead frame 1 has a tab 1e capable of supporting the semiconductor chip 2.
(Chip supporting portion) and a terminal connection surface 1 disposed around the tab 1 e and exposed on the back surface 3 a of the sealing portion 3 of the CSP 7.
b, a plurality of leads 1a provided inclining in the same direction on each side with respect to a direction perpendicular to the arrangement direction, and a tab suspension lead 1d for supporting a tab 1e; It is a thin metal plate composed of a lead 1a and a frame portion 1f supporting the tab suspension lead 1d, and is a strip-shaped multiple unit capable of manufacturing a plurality of CSPs 7 from one lead frame 1. is there.

【００３２】つまり、１枚のリードフレーム１には、１
個のＣＳＰ７に対応したパッケージ領域が複数個形成さ
れており、さらに、その枠部１ｆには、ダイボンディン
グ時やワイヤボンディング時にリードフレーム１を搬送
する際の複数のガイド用長孔１ｇおよび位置決め孔１ｈ
が形成されている。That is, one lead frame 1 has 1
A plurality of package regions corresponding to the CSPs 7 are formed, and a plurality of guide slots 1g and positioning holes for transporting the lead frame 1 at the time of die bonding or wire bonding are formed in the frame portion 1f. 1h
Are formed.

【００３３】なお、リードフレーム１の材料は、例え
ば、銅（Ｃｕ）、鉄（Ｆｅ）、または、鉄とニッケルと
の合金（Ｆｅ−Ｎｉ）などであり、その厚さは、例え
ば、０.1〜０.2ｍｍ程度であるが、前記材料や前記厚さ
などは、これらに限定されるものではない。The material of the lead frame 1 is, for example, copper (Cu), iron (Fe), or an alloy of iron and nickel (Fe-Ni). The thickness is about 1 to 0.2 mm, but the material and the thickness are not limited to these.

【００３４】次に、本実施の形態の半導体装置（ＣＳＰ
７）の製造方法を図３に示す製造プロセスフロー図にし
たがって説明する。Next, the semiconductor device of this embodiment (CSP
The manufacturing method 7) will be described with reference to the manufacturing process flow chart shown in FIG.

【００３５】なお、前記ＣＳＰ７の製造方法は、図４に
示すリードフレーム１を用いて行うものである。The method of manufacturing the CSP 7 is performed using the lead frame 1 shown in FIG.

【００３６】まず、ステップＳ１により、半導体チップ
２を支持可能なタブ１ｅと、タブ１ｅの周囲に配置さ
れ、かつ配列方向と直角を成す方向に対してそれぞれ同
一方向に傾斜して設けられた複数のリード１ａとを有す
る図４に示すリードフレーム１を準備する。First, in step S1, a tab 1e capable of supporting the semiconductor chip 2 and a plurality of tabs disposed around the tab 1e and provided in the same direction with respect to a direction perpendicular to the arrangement direction are provided. The lead frame 1 shown in FIG.

【００３７】なお、リードフレーム１は、１枚のリード
フレーム１から複数個のＣＳＰ７を製造することが可能
な短冊状の多連のものであり、１枚のリードフレーム１
には、１個のＣＳＰ７に対応したパッケージ領域が複数
個形成されている。Note that the lead frame 1 is a strip-shaped multiple unit capable of manufacturing a plurality of CSPs 7 from one lead frame 1.
, A plurality of package regions corresponding to one CSP 7 are formed.

【００３８】続いて、ステップＳ２により、半導体チッ
プ２を供給し、その後、ステップＳ３により、リードフ
レーム１のタブ１ｅと半導体チップ２の裏面２ｃとを接
合する。Subsequently, in step S2, the semiconductor chip 2 is supplied, and then, in step S3, the tab 1e of the lead frame 1 and the back surface 2c of the semiconductor chip 2 are joined.

【００３９】すなわち、図２に示すように、リードフレ
ーム１（図４参照）のタブ１ｅにダイボンド材５を介し
て主面２ｂを上方に向けて半導体チップ２を固定するチ
ップマウント（ダイボンディングまたはペレットボンデ
ィングともいう）を行う。That is, as shown in FIG. 2, a chip mount (die bonding or die bonding) for fixing the semiconductor chip 2 to the tab 1e of the lead frame 1 (see FIG. 4) with the main surface 2b facing upward via the die bonding material 5. Pellet bonding).

【００４０】その後、半導体チップ２のパッド２ａ（表
面電極）と、これに対応するリード１ａのボンディング
面１ｃとをワイヤボンディング（ステップＳ４）によっ
て接続する。Thereafter, the pads 2a (surface electrodes) of the semiconductor chip 2 and the corresponding bonding surfaces 1c of the leads 1a are connected by wire bonding (step S4).

【００４１】さらに、ステップＳ５に示すように、モー
ルドによる半導体チップ２の樹脂封止を行う。Further, as shown in step S5, resin sealing of the semiconductor chip 2 by molding is performed.

【００４２】ここでは、半導体チップ２をモールドによ
って樹脂封止し、その際、各リード１ａのそれぞれの端
子接続面１ｂが、封止部３の裏面３ａ（半導体装置実装
側の面）にほぼ同一面となって露出するように樹脂封止
して封止部３を形成する。Here, the semiconductor chip 2 is sealed with a resin by molding, and at this time, each terminal connection surface 1b of each lead 1a is substantially the same as the back surface 3a of the sealing portion 3 (the surface on the semiconductor device mounting side). The sealing portion 3 is formed by resin sealing so as to be exposed as a surface.

【００４３】これにより、図１（ｃ）に示すように、各
リード１ａが封止部３の裏面３ａにこの裏面３ａとほぼ
同一面となって配置されるとともに、裏面３ａの外周部
においてその配列方向と直角を成す方向に対して各辺ご
とにそれぞれ同一方向に僅かに傾斜して配置される。Thus, as shown in FIG. 1 (c), each lead 1a is disposed on the back surface 3a of the sealing portion 3 so as to be substantially flush with the back surface 3a, and at the outer periphery of the back surface 3a. Each side is slightly inclined in the same direction with respect to a direction perpendicular to the arrangement direction.

【００４４】樹脂封止後、封止部３の裏面３ａに露出し
た各リード１ａの端子接続面１ｂに図２に示すような半
田めっき層６を形成する（ステップＳ６）。After resin sealing, a solder plating layer 6 as shown in FIG. 2 is formed on the terminal connection surface 1b of each lead 1a exposed on the back surface 3a of the sealing portion 3 (step S6).

【００４５】なお、各リード１ａに対しての半田めっき
については、例えば、予め、リードフレーム１の段階で
これの表面に外部装置（例えば、測定機器など）との接
続を可能にする表面処理、例えば、ＰｄやＰｄ−Ａｕな
どの表面処理が行われている場合には、樹脂封止後の半
田めっき層６の形成すなわち半田めっき処理は不要とな
る。For the solder plating on each lead 1a, for example, a surface treatment for enabling connection to an external device (for example, a measuring instrument or the like) on the surface of the lead frame 1 at the stage of the lead frame 1 is performed in advance. For example, when a surface treatment such as Pd or Pd-Au is performed, the formation of the solder plating layer 6 after resin sealing, that is, the solder plating process is not required.

【００４６】その後、複数のリード１ａおよびタブ吊り
リード１ｄをリードフレーム１の枠部１ｆから切断によ
って切り離すリード切断（ステップＳ７）を行って、リ
ードフレーム１の枠部１ｆから封止部３を含む各リード
１ａを分離して図１（ａ),（ｂ),（ｃ) に示す形状とす
る。Thereafter, lead cutting (step S7) is performed in which the plurality of leads 1a and tab suspension leads 1d are cut off from the frame 1f of the lead frame 1 by cutting, thereby including the sealing portion 3 from the frame 1f of the lead frame 1. Each lead 1a is separated into a shape shown in FIGS. 1 (a), 1 (b) and 1 (c).

【００４７】これにより、図１に示すＣＳＰ７を完成さ
せる（ステップＳ８）。Thus, the CSP 7 shown in FIG. 1 is completed (step S8).

【００４８】その後、ＣＳＰ７を半導体装置支持部材に
実装する。After that, the CSP 7 is mounted on the semiconductor device supporting member.

【００４９】本実施の形態では、前記半導体装置支持部
材が図５に示す実装基板８であり、ＣＳＰ７を実装基板
８に実装する場合と、前記半導体装置支持部材が図６に
示すソケット９であり、ＣＳＰ７をソケット９に実装す
る場合とをそれぞれ説明する。In this embodiment, the semiconductor device supporting member is the mounting substrate 8 shown in FIG. 5, and the CSP 7 is mounted on the mounting substrate 8, and the semiconductor device supporting member is the socket 9 shown in FIG. , And the case where the CSP 7 is mounted on the socket 9 will be described.

【００５０】まず、図５に示すように、ＣＳＰ７を実装
基板８に実装する場合は、例えば、半田リフローなどに
よってＣＳＰ７を実装基板８に実装する。First, as shown in FIG. 5, when mounting the CSP 7 on the mounting board 8, the CSP 7 is mounted on the mounting board 8 by, for example, solder reflow.

【００５１】その際、ＣＳＰ７は、各リード１ａが、そ
の封止部３の裏面３ａの外周部においてその配列方向と
直角を成す方向に対して各辺ごとにそれぞれ同一方向に
僅かに傾斜して配置されており、ＣＳＰ７と実装基板８
との間に多少の位置ずれが生じていても、図５に示すよ
うに、各リード１ａと、配列方向と直角を成す方向に対
してそれぞれほぼ平行に配置された実装基板８の接続端
子８ａとを確実に接触させることができる。At this time, the CSP 7 is configured such that each lead 1a is slightly inclined in the same direction on each side with respect to a direction perpendicular to the arrangement direction on the outer peripheral portion of the back surface 3a of the sealing portion 3. CSP 7 and mounting board 8
Even if there is some displacement between them, as shown in FIG. 5, each lead 1a and the connection terminal 8a of the mounting board 8 arranged substantially parallel to the direction perpendicular to the arrangement direction. Can be surely brought into contact.

【００５２】一方、ＣＳＰ７をソケット９に実装する場
合を図６、図７に示す。On the other hand, the case where the CSP 7 is mounted on the socket 9 is shown in FIGS.

【００５３】ここで、ソケット９は、例えば、半導体装
置の電気的特性検査などにおいて、シートコンタクト方
式でＣＳＰ７などを検査する際に用いるクラムシェルタ
イプのものである。Here, the socket 9 is of a clamshell type used for inspecting the CSP 7 or the like by a sheet contact method in, for example, an electrical characteristic inspection of a semiconductor device.

【００５４】したがって、ソケット９には、ＣＳＰ７の
外部端子数に応じたピン部材９ｆが設けられており、こ
のピン部材９ｆがテストボード１０に取り付けられてソ
ケット９とテストボード１０との電気的接続が行われ
る。Therefore, the socket 9 is provided with pin members 9f corresponding to the number of external terminals of the CSP 7, and the pin members 9f are attached to the test board 10 to electrically connect the socket 9 to the test board 10. Is performed.

【００５５】なお、ソケット９は、ＣＳＰ７が配置され
るソケット本体９ａと、ＣＳＰ７に荷重を印加する蓋部
材９ｂとからなり、この蓋部材９ｂには、蓋部材９ｂを
閉じた際に蓋部材９ｂをソケット本体９ａにロックする
フック部材９ｅや、ＣＳＰ７に荷重を掛けるバネ部材９
ｃおよび押圧子９ｄなどが設けられている。The socket 9 includes a socket body 9a on which the CSP 7 is disposed and a lid member 9b for applying a load to the CSP 7. The lid member 9b has a lid member 9b when the lid member 9b is closed. Hook member 9e for locking the CSP 7 to the socket body 9a and a spring member 9 for applying a load to the CSP 7
c and a pressing element 9d are provided.

【００５６】また、ソケット本体９ａ側には、検査時に
ＣＳＰ７とシートコンタクトを行うためのテープ状の回
路基板９ｇと、この回路基板９ｇを支持するベース部材
９ｉとが設けられている。The socket body 9a is provided with a tape-shaped circuit board 9g for making a sheet contact with the CSP 7 at the time of inspection, and a base member 9i for supporting the circuit board 9g.

【００５７】さらに、回路基板９ｇの表面（ＣＳＰ７を
支持する側の面）には、図７（ａ）に示すように、ＣＳ
Ｐ７の各リード１ａに対応して配置された複数のコンタ
クトピンである接続端子９ｈが設けられている。Further, as shown in FIG. 7A, the surface of the circuit board 9g (the surface on the side supporting the CSP 7) is CS
A connection terminal 9h, which is a plurality of contact pins arranged corresponding to each lead 1a of P7, is provided.

【００５８】このソケット９にＣＳＰ７をセットした場
合、ＣＳＰ７では、各リード１ａがその配列方向と直角
を成す方向に対してそれぞれ同一方向に僅かに傾斜して
配置されているため、ＣＳＰ７とソケット９の回路基板
９ｇとの間に多少の位置ずれが生じていても、図７
（ａ),（ｂ）に示すように、各リード１ａと、配列方向
と直角を成す方向に対してそれぞれほぼ平行に配置され
たソケット９の回路基板９ｇの接続端子９ｈとを確実に
接触させることができる。When the CSP 7 is set in the socket 9, the leads 1a of the CSP 7 are slightly inclined in the same direction with respect to the direction perpendicular to the arrangement direction. Even if there is a slight misalignment with the circuit board 9g of FIG.
As shown in (a) and (b), each lead 1a is securely brought into contact with the connection terminal 9h of the circuit board 9g of the socket 9 arranged substantially parallel to the direction perpendicular to the arrangement direction. be able to.

【００５９】本実施の形態の半導体装置（ＣＳＰ７）の
製造方法によれば、以下のような作用効果が得られる。According to the method of manufacturing the semiconductor device (CSP 7) of the present embodiment, the following operational effects can be obtained.

【００６０】すなわち、ＣＳＰ７の複数のリード１ａを
封止部３の裏面３ａにおいてその配列方向と直角を成す
方向に対して傾斜させて配置してＣＳＰ７を実装基板８
やソケット９などの半導体装置支持部材に実装すること
により、ＣＳＰ７のリード１ａと実装基板８の接続端子
８ａもしくはソケット９の接続端子９ｈとにおいて両者
が平行ではなく斜めに接触するため、接続端子８ａ，９
ｈとリード１ａとの接触マージンを増やすことができ
る。That is, the plurality of leads 1a of the CSP 7 are arranged on the back surface 3a of the sealing portion 3 so as to be inclined with respect to the direction perpendicular to the arrangement direction, and the CSP 7 is mounted on the mounting substrate 8
When the semiconductor device is mounted on a semiconductor device supporting member such as the socket 9 or the like, the leads 1a of the CSP 7 and the connection terminals 8a of the mounting board 8 or the connection terminals 9h of the socket 9 are not parallel but obliquely contact with each other. , 9
The contact margin between h and the lead 1a can be increased.

【００６１】これにより、実装基板８の接続端子８ａも
しくはソケット９の接続端子９ｈとＣＳＰ７のリード１
ａとを確実に接触させることができ、したがって、コン
タクトピンなどの接続端子９ｈのエッジなどにバリが形
成されている場合であっても前記コンタクトピンとＣＳ
Ｐ７のリード１ａとを確実に接触させることができる。Thus, the connection terminal 8a of the mounting board 8 or the connection terminal 9h of the socket 9 and the lead 1 of the CSP 7
a can be reliably brought into contact with each other. Therefore, even when burrs are formed at the edge of the connection terminal 9h such as a contact pin, the contact pin and the CS are not connected.
The lead 1a of P7 can be reliably contacted.

【００６２】その結果、ＣＳＰ７におけるリード１ａの
コンタクト性の向上を図ることができる。As a result, the contact property of the lead 1a in the CSP 7 can be improved.

【００６３】特に、スタンドオフの小さなＣＳＰ７に対
してそのリード１ａのコンタクト性の向上を図ることが
できる。In particular, it is possible to improve the contact property of the lead 1a with respect to the CSP 7 having a small standoff.

【００６４】その結果、コンタクト不良による再検査
（一回めの検査で不良と判定されたＣＳＰ７の再検査）
などの付帯作業を低減できる。As a result, re-inspection due to contact failure (re-inspection of CSP 7 determined to be defective in the first inspection)
And other incidental operations can be reduced.

【００６５】さらに、再検査を低減できるため、検査用
テスタを有効活用することができ、その結果、ＣＳＰ７
の検査のスループットを向上できる。Furthermore, since re-inspection can be reduced, an inspection tester can be effectively used, and as a result, the CSP7
Inspection throughput can be improved.

【００６６】また、ＣＳＰ７のコンタクト性の向上を図
ることができるため、ＣＳＰ７の歩留りを向上させるこ
とができる。Further, since the contact property of the CSP 7 can be improved, the yield of the CSP 7 can be improved.

【００６７】また、ＣＳＰ７のコンタクト性の向上を図
ることができるため、ＣＳＰ７をソケット９や実装基板
８などの半導体装置支持部材に実装する際のＣＳＰ７と
前記半導体装置支持部材の接続端子８ａ，９ｈとの位置
合わせにおいて、高精度の位置合わせを必要としないラ
フな位置合わせを行うことができるとともに、ＣＳＰ７
の多少の位置ずれは吸収することができ、これにより、
ＣＳＰ７の実装性を向上できる。Further, since the contact property of the CSP 7 can be improved, the CSP 7 when mounting the CSP 7 on a semiconductor device supporting member such as the socket 9 or the mounting substrate 8 and the connection terminals 8a and 9h of the semiconductor device supporting member are mounted. In the positioning with the CSP7, rough positioning that does not require high-precision positioning can be performed.
Slight misalignment can be absorbed,
The mountability of the CSP 7 can be improved.

【００６８】以上、本発明者によってなされた発明を発
明の実施の形態に基づき具体的に説明したが、本発明は
前記発明の実施の形態に限定されるものではなく、その
要旨を逸脱しない範囲で種々変更可能であることは言う
までもない。As described above, the invention made by the inventor has been specifically described based on the embodiments of the present invention. However, the present invention is not limited to the embodiments of the present invention, and does not depart from the gist of the invention. It is needless to say that various changes can be made.

【００６９】例えば、前記実施の形態では、ＣＳＰ７に
おいてタブ１ｅが封止部３の裏面３ａに露出しない構造
の場合を説明したが、ＣＳＰ７はタブ露出構造のもので
あってもよい。For example, in the above-described embodiment, the case where the tab 1e is not exposed on the back surface 3a of the sealing portion 3 in the CSP 7 has been described, but the CSP 7 may have a tab exposed structure.

【００７０】また、前記実施の形態では、ソケット９が
クラムシェルタイプの場合について説明したが、ソケッ
ト９は、オープントップタイプのものであってもよい。In the above embodiment, the case where the socket 9 is of the clamshell type has been described, but the socket 9 may be of the open top type.

【００７１】また、前記実施の形態では、半導体装置
（ＣＳＰ７）のリード１ａを配列方向と直角を成す方向
に対して各辺ごとに同一方向に傾斜させて配置する場合
を説明したが、図８および図９に示す他の実施の形態の
ように、半導体装置（ＣＳＰ７）のリード１ａは傾斜配
置させずに実装基板８の接続端子８ａあるいはソケット
９の接続端子９ｈを傾斜配置してもよい。In the above-described embodiment, the case where the leads 1a of the semiconductor device (CSP 7) are arranged so as to be inclined in the same direction for each side with respect to a direction perpendicular to the arrangement direction has been described. As in the other embodiment shown in FIG. 9, the leads 1a of the semiconductor device (CSP7) may not be inclined but the connection terminals 8a of the mounting board 8 or the connection terminals 9h of the socket 9 may be inclined.

【００７２】そこで、図８に示す他の実施の形態は、実
装基板８の接続端子８ａをその配列方向と直角を成す方
向に対して各辺ごとに同一方向に傾斜させて配置したも
のであり、これにより、前記実施の形態のＣＳＰ７のリ
ード１ａを傾斜配置した場合と同様に、接続端子８ａと
リード１ａとの接触関係を斜めにすることができ、その
結果、前記実施の形態と同様の作用効果を得ることがで
きる。Therefore, in another embodiment shown in FIG. 8, the connection terminals 8a of the mounting board 8 are arranged so as to be inclined in the same direction for each side with respect to a direction perpendicular to the arrangement direction. As a result, the contact relationship between the connection terminal 8a and the lead 1a can be made oblique, as in the case where the lead 1a of the CSP 7 of the embodiment is inclined. As a result, the same effect as in the embodiment described above can be obtained. The operation and effect can be obtained.

【００７３】さらに、図９に示す他の実施の形態は、ソ
ケット９の接続端子９ｈをその配列方向と直角を成す方
向に対して各辺ごとに同一方向に傾斜させて配置したも
のであり、これにより、前記図８に示す他の実施の形態
の場合と同様に、接続端子９ｈとリード１ａとの接触関
係を斜めにすることができ、その結果、前記実施の形態
と同様の作用効果を得ることができる。Further, in another embodiment shown in FIG. 9, the connection terminals 9h of the socket 9 are arranged so as to be inclined in the same direction for each side with respect to a direction perpendicular to the arrangement direction. Thus, as in the other embodiment shown in FIG. 8, the contact relationship between the connection terminal 9h and the lead 1a can be made oblique, and as a result, the same operation and effect as those of the above embodiment can be obtained. Obtainable.

【００７４】また、前記実施の形態および前記他の実施
の形態においては、半導体装置が小形のＣＳＰ７の場合
について説明したが、前記半導体装置は、封止部３の裏
面３ａに複数のリード１ａが配置されたものであれば、
ＣＳＰ７（ＱＦＮ）以外のものであってもよい。In the above-described embodiment and the other embodiments, the case where the semiconductor device is a small CSP 7 has been described. However, in the semiconductor device, a plurality of leads 1 a are provided on the back surface 3 a of the sealing portion 3. If it is placed,
It may be other than CSP7 (QFN).

【００７５】[0075]

【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

【００７６】（１）．半導体装置支持部材の複数の接続
端子および半導体装置の複数のリードのうち、何れか一
方をその配列方向と直角を成す方向に対して傾斜させて
配置して半導体装置を半導体装置支持部材に実装するこ
とにより、半導体装置支持部材の接続端子と半導体装置
のリードとを確実に接触させることができ、その結果、
半導体装置のコンタクト性の向上を図ることができる。(1). At least one of the plurality of connection terminals of the semiconductor device support member and the plurality of leads of the semiconductor device is arranged to be inclined with respect to a direction perpendicular to the arrangement direction, and the semiconductor device is mounted on the semiconductor device support member. Thereby, the connection terminal of the semiconductor device support member and the lead of the semiconductor device can be reliably brought into contact, and as a result,
The contact property of the semiconductor device can be improved.

【００７７】（２）．前記（１）により、コンタクト不
良による再検査などの付帯作業を低減できる。さらに、
再検査を低減できるため、検査用テスタを有効活用する
ことができ、その結果、検査のスループットを向上でき
る。(2). According to the above (1), it is possible to reduce incidental work such as re-inspection due to contact failure. further,
Since re-inspection can be reduced, an inspection tester can be effectively used, and as a result, inspection throughput can be improved.

【００７８】（３）．半導体装置のコンタクト性の向上
を図ることができるため、半導体装置の歩留りを向上さ
せることができる。(3). Since the contact property of the semiconductor device can be improved, the yield of the semiconductor device can be improved.

【００７９】（４）．半導体装置のコンタクト性の向上
を図ることができるため、半導体装置をソケットや実装
基板などの半導体装置支持部材に実装する際の半導体装
置と半導体装置支持部材の接続端子との位置合わせをラ
フにすることができ、かつ半導体装置の多少の位置ずれ
は吸収することができるため、その結果、半導体装置の
実装性を向上できる。(4). Since the contact property of the semiconductor device can be improved, when the semiconductor device is mounted on a semiconductor device support member such as a socket or a mounting board, the alignment between the semiconductor device and the connection terminal of the semiconductor device support member is roughened. And a slight displacement of the semiconductor device can be absorbed. As a result, the mountability of the semiconductor device can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】（ａ),（ｂ),（ｃ）は本発明の実施の形態の半
導体装置の製造方法によって組み立てられる半導体装置
の構造の一例を示す図であり、（ａ）は平面図、（ｂ）
は側面図、（ｃ）は底面図である。FIGS. 1A, 1B, and 1C are diagrams showing an example of a structure of a semiconductor device assembled by a method of manufacturing a semiconductor device according to an embodiment of the present invention; FIG. (B)
Is a side view, and (c) is a bottom view.

【図２】図１に示す半導体装置の構造を示す断面図であ
る。FIG. 2 is a cross-sectional view showing a structure of the semiconductor device shown in FIG.

【図３】図１に示す半導体装置の製造方法の実施の形態
の一例を示す製造プロセスフロー図である。FIG. 3 is a manufacturing process flow chart showing one example of an embodiment of a method of manufacturing the semiconductor device shown in FIG. 1;

【図４】図１に示す半導体装置の製造方法で用いられる
リードフレームの構造の一例を示す部分平面図である。FIG. 4 is a partial plan view showing an example of the structure of a lead frame used in the method of manufacturing the semiconductor device shown in FIG.

【図５】図１に示す半導体装置の実装基板への実装状態
の一例を示す部分平面図である。FIG. 5 is a partial plan view showing an example of a mounting state of the semiconductor device shown in FIG. 1 on a mounting board.

【図６】図１に示す半導体装置のソケットへの実装状態
の一例を示す部分断面図である。6 is a partial cross-sectional view showing an example of a state in which the semiconductor device shown in FIG. 1 is mounted on a socket.

【図７】（ａ),（ｂ) は図１に示す半導体装置のソケッ
トへの実装時のパッケージ側のリードと基板側の接続端
子との接触状態の一例を示す図であり、（ａ）は平面
図、（ｂ）は部分断面図である。FIGS. 7A and 7B are diagrams showing an example of a contact state between a package-side lead and a board-side connection terminal when the semiconductor device shown in FIG. 1 is mounted on a socket; Is a plan view, and (b) is a partial sectional view.

【図８】本発明の他の実施の形態の半導体装置の製造方
法による実装基板への実装状態を示す部分平面図であ
る。FIG. 8 is a partial plan view showing a state of being mounted on a mounting board by a method of manufacturing a semiconductor device according to another embodiment of the present invention.

【図９】本発明の他の実施の形態の半導体装置の製造方
法によるソケットへの実装状態を示す平面図である。FIG. 9 is a plan view showing a state of being mounted on a socket by a method of manufacturing a semiconductor device according to another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ リードフレーム １ａ リード １ｂ 端子接続面 １ｃ ボンディング面 １ｄ タブ吊りリード １ｅ タブ（チップ支持部） １ｆ 枠部 １ｇ ガイド用長孔 １ｈ 位置決め孔 ２ 半導体チップ ２ａ パッド（表面電極） ２ｂ 主面 ２ｃ 裏面 ３ 封止部 ３ａ 裏面（半導体装置実装側の面） ４ ボンディングワイヤ ５ ダイボンド材 ６ 半田めっき層 ７ ＣＳＰ（半導体装置） ８ 実装基板（半導体装置支持部材） ８ａ 接続端子 ９ ソケット（半導体装置支持部材） ９ａ ソケット本体 ９ｂ 蓋部材 ９ｃ バネ部材 ９ｄ 押圧子 ９ｅ フック部材 ９ｆ ピン部材 ９ｇ 回路基板 ９ｈ 接続端子 ９ｉ ベース部材 １０ テストボード DESCRIPTION OF SYMBOLS 1 Lead frame 1a Lead 1b Terminal connection surface 1c Bonding surface 1d Tab suspension lead 1e Tab (chip support part) 1f Frame part 1g Guide long hole 1h Positioning hole 2 Semiconductor chip 2a Pad (surface electrode) 2b Main surface 2c Back surface 3 Sealing Stop portion 3a Back surface (surface on the semiconductor device mounting side) 4 Bonding wire 5 Die bond material 6 Solder plating layer 7 CSP (semiconductor device) 8 Mounting substrate (semiconductor device support member) 8a Connection terminal 9 Socket (semiconductor device support member) 9a socket Main body 9b Lid member 9c Spring member 9d Presser 9e Hook member 9f Pin member 9g Circuit board 9h Connection terminal 9i Base member 10 Test board

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 表面実装形の半導体装置の製造方法であ
って、 半導体チップを支持可能なチップ支持部と、これの周囲
に配置された複数のリードとを有するリードフレームを
準備する工程と、 前記リードフレームの前記チップ支持部と前記半導体チ
ップとを接合する工程と、 前記半導体チップの表面電極とこれに対応する前記リー
ドとを接続する工程と、 前記半導体チップを封止して、前記リードの端子接続面
を前記半導体装置実装側の面に露出させて封止部を形成
する工程と、 複数の前記リードを前記リードフレームの枠部から分離
する工程と、 前記半導体装置を支持可能な半導体装置支持部材の複数
の接続端子および前記半導体装置の複数の前記リードの
うち、何れか一方を配列方向と直角を成す方向に対して
傾斜させて配置して前記接続端子と前記リードとを接触
させて前記半導体装置を前記半導体装置支持部材に実装
する工程とを有することを特徴とする半導体装置の製造
方法。1. A method for manufacturing a surface-mounted semiconductor device, comprising: preparing a lead frame having a chip support portion capable of supporting a semiconductor chip and a plurality of leads arranged around the chip support portion; Joining the chip support portion of the lead frame and the semiconductor chip; connecting a surface electrode of the semiconductor chip and the corresponding lead; sealing the semiconductor chip and providing the lead Forming a sealing portion by exposing a terminal connection surface of the semiconductor device to the surface on the semiconductor device mounting side; separating a plurality of leads from a frame portion of the lead frame; and a semiconductor capable of supporting the semiconductor device. Any one of the plurality of connection terminals of the device support member and the plurality of leads of the semiconductor device is disposed so as to be inclined with respect to a direction perpendicular to the arrangement direction. Mounting the semiconductor device on the semiconductor device supporting member by bringing a connection terminal into contact with the lead.
JP2000035295A 2000-02-14 2000-02-14 Method of manufacturing semiconductor device Pending JP2001230363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000035295A JP2001230363A (en) 2000-02-14 2000-02-14 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000035295A JP2001230363A (en) 2000-02-14 2000-02-14 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JP2001230363A true JP2001230363A (en) 2001-08-24

Family

ID=18559517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000035295A Pending JP2001230363A (en) 2000-02-14 2000-02-14 Method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2001230363A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180078965A (en) * 2016-12-30 2018-07-10 스템코 주식회사 Flexible printed circuit boards and method of manufacturing electronic product including the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180078965A (en) * 2016-12-30 2018-07-10 스템코 주식회사 Flexible printed circuit boards and method of manufacturing electronic product including the same
KR102009827B1 (en) 2016-12-30 2019-08-12 스템코 주식회사 Flexible printed circuit boards and method of manufacturing electronic product including the same

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