JP2001189422A - Method of manufacturing thin-film capacitor - Google Patents

Method of manufacturing thin-film capacitor

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Publication number
JP2001189422A
JP2001189422A JP37105599A JP37105599A JP2001189422A JP 2001189422 A JP2001189422 A JP 2001189422A JP 37105599 A JP37105599 A JP 37105599A JP 37105599 A JP37105599 A JP 37105599A JP 2001189422 A JP2001189422 A JP 2001189422A
Authority
JP
Japan
Prior art keywords
thin film
dielectric
film capacitor
dielectric thin
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP37105599A
Other languages
Japanese (ja)
Inventor
Hajime Yamada
一 山田
Shinji Tanaka
伸治 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP37105599A priority Critical patent/JP2001189422A/en
Publication of JP2001189422A publication Critical patent/JP2001189422A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a thin-film capacitor which is suitably used, even for a small integrated circuit, superior in crystallininty, restrained from deteriorating in resistance, and stable in characteristics. SOLUTION: A dielectric thin film, that forms a thin film capacitor is formed of oxide dielectric which is represented by a general formula, ABO3 as the chemical formula, the oxide dielectric is manufactured through an ECR sputtering method, and the dielectric thin film has a composition that satisfies the expression 0.82<=A/B<=0.97.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、集積回路等に用い
られる薄膜キャパシタの製造方法に関する。より具体的
には、基板上に下部電極、誘電体薄膜、上部電極が順次
積層して形成された、いわゆるMIM構造の誘電体薄膜
キャパシタの製造方法に関する。
The present invention relates to a method for manufacturing a thin film capacitor used for an integrated circuit or the like. More specifically, the present invention relates to a method of manufacturing a dielectric thin film capacitor having a so-called MIM structure in which a lower electrode, a dielectric thin film, and an upper electrode are sequentially laminated on a substrate.

【0002】[0002]

【従来の技術】近年、集積回路技術の飛躍的な発達にと
もなって電子回路が急速に小型化しており、それととも
に電子回路を構成する薄膜キャパシタの一層の小型化が
求められている。
2. Description of the Related Art In recent years, electronic circuits have been rapidly miniaturized with the rapid development of integrated circuit technology, and further miniaturization of thin film capacitors constituting electronic circuits has been demanded.

【0003】ここで、従来より用いられている薄膜キャ
パシタの断面図を図4に示す。図4において、薄膜キャ
パシタ51は、半導体基板52、Ptよりなる下部電極
53、誘電体薄膜54、同じくPtよりなる上部電極5
5から構成されている。
FIG. 4 is a sectional view of a conventionally used thin film capacitor. In FIG. 4, a thin film capacitor 51 includes a semiconductor substrate 52, a lower electrode 53 made of Pt, a dielectric thin film 54, and an upper electrode 5 made of Pt.
5 is comprised.

【0004】ここで、誘電体薄膜54にはSiO2、S
iNxなどの誘電体材料が用いられる。これらの材料は
誘電率は4〜7と比較的小さいものの、絶縁性が高く特
性の安定した薄膜キャパシタを実現できることから、従
来より薄膜キャパシタ用の誘電体材料としてしばしば用
いられている。
Here, the dielectric thin film 54 is made of SiO 2 , S
A dielectric material such as iN x is used. Although these materials have a relatively small dielectric constant of 4 to 7, they have been often used as dielectric materials for thin film capacitors since they can realize a thin film capacitor having high insulation properties and stable characteristics.

【0005】ところで、一般に薄膜キャパシタの容量値
Cは、C=ε0・εr・S/t、なる式にて表される
(ε0は用いる誘電体材料の真空中での誘電率、εrは
比誘電率、Sは電極面積、tは誘電体薄膜の膜厚をそれ
ぞれ示す)。従って、集積回路の小型化により電極面積
Sが小さくなった場合、SiO2、SiNx等の従来の誘
電体材料を用いると、必然的に薄膜キャパシタ51の容
量は小さくなってしまう。電極面積Sを小さくしつつ、
従来と同程度の容量の薄膜キャパシタを実現しようとす
る場合、誘電体薄膜53の膜厚tを薄くするか、あるい
は比誘電率εrの高い誘電体材料を用いるか、のいずれ
かの手法が用いる必要がある。
In general, the capacitance value C of a thin film capacitor is expressed by the following equation: C = ε 0 · εr · S / t (ε 0 is the dielectric constant of a dielectric material used in vacuum, and εr is The relative dielectric constant, S indicates the electrode area, and t indicates the thickness of the dielectric thin film). Therefore, when the electrode area S is reduced due to the miniaturization of the integrated circuit, the capacitance of the thin film capacitor 51 is necessarily reduced when a conventional dielectric material such as SiO 2 or SiN x is used. While reducing the electrode area S,
In order to realize a thin film capacitor having the same capacity as the conventional one, either a method of reducing the thickness t of the dielectric thin film 53 or using a dielectric material having a high relative permittivity εr is used. There is a need.

【0006】誘電体薄膜53の膜厚tを薄くする手法は
比較的容易に行いうるが、絶縁性確保の観点から膜厚t
の薄膜化には自ずと限界があり、さらなる高容量の薄膜
キャパシタの実現には比誘電率の大きな誘電体材料の開
発が不可欠である。この要求に応える誘電体材料とし
て、近年、一般式ABO3で表されるペロブスカイト型
の結晶構造を有するSrTiO3、BiTiO3、(B
a、Sr)TiO3などの、チタンを含む酸化物誘電体
が注目されている。これらの酸化物誘電体は、数百程度
の高い比誘電率を有しており、小型高容量の薄膜キャパ
シタに好適に用いうる。
[0006] The method of reducing the thickness t of the dielectric thin film 53 can be relatively easily performed.
There is naturally a limit to the thinning of GaN, and the development of a dielectric material having a large relative dielectric constant is indispensable for the realization of a thinner capacitor with a higher capacity. In recent years, as a dielectric material meeting this demand, SrTiO 3 , BiTiO 3 , (B) having a perovskite-type crystal structure represented by the general formula ABO 3
Attention has been focused on oxide dielectrics containing titanium, such as a, Sr) TiO 3 . These oxide dielectrics have a high relative dielectric constant of about several hundreds and can be suitably used for small-sized and high-capacity thin-film capacitors.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、上述の
一般式ABO3で表されるペロブスカイト型誘電体材料
を用いて誘電体薄膜を作製した場合、特性の安定した薄
膜キャパシタを実現することが困難であった。具体的に
は、これらの誘電体材料を用いた薄膜キャパシタでは、
高温環境下で一定の電圧を印加し続けると、ある時点か
ら絶縁抵抗が急激に劣化してしまう、と言う現象が見ら
れ実用に供することが困難であった。この現象は、一般
に「抵抗劣化」と呼ばれており、その詳細なメカニズム
は不明であるが、ペロブスカイト型酸化物薄膜内に存在
する酸素欠陥が電界に沿って移動する現象として理解さ
れている。バルクの誘電体に対しては、ある種の希土類
元素を誘電体材料中に添加することで抵抗劣化の抑制が
可能であることが知られており、薄膜形成した誘電体に
対しても希土類元素の添加が抵抗劣化に対して有効であ
ることが確認されている。しかしながら、希土類元素の
添加量の微妙な制御が非常に困難であるため、この手法
による抵抗劣化の抑制方法は未だ確立されていないのが
現状である。
However, when a dielectric thin film is manufactured using the perovskite type dielectric material represented by the above-mentioned general formula ABO 3 , it is difficult to realize a thin film capacitor having stable characteristics. there were. Specifically, in thin film capacitors using these dielectric materials,
When a constant voltage is continuously applied in a high-temperature environment, a phenomenon that the insulation resistance is rapidly deteriorated from a certain point is observed, and it has been difficult to put to practical use. This phenomenon is generally called “resistance deterioration”, and its detailed mechanism is unknown, but is understood as a phenomenon in which oxygen defects existing in the perovskite oxide thin film move along the electric field. It is known that the addition of a certain rare earth element to a dielectric material can suppress the resistance degradation of bulk dielectrics. Has been confirmed to be effective for resistance degradation. However, since it is very difficult to finely control the amount of the rare earth element to be added, a method for suppressing the resistance deterioration by this method has not yet been established.

【0008】従って本発明の目的は、上述の技術的問題
点を解決するためになされたものであって、小型の集積
回路にも好適に使用することができ、結晶性が良好で抵
抗劣化の抑制された、安定した特性を有する薄膜キャパ
シタの製造方法を提供することにある。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned technical problems, and can be suitably used for a small-sized integrated circuit. An object of the present invention is to provide a method for manufacturing a thin film capacitor having suppressed and stable characteristics.

【0009】[0009]

【課題を解決するための手段】上述の技術的課題を解決
するために本発明の薄膜キャパシタの製造方法において
は、薄膜キャパシタを構成する誘電体薄膜を、一般式A
BO3の化学式で表される酸化物誘電体で構成し、かつ
この酸化物誘電体をECRスパッタリング法を用いて作
製することを特徴とする。かつ、この誘電体薄膜は、
0.82≦A/B≦0.97を満たす膜組成を有してい
ることを特徴とする。
In order to solve the above-mentioned technical problems, in a method of manufacturing a thin film capacitor according to the present invention, a dielectric thin film constituting a thin film capacitor is represented by a general formula A
It is characterized by comprising an oxide dielectric represented by the chemical formula of BO 3 , and manufacturing this oxide dielectric by using an ECR sputtering method. And this dielectric thin film is
It has a film composition satisfying 0.82 ≦ A / B ≦ 0.97.

【0010】後述の実施例中にて詳細に説明するが、E
CRスパッタリング法を用いて誘電体薄膜を作製するこ
とにより誘電体薄膜の結晶性を高めることができ、特に
一般式ABO3における膜組成を0.82≦A/B≦
0.97の範囲に設定した場合に、実用に供することが
できる程度に安定した特性を有する薄膜キャパシタを作
製しうることを見出し本発明を完成させるに到った。
As will be described in detail in the embodiments described later,
The crystallinity of the dielectric thin film can be improved by producing the dielectric thin film by using the CR sputtering method. In particular, the film composition in the general formula ABO 3 is set to 0.82 ≦ A / B ≦
It has been found that a thin film capacitor having characteristics stable enough to be practically used can be manufactured when the thickness is set in the range of 0.97, and the present invention has been completed.

【0011】また、上記一般式ABO3中で表される誘
電体薄膜において、式中AにはBa、Sr、Ca、Pb
からなる群より選ばれた少なくとも一種の元素を用いる
ことが好ましく、式中BにはTi、Zr、Hf、Snか
らなる群より選ばれた少なくとも一種の元素を用いるこ
とが好ましい。
In the dielectric thin film represented by the general formula ABO 3 , A represents Ba, Sr, Ca, Pb
Preferably, at least one element selected from the group consisting of Ti, Zr, Hf, and Sn is used for B in the formula.

【0012】[0012]

【発明の実施の形態】[第1実施例、図1〜図2]以
下、本発明の薄膜キャパシタの製造方法を図を参照して
詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment, FIGS. 1 and 2] Hereinafter, a method for manufacturing a thin film capacitor according to the present invention will be described in detail with reference to the drawings.

【0013】まず、本発明の製造方法によって得られる
薄膜キャパシタの断面図を図1に示す。図1において、
薄膜キャパシタ1は、シリコン半導体基板2、Pt等よ
りなる下部電極3、誘電体薄膜4、同じくPt等よりな
る上部電極5から構成されている。
First, a sectional view of a thin film capacitor obtained by the manufacturing method of the present invention is shown in FIG. In FIG.
The thin film capacitor 1 includes a silicon semiconductor substrate 2, a lower electrode 3 made of Pt or the like, a dielectric thin film 4, and an upper electrode 5 made of Pt or the like.

【0014】より詳細には、下部電極3は、基板側から
順にTi、Pt、Auの順に積層されて形成されてい
る。また、上部電極5は、誘電体薄膜4側から順にP
t、Auの順に積層されて形成されている。誘電体薄膜
4は、RFターゲットとDCターゲットの二種のターゲ
ットを載置できる二元ターゲット型のECRスパッタリ
ング装置を用いて作製を行った。作製にあたっては、R
Fターゲットとして化学量論比通りの組成を有するSr
TiO3ターゲットを用い、他方DCターゲットとして
Tiターゲットを用いた。このとき、Tiターゲットに
印加する電力を調整することで、膜組成をSr/Ti=
0.70〜1.12の範囲内で種々に変化させ複数の試
料(薄膜キャパシタ)を作成した。誘電体薄膜4の膜厚
はいずれも200nmとし、Ar:0.05Pa、
2:0.05Paの真空雰囲気中でスパッタリングに
より成膜を行った。
More specifically, the lower electrode 3 is formed by laminating Ti, Pt, and Au in this order from the substrate side. In addition, the upper electrode 5 is composed of P in order from the dielectric thin film 4 side.
The layers are laminated in the order of t and Au. The dielectric thin film 4 was manufactured using a binary target type ECR sputtering apparatus on which two kinds of targets, an RF target and a DC target, could be placed. In making, R
Sr having composition as stoichiometric as F target
A TiO 3 target was used, while a Ti target was used as a DC target. At this time, by adjusting the power applied to the Ti target, the film composition is changed to Sr / Ti =
A plurality of samples (thin film capacitors) were prepared with various changes in the range of 0.70 to 1.12. The thickness of each of the dielectric thin films 4 is 200 nm, Ar: 0.05 Pa,
O 2 : A film was formed by sputtering in a vacuum atmosphere of 0.05 Pa.

【0015】このようにして得られた複数の試料に対し
て、200℃・0.4MV/cmの環境下で信頼性試験
を行い、薄膜キャパシタ1の劣化時間を測定した。ここ
で、劣化時間の膜組成依存性を図2にまとめる。この結
果から、膜組成0.82≦Sr/Ti≦0.97の範囲
で劣化時間を5×10-1時間以上に持続できることがわ
かる。ところで、信頼性試験における高温高圧環境下で
の上述の劣化時間は、通常の環境下でのSrTiO3
対する劣化の活性化エネルギーが0.7〜1.0eV程
度であることから、室温においては抵抗劣化の抑制時間
は20000時間以上に換算され、十分に高い信頼性を
確保しうることがわかる。
A plurality of the samples thus obtained were subjected to a reliability test under an environment of 200 ° C. and 0.4 MV / cm, and the deterioration time of the thin film capacitor 1 was measured. Here, the dependency of the deterioration time on the film composition is summarized in FIG. From this result, it can be seen that the deterioration time can be maintained at 5 × 10 −1 hours or more in the range of the film composition 0.82 ≦ Sr / Ti ≦ 0.97. Incidentally, the above-mentioned deterioration time in a high-temperature and high-pressure environment in the reliability test is as follows. Since the activation energy of deterioration with respect to SrTiO 3 in a normal environment is about 0.7 to 1.0 eV, the The deterioration suppression time is converted to 20,000 hours or more, which indicates that sufficiently high reliability can be ensured.

【0016】本発明の薄膜キャパシタの製造方法によっ
て、抵抗劣化に対して高い信頼性を有する薄膜キャパシ
タが得られるメカニズムは、おそらく以下の理由による
ものと考えられる。まず、膜組成0.82≦Sr/Ti
≦0.97の範囲では、Aサイトに−2の有効電荷を有
するSr欠陥が多数存在している。他方、誘電体薄膜中
には+2の有効電荷を有する酸素欠陥が同じく多数存在
しており、このSr欠陥と酸素欠陥とが静電力によって
接近し、欠陥クラスタとして会合することになる。ペロ
ブスカイト構造中では、酸素欠陥は高い移動性を有する
が、Sr欠陥の移動性は低い。このため、Sr欠陥と酸
素欠陥とが会合することにより、電界中の酸素欠陥の移
動性が低く抑えられているものと考えられる。
The mechanism by which the method for manufacturing a thin film capacitor of the present invention can provide a thin film capacitor having high reliability against resistance deterioration is probably due to the following reasons. First, the film composition 0.82 ≦ Sr / Ti
In the range of ≦ 0.97, there are many Sr defects having an effective charge of −2 at the A site. On the other hand, a large number of oxygen vacancies having an effective charge of +2 also exist in the dielectric thin film, and the Sr vacancies and the oxygen vacancies approach each other by electrostatic force and associate as defect clusters. In the perovskite structure, oxygen vacancies have high mobility, but Sr vacancies have low mobility. Therefore, it is considered that the mobility of the oxygen defect in the electric field is suppressed to a low level by the association of the Sr defect and the oxygen defect.

【0017】また、平行平板型のRFスパッタリング装
置を用いて、同様の膜組成となるように薄膜キャパシタ
を作製し、該薄膜キャパシタの抵抗劣化時間を計った。
この結果、RFスパッタリング法を用いて作製した薄膜
キャパシタでは、膜組成が同一であってもECRスパッ
タ法を用いて作製したものに比べて劣化時間は1/20
以下と速かった。RFスパッタリング法で作製した誘電
体薄膜をX線回折およびTEMにて測定したところ、転
位が多く結晶性に劣ることが確認された。RFスパッタ
リング法では、反跳Ar粒子や負イオンとなった酸素イ
オン等が成膜中の誘電体薄膜にダメージを与えることが
原因で結晶性が劣化するものと考えられる。この結晶性
の良否も誘電体薄膜中の酸素欠陥の量や移動性に影響を
与えており、誘電体薄膜の結晶性を高めることの可能な
ECRスパッタリング法を用いて成膜することも本発明
において重要な意味を有する。
Using a parallel plate type RF sputtering apparatus, a thin film capacitor was manufactured to have the same film composition, and the resistance deterioration time of the thin film capacitor was measured.
As a result, the deterioration time of the thin film capacitor manufactured by using the RF sputtering method is 1/20 as compared with that manufactured by using the ECR sputtering method even if the film composition is the same.
It was quick with the following. When the dielectric thin film produced by the RF sputtering method was measured by X-ray diffraction and TEM, it was confirmed that there were many dislocations and the crystallinity was poor. In the RF sputtering method, it is considered that crystallinity is degraded due to damage to the dielectric thin film during film formation by recoiled Ar particles or oxygen ions that have become negative ions. The quality of the crystallinity also affects the amount and mobility of oxygen defects in the dielectric thin film, and the film formation using the ECR sputtering method capable of increasing the crystallinity of the dielectric thin film is also possible in the present invention. Has an important meaning.

【0018】なお、本実施例においては下部電極、上部
電極はTi、Pt、Au等の金属を用いて作製したが、
これに限られることなく、既知の種々の配線材料を用い
て構わない。半導体基板に注入を行って形成した注入配
線を下部電極として用いても構わない。また、電極は蒸
着、スパッタリング等、任意の手法で形成すればよい。
また、本実施例ではシリコン半導体基板を用いたが、こ
れに限られることなく、誘電体基板、ガラス基板等、既
知の種々の基板を用いることができる。 [第2実施例、図3]本発明の第2実施例の薄膜キャパ
シタの製造方法を図を用いて詳細に説明する。
In this embodiment, the lower electrode and the upper electrode are made of a metal such as Ti, Pt, or Au.
Without being limited to this, various known wiring materials may be used. An injection wiring formed by injection into a semiconductor substrate may be used as a lower electrode. Further, the electrodes may be formed by any method such as vapor deposition and sputtering.
In this embodiment, a silicon semiconductor substrate is used. However, the present invention is not limited to this, and various known substrates such as a dielectric substrate and a glass substrate can be used. Second Embodiment, FIG. 3 A method of manufacturing a thin film capacitor according to a second embodiment of the present invention will be described in detail with reference to the drawings.

【0019】本実施例の薄膜キャパシタの製造方法にお
いては、図3に示すように、下部電極2のエッジ部分へ
の電界集中による絶縁破壊を防止するための絶縁層6を
形成する工程を有することを特徴とする。これにより、
より耐圧性に優れた薄膜キャパシタ11が得られる。そ
の他の部分は、第1実施例の薄膜キャパシタの製造方法
と異なる点がないので、その説明を省略する。
In the method of manufacturing a thin film capacitor according to the present embodiment, as shown in FIG. 3, a step of forming an insulating layer 6 for preventing dielectric breakdown due to electric field concentration on an edge portion of the lower electrode 2 is required. It is characterized by. This allows
The thin-film capacitor 11 having more excellent withstand voltage can be obtained. The other parts are not different from the method of manufacturing the thin film capacitor according to the first embodiment, and therefore the description thereof is omitted.

【0020】[0020]

【発明の効果】上述の説明から明らかなように、本発明
の薄膜キャパシタの製造方法によれば、例えばペロブス
カイト型誘電体のような一般式ABO3で表される酸化
物の膜組成を0.82≦Sr/Ti≦0.97の範囲と
することにより、Sr欠陥と酸素欠陥との会合の割合が
最適化され、抵抗劣化を抑制し信頼性の高い薄膜キャパ
シタを提供することが可能になる。
As is apparent from the above description, according to the method for manufacturing a thin film capacitor of the present invention, the film composition of the oxide represented by the general formula ABO 3 such as a perovskite dielectric is reduced to 0.1%. By setting the range of 82 ≦ Sr / Ti ≦ 0.97, the ratio of association between Sr defects and oxygen defects is optimized, and it is possible to provide a thin film capacitor that suppresses resistance deterioration and has high reliability. .

【0021】また、成膜中の誘電体薄膜へのダメージの
少ないECRスパッタリング法で誘電体薄膜を作製する
ことにより、誘電体薄膜の結晶性を高めることができ、
よって酸素欠陥の量が少なくかつ移動性の低い誘電体薄
膜を形成できる。
Further, by forming the dielectric thin film by the ECR sputtering method which causes less damage to the dielectric thin film during film formation, the crystallinity of the dielectric thin film can be improved,
Therefore, a dielectric thin film having a small amount of oxygen defects and low mobility can be formed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の第1実施例の製造方法で作製された
薄膜キャパシタの断面図である。
FIG. 1 is a sectional view of a thin film capacitor manufactured by a manufacturing method according to a first embodiment of the present invention.

【図2】 第1実施例の製造方法で得られた薄膜キャパ
シタの、抵抗劣化と膜組成依存性の関係を示す図であ
る。
FIG. 2 is a diagram showing the relationship between resistance degradation and film composition dependence of a thin film capacitor obtained by the manufacturing method of the first embodiment.

【図3】 本発明の第2実施例の製造方法で作成された
薄膜キャパシタの断面図である。
FIG. 3 is a cross-sectional view of a thin-film capacitor manufactured by a manufacturing method according to a second embodiment of the present invention.

【図4】 従来例の薄膜キャパシタの構造を示す断面図
である。
FIG. 4 is a cross-sectional view showing the structure of a conventional thin film capacitor.

【符号の説明】[Explanation of symbols]

1 ・・・ 薄膜キャパシタ 2 ・・・ 半導体基板 3 ・・・ 下部電極 4 ・・・ 誘電体薄膜 5 ・・・ 上部電極 DESCRIPTION OF SYMBOLS 1 ... Thin film capacitor 2 ... Semiconductor substrate 3 ... Lower electrode 4 ... Dielectric thin film 5 ... Upper electrode

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 27/108 21/8242 Fターム(参考) 4K029 BA50 BB07 BC00 BD01 DC48 5F038 AC05 AC14 EZ11 EZ20 5F058 BA11 BA20 BC03 BC04 BF14 BJ01 5F083 FR01 JA13 PR22 5F103 AA08 DD30 HH03 LL20 NN04 NN05 RR04 RR05 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 27/108 21/8242 F-term (Reference) 4K029 BA50 BB07 BC00 BD01 DC48 5F038 AC05 AC14 EZ11 EZ20 5F058 BA11 BA20 BC03 BC04 BF14 BJ01 5F083 FR01 JA13 PR22 5F103 AA08 DD30 HH03 LL20 NN04 NN05 RR04 RR05

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板上に下部電極、誘電体薄膜、上部電
極を順次積層形成してなる薄膜キャパシタの製造方法で
あって、 前記誘電体薄膜はECRスパッタリング法を用いて作製
された一般式ABO3の化学式で表される酸化物であ
り、かつ前記誘電体薄膜は0.82≦A/B≦0.97
を満たす組成を有していることを特徴とする薄膜キャパ
シタの製造方法。
1. A method of manufacturing a thin film capacitor in which a lower electrode, a dielectric thin film, and an upper electrode are sequentially formed on a substrate, wherein the dielectric thin film is formed by a general formula ABO manufactured by using an ECR sputtering method. an oxide represented by a third formula, and the dielectric thin film is 0.82 ≦ a / B ≦ 0.97
A method for producing a thin film capacitor, having a composition satisfying the following.
【請求項2】 前記一般式ABO3中で表される誘電体
薄膜の、式中AはBa、Sr、Ca、Pbからなる群よ
り選ばれた少なくとも一種の元素を含み、かつ式中Bは
Ti、Zr、Hf、Snからなる群より選ばれた少なく
とも一種の元素を含むことを特徴とする請求項1に記載
の薄膜キャパシタの製造方法。
2. In the dielectric thin film represented by the general formula ABO 3 , A in the formula includes at least one element selected from the group consisting of Ba, Sr, Ca, and Pb, and B in the formula is 2. The method according to claim 1, wherein the method includes at least one element selected from the group consisting of Ti, Zr, Hf, and Sn.
JP37105599A 1999-12-27 1999-12-27 Method of manufacturing thin-film capacitor Pending JP2001189422A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP37105599A JP2001189422A (en) 1999-12-27 1999-12-27 Method of manufacturing thin-film capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP37105599A JP2001189422A (en) 1999-12-27 1999-12-27 Method of manufacturing thin-film capacitor

Publications (1)

Publication Number Publication Date
JP2001189422A true JP2001189422A (en) 2001-07-10

Family

ID=18498064

Family Applications (1)

Application Number Title Priority Date Filing Date
JP37105599A Pending JP2001189422A (en) 1999-12-27 1999-12-27 Method of manufacturing thin-film capacitor

Country Status (1)

Country Link
JP (1) JP2001189422A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005251843A (en) * 2004-03-02 2005-09-15 Nec Electronics Corp Semiconductor device, its manufacturing method, and storage device
US7518199B2 (en) 2005-01-26 2009-04-14 Kabushiki Kaisha Toshiba Insulating film containing an additive element and semiconductor device
JP2011124539A (en) * 2009-11-13 2011-06-23 Sony Corp Printed-circuit board and manufacturing method thereof
CN102544118A (en) * 2010-12-20 2012-07-04 中芯国际集成电路制造(上海)有限公司 Metal-insulator-metal (MIM) capacitor and preparation method thereof
US8315038B2 (en) 2009-04-15 2012-11-20 Tdk Corporation Thin-film capacitor and electronic circuit board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005251843A (en) * 2004-03-02 2005-09-15 Nec Electronics Corp Semiconductor device, its manufacturing method, and storage device
US7518199B2 (en) 2005-01-26 2009-04-14 Kabushiki Kaisha Toshiba Insulating film containing an additive element and semiconductor device
US8315038B2 (en) 2009-04-15 2012-11-20 Tdk Corporation Thin-film capacitor and electronic circuit board
JP2011124539A (en) * 2009-11-13 2011-06-23 Sony Corp Printed-circuit board and manufacturing method thereof
CN102544118A (en) * 2010-12-20 2012-07-04 中芯国际集成电路制造(上海)有限公司 Metal-insulator-metal (MIM) capacitor and preparation method thereof

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