JP2001185449A - Laminated ceramic capacitor - Google Patents
Laminated ceramic capacitorInfo
- Publication number
- JP2001185449A JP2001185449A JP37069999A JP37069999A JP2001185449A JP 2001185449 A JP2001185449 A JP 2001185449A JP 37069999 A JP37069999 A JP 37069999A JP 37069999 A JP37069999 A JP 37069999A JP 2001185449 A JP2001185449 A JP 2001185449A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- multilayer
- external electrode
- capacity
- laminated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子機器の受動部
品として用いられる積層セラミックコンデンサに関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic capacitor used as a passive component of electronic equipment.
【０００２】[0002]
【従来の技術】携帯電話機やノートパソコン等の電子機
器から発生する放射雑音を低減する方法として、また、
回路基板上のＬＳＩの動作に必要な電流を供給するコン
デンサとして、更に、電流供給ライン経路の増加に伴う
カップリングで発生する雑音を抑制するためにカップリ
ングを緩衝するコンデンサとして、デカップリング・コ
ンデンサが用いられている。2. Description of the Related Art As a method for reducing radiated noise generated from electronic devices such as mobile phones and notebook personal computers,
A decoupling capacitor as a capacitor for supplying current necessary for the operation of the LSI on the circuit board, and as a capacitor for buffering the coupling in order to suppress noise generated by coupling due to an increase in current supply line paths. Is used.
【０００３】デッカプリング・コンデンサの入れ方とし
て、消費電流や駆動電流がほとんど変化しないＴＴＬ
ＩＣの場合、ＴＴＬ ＩＣ１個当たり２．２μＦを２〜
３個入れていた。また、回路構成としては、電荷供給の
コンデンサとして大容量で高周波帯域で等価直列抵抗
（ＥＳＲ）の大きいタンタルコンデンサと、低容量で高
周波特性の良い積層セラミックコンデンサの組み合わせ
が一般的である。As a method of inserting a decoupling capacitor, a TTL in which current consumption and drive current hardly change is considered.
In the case of IC, 2.2 μF per TTL IC
I had three in it. As a circuit configuration, a combination of a tantalum capacitor having a large capacity and a large equivalent series resistance (ESR) in a high frequency band as a charge supply capacitor and a multilayer ceramic capacitor having a low capacity and a good high frequency characteristic is generally used.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、動作周
波数が高いＬＳＩの場合、ＬＳＩから離れた位置に実装
されたり、静電容量が少ないと、遠くのデカップリング
・コンデンサから電荷供給されるため、電流ラインが長
くなりデカップリング効果が得られなくなる。また、隣
接したコンデンサの距離と、そのラインを流れる高周波
電流の波長が一致し、共振現象を引き起こし放射雑音が
大きくなる。更に、ＥＳＲが小さく周波数特性の良い積
層セラミックコンデンサで、大きな静電容量のチップと
小さな静電容量のチップを単純に並列に電源ラインに挿
入すると、周波数に対して急峻なインピーダンス特性が
影響して、位相が１８０°反転した際に発振するために
リンギングという現象が起こるため、大きな静電容量の
チップに直列に抵抗を挿入しなければならなくなるとい
う問題点があった。However, in the case of an LSI having a high operating frequency, if the LSI is mounted at a position distant from the LSI or if the capacitance is small, electric charge is supplied from a distant decoupling capacitor, so that the current is reduced. The line becomes longer and the decoupling effect cannot be obtained. Further, the distance between the adjacent capacitors and the wavelength of the high-frequency current flowing through the line coincide with each other, causing a resonance phenomenon and increasing radiation noise. Furthermore, when a multilayer ceramic capacitor with a small ESR and good frequency characteristics is used, simply inserting a chip with a large capacitance and a chip with a small capacitance into a power supply line in parallel will cause a sharp impedance characteristic with respect to frequency. When the phase is inverted by 180 °, oscillation occurs and a phenomenon called ringing occurs. Therefore, there is a problem that a resistor must be inserted in series with a chip having a large capacitance.
【０００５】上述したことから、回路基板上に最低２個
のコンデンサと抵抗を実装する必要があり、その実装も
共振現象を引き起こさない距離が必要であるため、実装
時の部品点数が多く、かつ、実装面積が大きくなるとい
う問題点があった。[0005] As described above, it is necessary to mount at least two capacitors and resistors on a circuit board, and the mounting requires a distance that does not cause a resonance phenomenon. Therefore, the number of components at the time of mounting is large, and However, there is a problem that the mounting area becomes large.
【０００６】このデカップリング・コンデンサの不都合
を解消するコンデンサとして、２つ以上の容量の異なる
積層コンデンサ部を有する１チップにした積層セラミッ
クコンデンサが発明された。この１チップにした積層コ
ンデンサとして、特開平７−１４２２８５号公報や特願
平８−１６２３６８号公報に開示されるものがあるが、
いずれの積層セラミックコンデンサも周波数の広帯域化
の効果は上がっているが、異なる容量部を並列接続した
際のリンギングについては考慮されておらず、大容量部
を形成した場合、その効果は不十分であった。As a capacitor for solving the problem of the decoupling capacitor, a multilayer ceramic capacitor having a single chip having two or more multilayer capacitor portions having different capacities has been invented. Examples of the one-chip multilayer capacitor include those disclosed in JP-A-7-142285 and Japanese Patent Application No. 8-162368.
All multilayer ceramic capacitors have an effect of increasing the frequency band.However, ringing when different capacitors are connected in parallel is not considered, and when a large capacitor is formed, the effect is insufficient. there were.
【０００７】それ故に、本発明の課題は、複数の容量の
異なる積層セラミックコンデンサ部を有した１チップ部
品を構成し、大きな容量部の等価直列抵抗を大きくし、
電源回路で発生するリンギングを抑制できて、高周波特
性が良く、しかも実装時の部品点数及び実装面積を低減
することが可能な積層セラミックコンデンサを提供する
事にある。Therefore, an object of the present invention is to constitute a one-chip component having a plurality of multilayer ceramic capacitor portions having different capacities, to increase the equivalent series resistance of a large capacitance portion,
An object of the present invention is to provide a multilayer ceramic capacitor that can suppress ringing generated in a power supply circuit, has good high-frequency characteristics, and can reduce the number of components and the mounting area during mounting.
【０００８】[0008]
【課題を解決するための手段】請求項１記載の発明によ
れば、誘電体セラミック層と内部電極層を交互に積層し
て成り、容量の異なる複数の積層コンデンサ部を有した
積層体と、該積層体の外表面上に設けられ、前記複数の
積層コンデンサ部を並列に接続する外部電極とを含む積
層セラミックコンデンサにおいて、前記複数の積層コン
デンサ部の中で最も大容量の積層コンデンサ部と前記外
部電極との間に、高抵抗外部電極が介在しており、該高
抵抗外部電極は、前記積層体の外表面上に設けられ、前
記外部電極よりも電気抵抗が大きいことを特徴とする積
層セラミックコンデンサが得られる。According to the first aspect of the present invention, there is provided a laminated body having a plurality of laminated capacitor portions having different capacities, each of which is formed by alternately laminating dielectric ceramic layers and internal electrode layers; A multilayer ceramic capacitor provided on an outer surface of the multilayer body and including an external electrode for connecting the plurality of multilayer capacitor sections in parallel, wherein the multilayer capacitor section having the largest capacity among the plurality of multilayer capacitor sections and A high-resistance external electrode is interposed between the external electrode and the high-resistance external electrode, and the high-resistance external electrode is provided on an outer surface of the laminate, and has a higher electrical resistance than the external electrode. A ceramic capacitor is obtained.
【０００９】請求項２記載の発明によれば、所定の積層
方向に沿って誘電体セラミック層と内部電極層を交互に
積層して成り、前記積層方向で並んだ大容量の積層コン
デンサ部及び小容量の積層コンデンサ部を有した直方体
状の積層体と、該積層体の外表面上に設けられ、前記大
容量の積層コンデンサ部と前記小容量の積層コンデンサ
部を並列に接続する外部電極とを含む積層セラミックコ
ンデンサにおいて、前記大容量の積層コンデンサ部と前
記外部電極との間に、高抵抗外部電極が介在しており、
該高抵抗外部電極は、前記積層体の外表面上に設けら
れ、前記外部電極よりも電気抵抗が大きいことを特徴と
する積層セラミックコンデンサが得られる。According to the second aspect of the present invention, the dielectric ceramic layers and the internal electrode layers are alternately laminated along a predetermined laminating direction, and the large-capacity laminated capacitor portion and the small-capacity laminated capacitor portion are arranged in the laminating direction. A rectangular parallelepiped laminated body having a laminated capacitor part having a capacity, and an external electrode provided on the outer surface of the laminated body and connecting the large-capacity laminated capacitor part and the small-capacity laminated capacitor part in parallel. In the multilayer ceramic capacitor including, between the large-capacity multilayer capacitor portion and the external electrode, a high-resistance external electrode is interposed,
The high-resistance external electrode is provided on the outer surface of the multilayer body, and a multilayer ceramic capacitor characterized by having a higher electric resistance than the external electrode is obtained.
【００１０】請求項３記載の発明によれば、前記大容量
の積層コンデンサ部を構成する内部電極層が、前記積層
体の相対向する第１及び第２の側面上に引き出されてお
り、前記高抵抗外部電極が、前記大容量の積層コンデン
サ部を構成する内部電極層の引出部分を覆うように、前
記第１及び第２の側面上に設けられ、前記大容量の積層
コンデンサ部を構成する内部電極層に接続されており、
前記小容量の積層コンデンサ部を構成する内部電極層
が、前記積層体の前記第１及び第２の側面に隣接する第
３及び第４の側面上に引き出されており、前記外部電極
が、前記第３及び第４の側面からそれぞれ前記第１及び
第２の側面に掛けて設けられ、前記小容量の積層コンデ
ンサ部を構成する内部電極層に接続されると共に前記高
抵抗外部電極を覆っていることを特徴とする請求項２記
載の積層セラミックコンデンサが得られる。According to the third aspect of the present invention, the internal electrode layers constituting the large-capacity multilayer capacitor portion are drawn out on the opposed first and second side surfaces of the laminate. A high-resistance external electrode is provided on the first and second side surfaces so as to cover a lead-out portion of an internal electrode layer constituting the large-capacity multilayer capacitor portion, and constitutes the large-capacity multilayer capacitor portion. Connected to the internal electrode layer,
An internal electrode layer constituting the small-capacity multilayer capacitor portion is drawn out on third and fourth side surfaces adjacent to the first and second side surfaces of the multilayer body, and the external electrode is provided on the third and fourth side surfaces. The third and fourth side surfaces are provided so as to extend over the first and second side surfaces, respectively, and are connected to the internal electrode layers constituting the small-capacity multilayer capacitor portion and cover the high-resistance external electrodes. A multilayer ceramic capacitor according to claim 2 is obtained.
【００１１】請求項４記載の発明によれば、前記大容量
の積層コンデンサ部と前記小容量部の積層コンデンサ部
の間隔が、０．１５ｍｍ以上であることを特徴とする請
求項２又は３記載の積層セラミックコンデンサが得られ
る。According to a fourth aspect of the present invention, the distance between the large-capacity multilayer capacitor portion and the small-capacity multilayer capacitor portion is 0.15 mm or more. Is obtained.
【００１２】[0012]
【作用】以上のように構成した積層セラミックコンデン
サによれば、電源回路に発生するリンギングを抑制し、
高周波特性が良く、複数の容量の異なる積層セラミック
コンデンサ部が１チップ部品で形成され、実装時の部品
点数及び実装面積を低減することが可能な積層セラミッ
クコンデンサを得ることができる。According to the multilayer ceramic capacitor configured as described above, ringing generated in the power supply circuit is suppressed,
A multilayer ceramic capacitor having good high-frequency characteristics and a plurality of multilayer ceramic capacitors having different capacities is formed by one chip component, and a multilayer ceramic capacitor capable of reducing the number of components and the mounting area during mounting can be obtained.
【００１３】[0013]
【発明の実施の形態】次に、本発明の積層セラミックコ
ンデンサの実施の形態について図面を参照して説明す
る。Next, an embodiment of the multilayer ceramic capacitor of the present invention will be described with reference to the drawings.
【００１４】図１は本発明の第１の実施形態に係わる積
層セラミックコンデンサの斜視図である。図２は図１に
示す積層セラミックコンデンサの断面を示し、（ａ）は
図１に示すＡ−Ａ′面での断面図、（ｂ）は図１に示す
Ｂ−Ｂ′面での断面図である。図１及び図２に示すよう
に、この積層セラミックコンデンサは、誘電体セラミッ
ク層１と内部電極層２を交互に積層し、その後、脱バイ
ンダ、焼結を行って得られたセラミック焼結体（積層
体）１０に外部電極６によって電気的に接続するように
したものである。FIG. 1 is a perspective view of a multilayer ceramic capacitor according to a first embodiment of the present invention. 2A and 2B show a cross section of the multilayer ceramic capacitor shown in FIG. 1, wherein FIG. 2A is a cross sectional view taken along the plane AA 'shown in FIG. 1, and FIG. 2B is a cross sectional view taken along the plane BB' shown in FIG. It is. As shown in FIGS. 1 and 2, this multilayer ceramic capacitor has a ceramic sintered body obtained by alternately stacking dielectric ceramic layers 1 and internal electrode layers 2 and then performing binder removal and sintering. The laminated body 10 is electrically connected by the external electrode 6.
【００１５】図２から明らかなように、この積層セラミ
ックコンデンサは、誘電体セラミック層１と内部電極層
２を交互に積層した２つの積層コンデンサ部３，４が積
層体厚み方向に所定の容量部間隔７をおいて離され、そ
の外側に設けた誘電体による２つの保護層５と、積層コ
ンデンサ部３に電気的に接続される高抵抗外部電極８
と、積層コンデンサ部４に電気的に接続される外部電極
６とを有している。ここで、高抵抗外部電極８は、導電
ペーストのガラスフリットを増量したものか、或いはＲ
ｕＯ２ 材料を主成分とする抵抗ペーストを用いてセラ
ミック焼結体１０の幅方向の両端面上に形成され、これ
により、セラミック焼結体１０の幅方向の両端面上に引
き出されている積層コンデンサ部３の後述する内部電極
引出部分２ａと電気的に接続されている。外部電極６
は、セラミック焼結体１０の長さ方向の両端面からセラ
ミック焼結体１０の幅方向両端面の側縁部に掛けて形成
され、高抵抗外部電極８を覆うように成っている。これ
により、外部電極６は、積層コンデンサ部３と積層コン
デンサ部４を並列に接続し、また、積層コンデンサ部３
と外部電極６との間には、高抵抗外部電極８が介在する
ように成っている。ここで、積層コンデンサ部３は、も
う一方の積層コンデンサ部４に比べて、誘電体層の厚み
が薄く多層構造であるので、高容量を有する。また、高
抵抗外部電極８は、外部電極６と比較して抵抗値が高く
なっている。誘電体セラミック層１の誘電率εは、１０
０〜２００００とする。内部電極層２は、低融点金属で
あるＡｇ、Ａｇ−Ｐｄ、Ｎｉ、Ｃｕ等の誘電体材料と同
時焼成が可能なものを使用した。As is apparent from FIG. 2, this multilayer ceramic capacitor comprises two multilayer capacitor portions 3 and 4 in which dielectric ceramic layers 1 and internal electrode layers 2 are alternately stacked, and has a predetermined capacitance portion in the thickness direction of the multilayer body. Two protective layers 5 made of a dielectric material provided outside and spaced apart from each other by a space 7, and a high-resistance external electrode 8 electrically connected to the multilayer capacitor portion 3.
And an external electrode 6 electrically connected to the multilayer capacitor unit 4. Here, the high resistance external electrode 8 is formed by increasing the glass frit of the conductive paste,
Laminated layers formed on both end surfaces in the width direction of the ceramic sintered body 10 by using a resistance paste containing a uO 2 material as a main component and thereby drawn out on both end surfaces in the width direction of the ceramic sintered body 10 It is electrically connected to an internal electrode lead-out portion 2a of the capacitor portion 3 described later. External electrode 6
Are formed so as to extend from both end surfaces in the longitudinal direction of the ceramic sintered body 10 to the side edges of both end surfaces in the width direction of the ceramic sintered body 10 so as to cover the high-resistance external electrode 8. As a result, the external electrode 6 connects the multilayer capacitor unit 3 and the multilayer capacitor unit 4 in parallel.
A high resistance external electrode 8 is interposed between the external electrode 6 and the external electrode 6. Here, the multilayer capacitor part 3 has a high capacity because the thickness of the dielectric layer is thinner and the multilayer structure is smaller than that of the other multilayer capacitor part 4. The high-resistance external electrode 8 has a higher resistance value than the external electrode 6. The dielectric constant ε of the dielectric ceramic layer 1 is 10
0 to 20,000. As the internal electrode layer 2, a material which can be co-fired with a dielectric material such as a low melting point metal such as Ag, Ag-Pd, Ni, and Cu is used.
【００１６】図３（ａ）は図１に示すＣ−Ｃ′面での断
面図であり、積層コンデンサ部３の内部電極パターンを
示したものである。誘電体セラミック層１の上に内部電
極層２が形成されており、この内部電極層２は、誘電体
セラミック層１の長辺に接する内部電極引出部分２ａを
有している。従って、この内部電極層２は、セラミック
焼結体１０の幅方向両端面上に引き出され、ここで高抵
抗外部電極８に接続され、更に抵抗の低い外部電極６で
覆われた構造に成っている。FIG. 3A is a cross-sectional view taken along the line CC ′ shown in FIG. 1 and shows the internal electrode pattern of the multilayer capacitor unit 3. An internal electrode layer 2 is formed on the dielectric ceramic layer 1, and the internal electrode layer 2 has an internal electrode lead portion 2 a that is in contact with the long side of the dielectric ceramic layer 1. Therefore, the internal electrode layer 2 is drawn out on both end surfaces in the width direction of the ceramic sintered body 10, connected to the high-resistance external electrode 8, and further covered with the external electrode 6 having a low resistance. I have.
【００１７】図３（ｂ）は図１に示すＤ−Ｄ′面での断
面図であり、積層コンデンサ部４の内部電極パターンを
示したものである。誘電体セラミック層１の上に内部電
極層２が形成されており、この内部電極層２は、誘電体
セラミック層１の短辺に接する内部電極引出部分２ｂを
有している。従って、この内部電極層２は、セラミック
焼結体１０の長さ方向両端面上に引き出され、ここで外
部電極６に接続された構造に成っている。FIG. 3B is a cross-sectional view taken along the line DD ′ shown in FIG. 1, and shows the internal electrode pattern of the multilayer capacitor unit 4. An internal electrode layer 2 is formed on the dielectric ceramic layer 1, and the internal electrode layer 2 has an internal electrode lead portion 2 b in contact with a short side of the dielectric ceramic layer 1. Accordingly, the internal electrode layer 2 is drawn out on both end surfaces in the longitudinal direction of the ceramic sintered body 10 and has a structure connected to the external electrode 6 here.
【００１８】次に、本実施形態の積層セラミックコンデ
ンサの周波数−インピーダンス特性について説明する。
図４は図１に示す積層構造を有する積層セラミックコン
デンサの等価回路を示したものである。コンデンサの等
価回路は、一般的に直列のＣ、Ｌ、Ｒで現わされ、積層
コンデンサ部３の等価回路は、Ｃ１ 、Ｌ１ 、Ｒ１ の
直列共振回路で、積層コンデンサ部４の等価回路は、Ｃ
２ 、Ｌ２ 、Ｒ２ の直列共振回路でそれぞれ現され、
これらの積層コンデンサ部３，４は、外部電極６で並列
接続される形となる。しかし、本実施形態の積層セラミ
ックコンデンサでは、積層コンデンサ部３の内部電極と
電気的に接続されている高抵抗外部電極８の導体抵抗Ｒ
３ を外部電極６より大きくしているため、積層コンデ
ンサ部３に直列に抵抗が付加された形で表すことができ
る。Next, the multilayer ceramic capacitor of the present embodiment will be described.
The frequency-impedance characteristics of the sensor will be described.
FIG. 4 shows a multilayer ceramic capacitor having the multilayer structure shown in FIG.
3 shows an equivalent circuit of a capacitor. Capacitors etc.
The value circuit is generally represented by C, L, R in series,
The equivalent circuit of the capacitor section 3 is C1, L1, R1 of
In the series resonance circuit, the equivalent circuit of the multilayer capacitor unit 4 is C
2, L2, R2 Respectively represented by a series resonance circuit of
These multilayer capacitor parts 3 and 4 are connected in parallel with the external electrodes 6.
It will be connected. However, the laminated ceramic of the present embodiment
In a ceramic capacitor, the internal electrodes of the multilayer capacitor unit 3 are
Conductor resistance R of high resistance external electrode 8 electrically connected
3Is larger than the external electrode 6,
It can be expressed in the form of adding a resistor in series to the sensor part 3.
You.
【００１９】図５は図１に示す積層セラミックコンデン
サと比較するために、静電容量が１０μＦのタンタル電
解コンデンサと、静電容量が０．１μＦの積層セラミッ
クコンデンサの周波数−インピーダンス特性を示すグラ
フである。FIG. 5 is a graph showing frequency-impedance characteristics of a tantalum electrolytic capacitor having a capacitance of 10 μF and a multilayer ceramic capacitor having a capacitance of 0.1 μF for comparison with the multilayer ceramic capacitor shown in FIG. is there.
【００２０】図６は図１に示す積層セラミックコンデン
サと比較するために、静電容量が１０μＦと、０．１μ
Ｆの積層セラミックコンデンサを並列接続したときの周
波数−インピーダンス特性を示すグラフである。FIG. 6 shows that the capacitance is 10 μF and 0.1 μF for comparison with the multilayer ceramic capacitor shown in FIG.
5 is a graph showing frequency-impedance characteristics when a multilayer ceramic capacitor F is connected in parallel.
【００２１】図７は図１に示す積層セラミックコンデン
サの周波数−インピーダンス特性を示すグラフである。
積層セラミックコンデンサの素子形状は、長さ３．２ｍ
ｍ、幅が２．５ｍｍのものを使用し、誘電体セラミック
層１と内部電極層２を交互に積層した２つの積層コンデ
ンサ部３，４の静電容量をそれぞれ１０μＦと０．１μ
Ｆとなるように積層数及び誘電体層厚みを設計した。こ
のとき、２つの積層コンデンサ部３，４の間隔は、０．
３ｍｍとした。ここで、小さな容量部の誘電体層厚みが
２つの積層コンデンサ部３，４の距離よりも大きくなっ
ても良い。尚、積層セラミックコンデンサの共振周波数
及びインピーダンス値は、使用する材料の誘電率、抵抗
率及び積層構造によっても変化する。FIG. 7 is a graph showing frequency-impedance characteristics of the multilayer ceramic capacitor shown in FIG.
The element shape of the multilayer ceramic capacitor is 3.2 m in length.
m and a width of 2.5 mm, and the capacitances of two multilayer capacitor portions 3 and 4 in which dielectric ceramic layers 1 and internal electrode layers 2 are alternately laminated are 10 μF and 0.1 μm, respectively.
The number of layers and the thickness of the dielectric layer were designed to be F. At this time, the interval between the two multilayer capacitor units 3 and 4 is set to 0.
3 mm. Here, the thickness of the dielectric layer of the small capacitance portion may be larger than the distance between the two multilayer capacitor portions 3 and 4. Note that the resonance frequency and the impedance value of the multilayer ceramic capacitor also change depending on the dielectric constant, the resistivity, and the multilayer structure of the material used.
【００２２】図７の結果より、タンタル電解と積層セラ
ミックコンデンサを並列接続したものと比較してＥＳＲ
が低く、積層コンデンサの並列の組合せに対して容量大
部の共振点の急峻な位相の反転が抑えられることが分か
り、従来構造に比較して高周波領域でのインピーダンス
値の向上が図られた。From the results shown in FIG. 7, the ESR is higher than that obtained by connecting a tantalum electrolytic capacitor and a multilayer ceramic capacitor in parallel.
It was found that the steep phase inversion of the resonance point of the large capacitance portion was suppressed for the parallel combination of the multilayer capacitors, and the impedance value in the high frequency region was improved as compared with the conventional structure.
【００２３】図８は本発明の第２の実施形態に係わる積
層セラミックコンデンサの断面を示し、（ａ）は図３
（ａ）と同じ部位での断面図、（ｂ）は図３（ｂ）と同
じ部位での断面図である。FIG. 8 shows a cross section of a multilayer ceramic capacitor according to a second embodiment of the present invention, and FIG.
FIG. 3A is a cross-sectional view at the same site as FIG. 3B, and FIG. 3B is a cross-sectional view at the same site as FIG.
【００２４】本実施形態は、第１の実施形態と略同構成
であるので、第１の実施形態と構成の同じ部分或いは同
様の部分については、第１の実施形態と同じ参照番号を
付してその説明を省略し、構成の異なる部分についての
み説明する。This embodiment has substantially the same configuration as that of the first embodiment. Therefore, the same reference numerals as those in the first embodiment denote the same or similar parts as those in the first embodiment. The description thereof will be omitted, and only different portions will be described.
【００２５】第１の実施形態では、セラミック焼結体１
０の長さ方向両端部において、それぞれ、外部電極８を
セラミック焼結体１０の幅方向一端面にしか形成してな
いが、本実施形態の場合、セラミック焼結体１０の長さ
方向両端部において、それぞれ、外部電極８をセラミッ
ク焼結体１０の幅方向両端面に形成してある（このセラ
ミック焼結体１０の幅方向両端面に形成された高抵抗外
部電極８の内、一方は、ダミーである）。In the first embodiment, the ceramic sintered body 1
The external electrodes 8 are formed only on one end surface in the width direction of the ceramic sintered body 10 at both ends in the length direction of the ceramic sintered body 10, respectively. , The external electrodes 8 are formed on both end surfaces in the width direction of the ceramic sintered body 10 (one of the high resistance external electrodes 8 formed on both end surfaces in the width direction of the ceramic sintered body 10, Is a dummy).
【００２６】[0026]
【発明の効果】以上、説明したように本発明によれば、
電源回路に発生するリンギングを抑制し、高周波特性が
良く、大きな容量と小さな容量の積層セラミックコンデ
ンサ部が１チップ部品で形成され、実装時の部品点数及
び実装面積の低減を図るための積層セラミックコンデン
サを提供することが可能になった。As described above, according to the present invention,
A multilayer ceramic capacitor that suppresses ringing generated in the power supply circuit, has high-frequency characteristics, and has a large capacity and a small capacity, is formed by one chip component, and reduces the number of components and mounting area during mounting. It became possible to provide.
【図１】本発明の一実施形態に係わる積層セラミックコ
ンデンサの斜視図である。FIG. 1 is a perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention.
【図２】図１に示す積層セラミックコンデンサの断面を
示し、（ａ）は図１に示すＡ−Ａ′面での断面図、
（ｂ）は図１に示すＢ−Ｂ′面での断面図である。2 shows a cross section of the multilayer ceramic capacitor shown in FIG. 1, (a) is a cross sectional view taken along the line AA ′ shown in FIG. 1,
FIG. 2B is a cross-sectional view taken along the line BB ′ shown in FIG.
【図３】図１に示す積層セラミックコンデンサの断面を
示し、（ａ）は図１に示すＣ−Ｃ′面での断面図、
（ｂ）は図１に示すＤ−Ｄ′面での断面図である。3 shows a cross section of the multilayer ceramic capacitor shown in FIG. 1, (a) is a cross-sectional view taken along the line CC ′ shown in FIG. 1,
FIG. 2B is a cross-sectional view taken along the line DD ′ shown in FIG.
【図４】図１に示す積層構造を有する積層セラミックコ
ンデンサの等価回路図ある。FIG. 4 is an equivalent circuit diagram of the multilayer ceramic capacitor having the multilayer structure shown in FIG.
【図５】図１に示す積層セラミックコンデンサと比較す
るために、静電容量が１０μＦのタンタル電解コンデン
サと、静電容量が０．１μＦの積層セラミックコンデン
サの周波数−インピーダンス特性を示すグラフである。5 is a graph showing frequency-impedance characteristics of a tantalum electrolytic capacitor having a capacitance of 10 μF and a multilayer ceramic capacitor having a capacitance of 0.1 μF for comparison with the multilayer ceramic capacitor shown in FIG. 1;
【図６】図１に示す積層セラミックコンデンサと比較す
るために、静電容量が１０μＦと、０．１μＦの積層セ
ラミックコンデンサを並列接続したときの周波数−イン
ピーダンス特性を示すグラフである。6 is a graph showing frequency-impedance characteristics when a multilayer ceramic capacitor having a capacitance of 10 μF and a capacitance of 0.1 μF are connected in parallel for comparison with the multilayer ceramic capacitor shown in FIG. 1;
【図７】図１に示す積層セラミックコンデンサの周波数
−インピーダンス特性を示すグラフである。FIG. 7 is a graph showing frequency-impedance characteristics of the multilayer ceramic capacitor shown in FIG.
【図８】図８は本発明の第２の実施形態に係わる積層セ
ラミックコンデンサの断面を示し、（ａ）は図３（ａ）
と同じ部位での断面図、（ｂ）は図３（ｂ）と同じ部位
での断面図である。FIG. 8 shows a cross section of a multilayer ceramic capacitor according to a second embodiment of the present invention, wherein FIG.
FIG. 3B is a cross-sectional view at the same site as FIG. 3B.
１ 誘電体セラミック層 ２ 内部電極層 ３ 積層コンデンサ部（大きな容量部） ４ 積層コンデンサ部（小さな容量部） ５ 誘電体による保護層 ６ 外部電極 ７ 容量部間隔 ８ 高抵抗外部電極 １０ セラミック焼結体 DESCRIPTION OF SYMBOLS 1 Dielectric ceramic layer 2 Internal electrode layer 3 Multilayer capacitor part (large capacity part) 4 Multilayer capacitor part (small capacity part) 5 Protective layer made of dielectric material 6 External electrode 7 Capacitance part interval 8 High resistance external electrode 10 Ceramic sintered body
───────────────────────────────────────────────────── フロントページの続き (72)発明者 村田 正浩 兵庫県宍粟郡山崎町須賀沢231番地 トー キンセラミクス株式会社内 Ｆターム(参考） 5E001 AB03 AC02 AC09 AC10 AF00 AF06 AH05 AH09 AJ01 AJ03 AZ01 5E082 AA01 AB03 BB05 BB07 BC40 CC02 DD02 EE04 EE23 EE35 FG26 FG54 GG10 HH43 JJ03 JJ13 JJ23 LL02 MM24 PP02 PP09 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Masahiro Murata 231 Sukazawa, Yamazaki-cho, Shiso-gun, Hyogo Tokin Ceramics Co., Ltd. F-term (reference) 5E001 AB03 AC02 AC09 AC10 AF00 AF06 AH05 AH09 AJ01 AJ03 AZ01 5E082 AA01 AB03 BB05 BB07 BC40 CC02 DD02 EE04 EE23 EE35 FG26 FG54 GG10 HH43 JJ03 JJ13 JJ23 LL02 MM24 PP02 PP09
Claims (4)
に積層して成り、容量の異なる複数の積層コンデンサ部
を有した積層体と、該積層体の外表面上に設けられ、前
記複数の積層コンデンサ部を並列に接続する外部電極と
を含む積層セラミックコンデンサにおいて、前記複数の
積層コンデンサ部の中で最も大容量の積層コンデンサ部
と前記外部電極との間に、高抵抗外部電極が介在してお
り、該高抵抗外部電極は、前記積層体の外表面上に設け
られ、前記外部電極よりも電気抵抗が大きいことを特徴
とする積層セラミックコンデンサ。1. A laminated body comprising a plurality of laminated capacitor portions having different capacitances, wherein said laminated body is formed by alternately laminating dielectric ceramic layers and internal electrode layers, and said plurality of laminated capacitor portions are provided on an outer surface of said laminated body. In a multilayer ceramic capacitor including an external electrode that connects the multilayer capacitor unit in parallel, a high-resistance external electrode is interposed between the multilayer capacitor unit having the largest capacity among the plurality of multilayer capacitor units and the external electrode. Wherein the high-resistance external electrode is provided on an outer surface of the multilayer body and has a higher electrical resistance than the external electrode.
ク層と内部電極層を交互に積層して成り、前記積層方向
で並んだ大容量の積層コンデンサ部及び小容量の積層コ
ンデンサ部を有した直方体状の積層体と、該積層体の外
表面上に設けられ、前記大容量の積層コンデンサ部と前
記小容量の積層コンデンサ部を並列に接続する外部電極
とを含む積層セラミックコンデンサにおいて、前記大容
量の積層コンデンサ部と前記外部電極との間に、高抵抗
外部電極が介在しており、該高抵抗外部電極は、前記積
層体の外表面上に設けられ、前記外部電極よりも電気抵
抗が大きいことを特徴とする積層セラミックコンデン
サ。2. A large-capacity multilayer capacitor portion and a small-capacity multilayer capacitor portion, which are formed by alternately laminating dielectric ceramic layers and internal electrode layers along a predetermined lamination direction, and are arranged in the lamination direction. The multilayer ceramic capacitor includes: a rectangular parallelepiped multilayer body; and an external electrode provided on an outer surface of the multilayer body and connecting the large-capacity multilayer capacitor section and the small-capacity multilayer capacitor section in parallel. A high-resistance external electrode is interposed between the multilayer capacitor portion of the capacitor and the external electrode, and the high-resistance external electrode is provided on an outer surface of the multilayer body and has a higher electrical resistance than the external electrode. Multilayer ceramic capacitors characterized by being large.
る内部電極層が、前記積層体の相対向する第１及び第２
の側面上に引き出されており、前記高抵抗外部電極が、
前記大容量の積層コンデンサ部を構成する内部電極層の
引出部分を覆うように、前記第１及び第２の側面上に設
けられ、前記大容量の積層コンデンサ部を構成する内部
電極層に接続されており、前記小容量の積層コンデンサ
部を構成する内部電極層が、前記積層体の前記第１及び
第２の側面に隣接する第３及び第４の側面上に引き出さ
れており、前記外部電極が、前記第３及び第４の側面か
らそれぞれ前記第１及び第２の側面に掛けて設けられ、
前記小容量の積層コンデンサ部を構成する内部電極層に
接続されると共に前記高抵抗外部電極を覆っていること
を特徴とする請求項２記載の積層セラミックコンデン
サ。3. An internal electrode layer constituting the large-capacity multilayer capacitor portion includes first and second opposed layers of the multilayer body.
And the high-resistance external electrode is
The first capacitor is provided on the first and second side surfaces so as to cover a lead-out portion of the internal electrode layer forming the large-capacity multilayer capacitor portion, and is connected to the internal electrode layer forming the large-capacity multilayer capacitor portion. An internal electrode layer constituting the small-capacity multilayer capacitor portion is drawn out on third and fourth side surfaces adjacent to the first and second side surfaces of the multilayer body, and the external electrode Are provided on the first and second side surfaces from the third and fourth side surfaces, respectively.
3. The multilayer ceramic capacitor according to claim 2, wherein the multilayer ceramic capacitor is connected to an internal electrode layer forming the small-capacity multilayer capacitor portion and covers the high-resistance external electrode.
容量部の積層コンデンサ部の間隔が、０．１５ｍｍ以上
であることを特徴とする請求項２又は３記載の積層セラ
ミックコンデンサ。4. The multilayer ceramic capacitor according to claim 2, wherein an interval between the large-capacity multilayer capacitor portion and the small-capacity multilayer capacitor portion is 0.15 mm or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP37069999A JP2001185449A (en) | 1999-12-27 | 1999-12-27 | Laminated ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP37069999A JP2001185449A (en) | 1999-12-27 | 1999-12-27 | Laminated ceramic capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001185449A true JP2001185449A (en) | 2001-07-06 |
Family
ID=18497446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP37069999A Withdrawn JP2001185449A (en) | 1999-12-27 | 1999-12-27 | Laminated ceramic capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001185449A (en) |
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| JP2016187036A (en) * | 2016-06-02 | 2016-10-27 | 太陽誘電株式会社 | Multilayer ceramic capacitor |
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