JP2001168250A - Insulating substrate for semiconductor device, semiconductor device using that and manufacturing method of substrate - Google Patents
Insulating substrate for semiconductor device, semiconductor device using that and manufacturing method of substrateInfo
- Publication number
- JP2001168250A JP2001168250A JP35212399A JP35212399A JP2001168250A JP 2001168250 A JP2001168250 A JP 2001168250A JP 35212399 A JP35212399 A JP 35212399A JP 35212399 A JP35212399 A JP 35212399A JP 2001168250 A JP2001168250 A JP 2001168250A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- connection layer
- circuit layer
- connection
- base material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、セラミックス基材
にＡｌを主体とする導体回路層を実装した半導体用部材
およびそれを用いた半導体装置並びに該基板の製造方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor member in which a conductive circuit layer mainly composed of Al is mounted on a ceramic substrate, a semiconductor device using the same, and a method of manufacturing the substrate.
【０００２】[0002]
【従来の技術】従来、アルミニウムにより形成された導
体回路層（以下単に回路層と言う）をセラミックス基材
に接続する方法としては、たとえば特開平９−２３４８
２６に示されるようなアルミニウム溶融体にセラミック
ス基材を直接接触させ、順次接触部をアルミニウム凝固
温度以下にして接続する方法や、特許第２６５８４３５
に示されるようなＡｌＮ基板の表面に酸化膜やガラス膜
を形成してＡｌ−Ｓｉ系ろう材又はＡｌ−Ｇｅ系ろう材
を用いて接続する方法、実公平８−１０２０２に示され
るようなＡｌＮ基板の表面を粗面化してＡｌ−Ｓｉ系ろ
う材又はＡｌ−Ｇｅ系ろう材を用いて接続する方法、特
開平９−１８８５７３に示されるようなアルミニウム板
を融点付近まで加熱した後、セラミックス基材と圧力を
かけて接合する方法等が提案されている。2. Description of the Related Art Conventionally, as a method of connecting a conductor circuit layer (hereinafter simply referred to as a circuit layer) formed of aluminum to a ceramic substrate, for example, Japanese Patent Application Laid-Open No. 9-2348 discloses a method.
26, a ceramic base material is brought into direct contact with an aluminum melt, and the contact portions are successively brought down to the aluminum solidification temperature or lower.
A method of forming an oxide film or a glass film on the surface of an AlN substrate and connecting using an Al-Si brazing material or an Al-Ge brazing material as shown in JP-A-8-10202. A method in which the surface of a substrate is roughened and connected using an Al-Si-based brazing material or an Al-Ge-based brazing material. There has been proposed a method of joining materials by applying pressure.
【０００３】[0003]
【発明が解決しようとする課題】アルミニウムを融点付
近まで溶かしてセラミックス基板に接続する方法では、
アルミニウムとセラミックス基材の接続時の熱膨張係数
の差が大きく、接続後の残留応力が非常に大きい。この
ため、熱サイクル試験を施した時にかかる熱応力も大き
くなり、少ない回数での割れやクラックが発生しやすく
なる。そのため、セラミックス基材にアルミニウムを接
続する時の温度は、半導体素子をダイボンディングする
温度より高い温度で、出来るだけ低温の方が望ましい。
また、アルミニウムが溶融しているため、導体回路層と
して機能させるための事後の仕上げ工程も必要となる。In a method of connecting aluminum to a ceramic substrate by melting aluminum to a temperature close to its melting point,
The difference in the coefficient of thermal expansion when connecting aluminum and the ceramic substrate is large, and the residual stress after connection is very large. For this reason, the thermal stress applied when performing a thermal cycle test also becomes large, and cracks and cracks are likely to occur in a small number of times. Therefore, the temperature at which aluminum is connected to the ceramic base is preferably higher than the temperature at which the semiconductor element is die-bonded, and is as low as possible.
In addition, since aluminum is melted, a subsequent finishing step for functioning as a conductive circuit layer is also required.
【０００４】この課題を解決する方法として、純アルミ
ニウムより低融点で半導体素子をダイボンディングする
温度より高融点のＡｌ−Ｓｉろう材又はＡｌ−Ｇｅろう
材を用いて純アルミニウム板を接続する方法が提案され
ている。この場合、例えば実公平８−１０２０２に記載
されているようにＡｌＮ基材の表面を粗面化するだけで
は十分な接続強度が確保されない。そこで十分な接続強
度を確保するためには、例えば特許第２６５８４３５に
記載のようにＡｌＮ基材の表面に酸化膜（主にＡｌ2Ｏ3
からなる）やガラス膜を形成する必要がある。この酸化
膜やガラス膜は他の構成材料であるアルミニウムや窒化
アルミニウムに比べて熱伝導率が低いため、この膜によ
り基板の放熱能力が低下する問題がある。As a method of solving this problem, there is a method of connecting a pure aluminum plate using an Al-Si brazing material or an Al-Ge brazing material having a lower melting point than pure aluminum and a melting point higher than a temperature at which a semiconductor element is die-bonded. Proposed. In this case, sufficient connection strength cannot be ensured only by roughening the surface of the AlN substrate as described in, for example, Japanese Utility Model Publication No. 8-10202. Therefore, in order to ensure a sufficient connection strength, for example, as described in Japanese Patent No. 2658435, an oxide film (mainly Al 2 O 3
) Or a glass film. Since the oxide film and the glass film have a lower thermal conductivity than other constituent materials such as aluminum and aluminum nitride, there is a problem that the heat dissipation capability of the substrate is reduced by the film.
【０００５】本発明は、かかる従来の事情に鑑み、セラ
ミックス基材上にアルミニウムまたはアルミニウム合金
の板状回路層が形成されたこの種の基板について、以上
述べた従来のものに比べより大きな放熱能力を持ち、温
度サイクル試験等の信頼性試験に於いて格段に優れた性
能を有する半導体装置用絶縁基板の提供を目的とする。In view of the above circumstances, the present invention provides a substrate of this type, in which a plate-like circuit layer of aluminum or an aluminum alloy is formed on a ceramic substrate, having a greater heat dissipation capability than the above-described conventional substrate. It is an object of the present invention to provide an insulating substrate for a semiconductor device which has remarkably excellent performance in a reliability test such as a temperature cycle test.
【０００６】[0006]
【課題を解決するための手段】上記の目的を達成するた
め、本発明は下記の構成よりなる。 （１）セラミックスからなる絶縁基材の一方または両方
の主面上に、Ａｌおよび／又は、Ａｌとの合金化により
その融点を下げる合金成分とを含む接続層と、Ａｌとそ
の合金成分とを含み、接続層よりもＡｌ量の多い回路層
とが、順次形成されており、回路層の側面全周の端が、
接続層の側面全周の端よりも５０μｍ以上内側になるよ
うに配置されているとともに、回路層中には接続層の合
金成分が拡散しており、その合金成分の量が、表面に向
かって減少している半導体用絶縁基板。In order to achieve the above object, the present invention comprises the following constitution. (1) A connection layer containing Al and / or an alloy component that lowers its melting point by alloying with Al, and Al and its alloy component on one or both main surfaces of an insulating base made of ceramics. And a circuit layer having a larger amount of Al than the connection layer are sequentially formed.
The connection layer is arranged so as to be at least 50 μm inward from the end of the entire side surface of the connection layer, and the alloy component of the connection layer is diffused in the circuit layer, and the amount of the alloy component increases toward the surface. Insulating substrates for semiconductors are decreasing.
【０００７】（２）前記回路層の側面全周に、Ａｌとそ
の合金成分を含むメニスカスが形成されている前記
（１）記載の半導体装置用絶縁基板。(2) The insulating substrate for a semiconductor device according to (1), wherein a meniscus containing Al and its alloy component is formed all around the side surface of the circuit layer.
【０００８】（３）前記絶縁基材の一方の主面上に、前
記接続層と回路層が接続され、他方の主面上に、前記接
続層を介して冷却構造体が接続されている前記（１）又
は（２）記載の半導体装置用絶縁基板。(3) The connection layer and the circuit layer are connected to one main surface of the insulating base material, and the cooling structure is connected to the other main surface via the connection layer. The insulating substrate for a semiconductor device according to (1) or (2).
【０００９】（４）前記絶縁基材が、窒化アルミニウ
ム、窒化珪素、炭化珪素を主成分としたセラミックスで
ある前記（１）ないし（３）のいずれかに記載の半導体
装置用絶縁基板。(4) The insulating substrate for a semiconductor device according to any one of (1) to (3), wherein the insulating base is a ceramic containing aluminum nitride, silicon nitride, and silicon carbide as main components.
【００１０】（５）前記（１）ないし（４）のいずれか
に記載の絶縁基板を用いた半導体装置。(5) A semiconductor device using the insulating substrate according to any one of (1) to (4).
【００１１】（６）セラミックスからなる絶縁基材と、
絶縁基材上に形成される接続層と回路層の原料であるＡ
ｌ、Ａｌとの合金化によりその融点を下げる合金成分を
含む金属素材群とを準備する工程と、絶縁基材の片方ま
たは両方の主面上に、金属素材群の内の少なくとも１種
を含み、接続層を形成する工程と、接続層を構成する金
属素材よりもＡｌ量が多く、主面外寸が接続層のそれよ
りも全周にわたって５０μｍ以上小さい回路層の素材を
準備する工程と、この回路層の素材を接続層上に配置
し、非酸化性雰囲気中、接続層を構成する金属の融点以
上、回路層の素材の融点以下の温度下で加熱して回路層
を形成する工程とを含む半導体用絶縁基板の製造方法。(6) an insulating base made of ceramics;
A which is a raw material of the connection layer and the circuit layer formed on the insulating base material
l, a step of preparing a metal material group containing an alloy component that lowers its melting point by alloying with Al; and including at least one of the metal material groups on one or both main surfaces of the insulating base material. A step of forming a connection layer; and a step of preparing a circuit layer material having a larger amount of Al than the metal material constituting the connection layer and having a main surface outer dimension smaller than that of the connection layer by 50 μm or more over its entire circumference. Arranging the circuit layer material on the connection layer, forming a circuit layer by heating at a temperature not lower than the melting point of the metal constituting the connection layer and not higher than the melting point of the circuit layer material in a non-oxidizing atmosphere; A method for manufacturing an insulating substrate for a semiconductor, comprising:
【００１２】（７）前記接続層を形成する工程は、前記
金属素材群の内の少なくとも１種を含む第一の接続層
と、第一の接続層よりも合金成分の多い第二の接続層と
を形成する工程である前記（６）記載の半導体装置用絶
縁基板の製造方法。(7) The step of forming the connection layer includes the steps of: a first connection layer containing at least one of the metal material groups; and a second connection layer having a larger alloy component than the first connection layer. The method of manufacturing an insulating substrate for a semiconductor device according to (6), wherein
【００１３】本発明の絶縁基板は、半導体チップを搭載
する主面側のみか、又はその反対側の主面との両面とも
Ａｌ又はＡｌ合金からなる回路層が形成されている。こ
の回路層と基材との接続強度と回路層自体の電気伝導性
を高いレベルにするため、回路層と基材との間には、接
続層を介在させる。これらの二層は後述のように真空加
熱によって接続されるため、少なくとも接続層中に存在
する合金成分はある程度の厚み範囲内で回路層中にも拡
散する。したがって本発明の両層間の境目は不明瞭とな
る。しかしながら通常は上の層となる回路は接続層より
もＡｌ含有量の多い金属素材によって形成するため、回
路層中にはその表面方向に合金成分の濃淡が生じる。つ
まり回路層中では、表面方向に合金成分が減少してい
る。すなわち回路層において、その接続層との境目の方
がその表面よりも合金成分が多く成っている。In the insulating substrate of the present invention, a circuit layer made of Al or an Al alloy is formed only on the main surface side on which the semiconductor chip is mounted, or on both main surfaces on the opposite side. In order to increase the connection strength between the circuit layer and the base material and the electrical conductivity of the circuit layer itself to a high level, a connection layer is interposed between the circuit layer and the base material. Since these two layers are connected by vacuum heating as described later, at least the alloy component present in the connection layer diffuses into the circuit layer within a certain thickness range. Therefore, the boundary between the two layers of the present invention becomes unclear. However, since a circuit to be an upper layer is usually formed of a metal material having a higher Al content than that of the connection layer, shading of an alloy component occurs in the surface direction of the circuit layer. That is, in the circuit layer, the alloy component decreases in the surface direction. That is, in the circuit layer, the boundary between the circuit layer and the connection layer has more alloying components than the surface.
【００１４】例えば、同層の表面では当初の供給素材と
同じ純Ａｌに近い合金成分がより少ない層があり、アル
ミニウム部分から例えばＭｇやＳｉ等の合金成分が徐々
に下に向かって増加していたり、又は急激にある部分か
ら多くなったりする。For example, on the surface of the same layer, there is a layer in which the alloy component close to pure Al, which is the same as the original supply material, has a smaller amount, and the alloy component such as Mg or Si gradually increases downward from the aluminum portion. Or suddenly increases from a certain part.
【００１５】又本発明の回路基板の基材の接続層との境
目の酸素量は少ない。その境目から０．１ｍｍの範囲内
での量は、５重量％以下、さらには３重量％以下とする
のが望ましい。The amount of oxygen at the boundary between the substrate and the connection layer of the circuit board of the present invention is small. The amount within a range of 0.1 mm from the boundary is preferably 5% by weight or less, more preferably 3% by weight or less.
【００１６】又本発明の接続層の外周端は、その全周に
わたって基材の外周端より内側にある。又回路層の外周
端は、その全周にわたって接続層の外周端より内側にあ
る。内側へのそれぞれのズレは、基材と接続層間で基材
の主面方向の外寸に対し１００μｍ以上、接続層と回路
層間で基材の主面方向の外寸に対し１００μｍ以上とす
るのが望ましい。このようにすることにより熱サイクル
に対する信頼性は、顕著に向上する。The outer peripheral end of the connection layer of the present invention is located inside the outer peripheral end of the base material over the entire periphery. The outer peripheral edge of the circuit layer is located inside the outer peripheral edge of the connection layer over the entire circumference. Each deviation toward the inside should be 100 μm or more with respect to the outer dimension in the main surface direction of the base material between the base material and the connection layer, and 100 μm or more relative to the outer dimension in the main surface direction of the base material between the connection layer and the circuit layer. Is desirable. By doing so, the reliability for the thermal cycle is significantly improved.
【００１７】さらに本発明の基板の回路層の外周端に
は、下方に向かって裾を広げた形でのメニスカスが形成
されているのが望ましい。このメニスカスの厚み方向に
対する傾斜度合は、接続条件にもよるが、通常は裾の部
分でのその接線方向と基材主面方向との角度が８０゜以
下であるのが望ましい。望ましくは６０゜以下である。Further, it is desirable that a meniscus is formed on the outer peripheral end of the circuit layer of the substrate of the present invention in such a manner that its skirt is expanded downward. Although the degree of inclination of the meniscus with respect to the thickness direction depends on the connection conditions, it is usually desirable that the angle between the tangential direction at the skirt portion and the main surface direction of the base material be 80 ° or less. It is desirably 60 ° or less.
【００１８】このようなメニスカスが形成されるのは、
回路層の下に形成される接続層の表面の酸化皮膜が極め
て薄いため、加熱接続時のＡｌ又はＡｌ合金の融液が容
易に濡れる。又上述のように基材を接続層、接続層と回
路層との間の外径寸法に差を持たせ、これらの層形成部
分の端が階段上又は連続的に裾を引いた形状となってい
ることもこれを促す要因の一つである。The reason why such a meniscus is formed is as follows.
Since the oxide film on the surface of the connection layer formed below the circuit layer is extremely thin, the melt of Al or Al alloy at the time of heating connection easily gets wet. Also, as described above, the base material has a difference in the outer diameter between the connection layer and the connection layer and the circuit layer, and the ends of these layer formation portions have a stepped or continuous hem shape. Is one of the factors that encourages this.
【００１９】このようにＡｌ又はＡｌ合金融液の流れた
形態の端部が回路層外周に形成されることによって、こ
れと接続層、回路層間の裾を引いた外寸配置との相剰効
果により、本発明の基板の熱サイクル負荷への信頼性は
より一層高くなっている。（熱応力の緩和）又半導体Ｉ
Ｃからの放熱についても、外周形態によってよりスムー
ズに行われることも確認された。（下に向かって広がっ
ていること）By forming the end of the form in which the Al or Al mixed liquid flows in the outer periphery of the circuit layer in this manner, a surplus effect between the end and the outer dimensions of the connection layer and the skirt between the circuit layers is reduced. As a result, the reliability of the substrate of the present invention to a thermal cycle load is further enhanced. (Relaxation of thermal stress) Also semiconductor I
It was also confirmed that the heat radiation from C was performed more smoothly depending on the outer peripheral form. (Spread downward)
【００２０】中でもその厚み方向で１／２以上の接続
層、回路層を形成する材質はＡｌの純度が高い程望まし
い。特に回路層表面部分は、Ａｌが９９．９％以上であ
るのが望ましい。これは、回路層上に接続される半導体
チップから生じる熱の分散を高め、同チップの昇温によ
る出力の低下や誤動作を回避するとともに高い電気伝導
性を確保するためである。Among them, the material forming the connection layer and the circuit layer having a thickness of 1/2 or more in the thickness direction is preferably as high as the purity of Al. In particular, it is desirable that Al is 99.9% or more in the surface portion of the circuit layer. This is to increase the dispersion of heat generated from the semiconductor chip connected to the circuit layer, to avoid a decrease in output and malfunction due to a rise in temperature of the chip, and to ensure high electrical conductivity.
【００２１】接続層のＡｌ量についても、同じ理由によ
つて望ましくは８０〜９９重量％さらに望ましくは９０
重量％以上とする。For the same reason, the Al content of the connection layer is preferably 80 to 99% by weight, more preferably 90 to 99% by weight.
% By weight or more.
【００２２】なおこれらの層中に含ませる合金成分とし
ては、ＭｇやＳｉ、Ｃｕ等がある。これらの役割は接続
層にあっては、主に基材の表面との間ならびに回路層と
の間の接続強度のレベルアップ、回路層にあっては主に
接続層との間の接続強度のレベルアップと、上記のメニ
スカスの適切な形状形成にある。例えば合金成分のマグ
ネシウムは、真空接合時のアルミニウム板材の表面の強
固な酸化膜を分解する効果があり、重量比で１％〜２０
％程度含まれるのが望ましい。なおこのマグネシウム
は、４００℃前後でアルミニウム板材の表面酸化膜と反
応して炉内へ放出され、試料中にはほとんど残らない。The alloy components contained in these layers include Mg, Si, Cu and the like. These roles play a major role in improving the connection strength between the connection layer and the surface of the substrate and between the circuit layer and the circuit layer. It is in the level-up and the proper shaping of the meniscus. For example, magnesium as an alloy component has an effect of decomposing a strong oxide film on the surface of an aluminum plate at the time of vacuum bonding, and is 1% to 20% by weight.
% Is desirable. The magnesium reacts with the surface oxide film of the aluminum plate at around 400 ° C. and is released into the furnace, and hardly remains in the sample.
【００２３】ただしＭｇの量が２０重量％を越えると、
接続時間の加熱によっても接続層中に少量残ったり、接
続層がより硬くなるため熱応力緩和効果が下がり易くな
る。However, if the amount of Mg exceeds 20% by weight,
Even if the connection time is heated, a small amount remains in the connection layer or the connection layer becomes harder, so that the effect of relaxing the thermal stress tends to decrease.
【００２４】また本発明の基板には、両主面とも以上述
べた回路層を接続した構造としてもよいが、放熱容量の
大きな半導体装置に実装される場合には、Ｓｉチップの
搭載される反対側の面に接続層を介して回路層に代えて
冷却構造体を接続することができる。The substrate of the present invention may have a structure in which the above-described circuit layers are connected to both main surfaces. However, when the substrate is mounted on a semiconductor device having a large heat dissipation capacity, the opposite side on which a Si chip is mounted is used. The cooling structure can be connected to the surface on the side instead of the circuit layer via the connection layer.
【００２５】この冷却構造体は、例えば放熱面積を稼ぐ
ために回路層と同じ素材をフィン状に加工して取り付け
たり、又例えばコンパクトなサイズであれば水冷式の高
熱伝導性金属からなる水の循環回路でもよいし、熱交換
の効率のよいヒートパイプを取りつけてもよい。This cooling structure may be formed, for example, by processing the same material as the circuit layer into a fin shape in order to increase the heat dissipation area, or, for example, if the size is compact, water made of a water-cooled high heat conductive metal may be used. A circulation circuit may be used, or a heat pipe with high heat exchange efficiency may be attached.
【００２６】次に、本発明の半導体装置用部材の製造方
法を説明する。本発明のセラミックスから成る絶縁基材
は、その熱伝導率が３０Ｗ／ｍＫ以上であるのが望まし
い。したがって窒化アルミニウム、窒化珪素、炭化珪
素、アルミナもしくはベリリアを主成分としたセラミッ
クスを用いるのが望ましい。それらの基材を用意し、ま
ずその主面の一方又は両方に回路層を形成するが、本発
明では基材の主面にまずＡｌを主成分とする層を形成す
る。この層は、本発明の回路基板では接続層の一部とな
るが、その通常の形成方法としては、真空蒸着法が代表
的な方法である。まず、母材であるセラミックスを蒸着
用真空チャンバー内に入れ、蒸着前にチャンバー内を真
空排気する。このときの真空の雰囲気圧力は１．３×１
０-3Ｐａ以下が好ましく、これ以上の圧力であると蒸着
中に母材から付着ガスが放出され、形成されるＡｌの結
晶粒径が０．１μｍ未満にまで小さくなる傾向にある。
この厚みは、回路層を接続後の接続層に空洞等の欠陥を
作らないためには、０．５〜２０μｍとするのが望まし
い。十分なアンカー効果を生み出すためにはその結晶粒
径を０．１〜１０μｍの範囲に制御する必要があり、真
空度は大きな要因となる。これは基材表面と蒸着された
結晶粒子との物理的な絡み合いを適切にし、蒸着層の基
材への接続強度を高めるためである。また、母材は蒸着
中特に加熱しなくても良いが、加熱しない場合でも蒸着
中に基材の温度が１００℃〜２００℃程度になるのが普
通である。なお真空蒸着法以外に、イオンスパッタリン
グ法を用いてもよい。また、有機溶媒中に分散させたＡ
ｌ粉末もしくはＡｌ，Ｍｇ混合粉末を、セラミックス基
材にスクリーン印刷法により印刷するか又は浸漬により
塗布した後、真空もしくは不活性又は還元雰囲気中で焼
結することによっても得ることもできる。なおスクリー
ン印刷法や浸漬塗布による場合にも、被塗布材中のＡｌ
を主成分とする金属粒子の平均粒径は、上記と同じ理由
で０．１〜１０μｍの範囲とするのが望ましい。Next, a method of manufacturing a member for a semiconductor device according to the present invention will be described. The insulating substrate made of the ceramic of the present invention preferably has a thermal conductivity of 30 W / mK or more. Therefore, it is desirable to use ceramics containing aluminum nitride, silicon nitride, silicon carbide, alumina or beryllia as a main component. These base materials are prepared, and a circuit layer is first formed on one or both of the main surfaces. In the present invention, first, a layer mainly containing Al is formed on the main surface of the base material. This layer becomes a part of the connection layer in the circuit board of the present invention, and a typical method of forming the layer is a vacuum deposition method. First, a ceramic as a base material is placed in a vacuum chamber for vapor deposition, and the inside of the chamber is evacuated before vapor deposition. The atmospheric pressure of the vacuum at this time is 1.3 × 1
The pressure is preferably 0 -3 Pa or less, and if the pressure is more than 0 -3 Pa, the deposition gas is released from the base material during the vapor deposition, and the crystal grain size of Al formed tends to be reduced to less than 0.1 μm.
The thickness is desirably 0.5 to 20 μm in order not to create a defect such as a cavity in the connection layer after the connection of the circuit layer. In order to produce a sufficient anchor effect, it is necessary to control the crystal grain size in the range of 0.1 to 10 μm, and the degree of vacuum is a major factor. This is to make the physical entanglement between the substrate surface and the deposited crystal particles appropriate, and to increase the connection strength of the deposited layer to the substrate. Further, the base material does not need to be particularly heated during the vapor deposition, but the temperature of the base material usually becomes about 100 ° C. to 200 ° C. during the vapor deposition even without heating. Note that an ion sputtering method may be used instead of the vacuum evaporation method. In addition, A dispersed in an organic solvent
Alternatively, the powder may be obtained by printing a powder or a mixed powder of Al and Mg on a ceramic substrate by a screen printing method or applying the powder by immersion, followed by sintering in a vacuum or inert or reducing atmosphere. In the case of screen printing or dip coating, the Al
It is desirable that the average particle size of the metal particles containing as a main component is in the range of 0.1 to 10 μm for the same reason as described above.
【００２７】上記接続層を形成する基材の表面は、その
表面粗さをＪＩＳ規定のＲmaxで０．１〜２０μｍの範
囲にコントロールするのが好ましい。表面粗さがＲmax
で０．１μｍより小さいと、十分なアンカー効果を得難
くなる。また、Ｒmaxが２０μｍより粗いと吸着ガスが
多くなり、薄膜層形成時に余分なガスが放出され１．３
×１０-3Ｐａ以下の圧力が得られない場合があり、その
結果十分なアンカー効果が得られず接続強度が低下し易
い。It is preferable to control the surface roughness of the surface of the base material on which the connection layer is formed within a range of 0.1 to 20 μm in terms of Rmax specified by JIS. Surface roughness is Rmax
If it is smaller than 0.1 μm, it is difficult to obtain a sufficient anchor effect. On the other hand, if Rmax is coarser than 20 μm, the amount of adsorbed gas is increased, and an extra gas is released during the formation of the thin film layer.
In some cases, a pressure of × 10 −3 Pa or less cannot be obtained, and as a result, a sufficient anchor effect cannot be obtained, and the connection strength tends to decrease.
【００２８】本発明の回路基板の接続層は、以上の様な
基材上の第一の接続層を形成した後、直接その上に回路
層を形成してもよい。この場合第一の接続層が純度の高
いＡｌであれば、この層による熱抵抗が最も小さくな
り、その点では望ましい。しかしながら回路層と基材と
の間の接続後の強度を考えると、それらの間に第二の接
続層として予めＡｌとの合金化により、同層自体の融点
を下げる合金成分を含んだ層を介挿するのが望ましい。
これによって例えば第一の接続層と回路層が純度の高い
Ａｌの場合、回路層接続時の温度が下げられるため、両
層への合金成分の拡散が抑えられ、それによる両層の熱
伝導性の低下が避けられる。なお、この場合の第二の接
続層の厚みは以下に述べる回路層形成（焼成）前の段階
で２０〜１００μｍとするのが望ましい。厚みが２０μ
ｍ未満では接合に十分な液相が得られ難く接続層中に欠
陥が生じ易くなる。また、純アルミニウム板材の端部全
周にわたってメニスカスが形成され難いともある。厚み
が１００μｍ以上になると、余分な液層が発生し、アル
ミニウム板材の再加工が必要となる場合がある。The connection layer of the circuit board of the present invention may be such that the circuit layer is formed directly on the first connection layer on the substrate as described above. In this case, if the first connection layer is made of high-purity Al, the thermal resistance of this layer is minimized, which is desirable. However, considering the strength after connection between the circuit layer and the base material, a layer containing an alloy component that lowers the melting point of the same layer itself by alloying with Al in advance as a second connection layer is considered between them. It is desirable to interpose.
Thus, for example, when the first connection layer and the circuit layer are made of high-purity Al, the temperature at the time of connection of the circuit layer is reduced, so that diffusion of alloy components into both layers is suppressed, and the thermal conductivity of both layers is thereby reduced. Is avoided. The thickness of the second connection layer in this case is desirably 20 to 100 μm before the formation (firing) of the circuit layer described below. 20μ thickness
If it is less than m, it is difficult to obtain a liquid phase sufficient for bonding, and defects tend to occur in the connection layer. In addition, a meniscus may not be easily formed over the entire periphery of the end of the pure aluminum plate. When the thickness is 100 μm or more, an extra liquid layer is generated, and it may be necessary to rework the aluminum plate.
【００２９】次に、少なくとも薄膜形成パターンよりも
小さい主面外寸形状を持ったＡｌ又はＡｌ合金からなる
金属素材、例えばＡｌ−Ｓｉ−Ｍｇ系のろう材を置き、
その上に少なくともろう材パターンと同じかそれよりも
小さい形状を持った純アルミニウム又はアルミニウム合
金の回路層形成用の金属素材、例えば９９．９％以上の
純度のアルミニウム素材を載せて、回路形成用の素材の
融点よりも低く、ろう材の融点よりも高い温度でかつ好
ましくは１０-5Ｔｏｒｒ以下の真空度で焼成し接合す
る。この場合のろう材は溶融して接続層の一部となる。Next, a metal material made of Al or an Al alloy having a main surface outer dimension smaller than at least the thin film forming pattern, for example, an Al—Si—Mg brazing material is placed.
A metal material for forming a circuit layer of pure aluminum or an aluminum alloy having a shape at least equal to or smaller than the brazing material pattern, for example, an aluminum material having a purity of 99.9% or more is placed on the metal material for forming a circuit. And baked at a temperature lower than the melting point of the material and higher than the melting point of the brazing material, and preferably at a degree of vacuum of 10 -5 Torr or less. In this case, the brazing material melts and becomes a part of the connection layer.
【００３０】薄膜形成パターンよりもろう材や純アルミ
ニウム板材を小さくするのは、接合時の液層によって、
前述のように純アルミニウム板材の端部全周に容易にメ
ニスカスを形成するためである。このメニスカス構造に
よって、純アルミニウム板材端部の加熱接続後の残留熱
応力を大幅に減少させることが出来る。また半導体装置
に組み込まれた後の実動時の熱サイクルによる衝撃にも
極めて強くなる。The reason why the brazing material or the pure aluminum plate material is made smaller than the thin film forming pattern depends on the liquid layer at the time of bonding.
As described above, this is because a meniscus is easily formed around the entire edge of the pure aluminum plate. With this meniscus structure, it is possible to greatly reduce the residual thermal stress after heating and connecting the end of the pure aluminum plate. In addition, it is extremely resistant to shock due to a thermal cycle during actual operation after being incorporated in a semiconductor device.
【００３１】尚、上記接続加熱の際に、必要により、例
えば炭素質、アルミナ質、窒化アルミニウム質等の耐火
物を素材とする冶具を用いて双方の仮固定を行うととも
に、更に必要であれば、両者を積層したセット上に適当
な荷重をかけてもよい。In addition, at the time of the above-mentioned connection heating, if necessary, the two parts are temporarily fixed using a jig made of a refractory material such as carbonaceous material, alumina material or aluminum nitride material, and if necessary. Alternatively, an appropriate load may be applied to a set in which both are laminated.
【００３２】上記接続において、例えばＡｌ−Ｓｉ−Ｍ
ｇろう材を用いて接続する代わりにに、工程削減のた
め、純アルミニウムと例えばＡｌ−Ｓｉ−Ｍｇ系のよう
なＡｌろう材を圧延したクラッド材（ブレージングシー
ト）を用いてもよい。また、回路形成用となるＡｌ又は
Ａｌ合金薄板材と反対側のＡｌ又はＡｌ合金材は、板状
であってもよいが、既に述べたようにより放熱効率を向
上させるために放熱フィン加工を施してあってもよい。
なおこの部分については、前述のようにコンパクトな冷
却構造体が配置されれば、いかなるものでも構わない。In the above connection, for example, Al-Si-M
Instead of the connection using the g brazing material, a clad material (brazing sheet) in which pure aluminum and an Al brazing material such as an Al—Si—Mg material are rolled may be used in order to reduce the number of processes. Further, the Al or Al alloy material on the opposite side to the Al or Al alloy thin sheet material for forming a circuit may be plate-shaped, but as described above, heat-radiating fin processing is performed to improve heat radiation efficiency. May be.
This portion may be of any type as long as a compact cooling structure is arranged as described above.
【００３３】[0033]
【実施例】実施例１ 主成分粉末として、平均粒径１．２μｍのＡｌＮ粉末と
平均粒径０．６μｍのＹ2Ｏ3粉及び平均粒径０．３μｍ
のＣａＯ粉末を、それぞれ９７重量％、１．５重量％、
及び１．５重量％となるよう秤取し、エタノール溶媒中
ボールミルにて２４時間均一混合し、焼結助剤がＹ2Ｏ3
−ＣａＯからなる混合粉末を得た。更に、これらの混合
粉末１００重量部に対しバインダーとしてＰＶＢを１０
重量部加え、スラリー化した。このスラリーの一部を噴
霧乾燥し、粉末成形プレスにて幅６３ｍｍ×厚さ：０．
７９ｍｍ×長さ：９４ｍｍの大きさに成形した。これら
の成形体を、窒素雰囲気中にて１７００℃で５時間、焼
結した。この焼結体の相対密度（理論密度を１００％と
したとき水中法で測定したときの実測密度の比率）は９
９％であり、表面には実用上問題となるような空孔等の
欠陥は無かった。またレーザーフラッシュ法で測定した
熱伝導率は１５０ないし１６０Ｗ／ｍＫであった。EXAMPLES Example 1 AlN powder having an average particle diameter of 1.2 μm, Y 2 O 3 powder having an average particle diameter of 0.6 μm, and an average particle diameter of 0.3 μm were used as main component powders.
Of 97% by weight, 1.5% by weight, respectively,
And were weighed so as to be 1.5 wt%, 24 hours were uniformly mixed in an ethanol solvent in a ball mill, sintering aid Y 2 O 3
-A mixed powder consisting of CaO was obtained. Further, PVB was added as a binder to 100 parts by weight of these mixed powders.
A part by weight was added to form a slurry. A part of this slurry was spray-dried, and the width was 63 mm × thickness: 0.
It was molded to a size of 79 mm x length: 94 mm. These compacts were sintered at 1700 ° C. for 5 hours in a nitrogen atmosphere. The relative density of this sintered body (the ratio of the measured density measured by the underwater method when the theoretical density is 100%) is 9
9%, and there were no defects such as vacancies on the surface that would cause a practical problem. The thermal conductivity measured by a laser flash method was 150 to 160 W / mK.
【００３４】以上の手順を経て得られたＡｌＮ焼結体
を、長さ７５ｍｍ、幅５０ｍｍ、厚み０．６３５ｍｍの
基材に仕上げ加工した。また別途Ｓｉ3Ｎ4，ＳｉＣを主
成分とするセラミックス素材から、同じ形状の基材を切
り出した。なおＳｉＣを主成分とする基材については、
その全表面を電気的に絶縁するために、予め窒化層を形
成した。これらの基材の熱伝導率は、それぞれ順にＷ／
ｍ・Ｋ単位で１００および２００であった。The AlN sintered body obtained through the above procedure was finished into a base material having a length of 75 mm, a width of 50 mm and a thickness of 0.635 mm. Separately, a base material having the same shape was cut out from a ceramic material containing Si 3 N 4 and SiC as main components. In addition, about the base material which has SiC as a main component,
In order to electrically insulate the entire surface, a nitride layer was formed in advance. The thermal conductivity of these substrates is W /
They were 100 and 200 in mK units.
【００３５】これらの基材上に、表１に記載の素材の組
合せおよび形成条件にて、まずＡｌを主成分とする接続
層を形成した。以降各試料とも３０個ずつ作製した。First, a connection layer containing Al as a main component was formed on these substrates under the combinations of materials shown in Table 1 and the forming conditions. Thereafter, 30 samples were prepared for each sample.
【００３６】表中基材欄のＲmax は、基材の主面のＪＩ
Ｓに基づく表面粗さである。接続層１（第一の接続層）
および接続層２（第二の接続層）の形成欄の材質の内、
９９．９Ａｌは、Ａｌを９９．９重量％含む純Ａｌ材か
らなる箔、Ｍ５は、Ｍｇを５重量％含み残部Ａｌからな
る箔、Ｍ５Ｓ１０は、Ｍｇを５重量％、Ｓｉを１０重量
％含み、残部Ａｌからなる箔である。Ｍ５＋Ｍ５Ｓ１０
は、Ｍ５の箔とＭ５Ｓ１０の箔とを圧着一体化したろう
材（ブレージングシート）である。同様にＭ０．５，Ｍ
１，Ｓ１０等のＭおよびＳは、合金成分がＭｇおよびＳ
ｉであり、その後の数値はそれらの含有量（重量％）を
示す。ΔＬは、接続層の主面が基材のそれよりどれだけ
小さいか、その寸法差を示す。例えば試料１では、基材
主面の長さ方向の寸法が、７５ｍｍであるから、その接
続層１と２の同じ方向は、それより５００μｍ（０．５
ｍｍ）短い７４．５ｍｍである。接続層の形成温度は、
蒸発源の温度ではなく、蒸着される基材表面の温度であ
る。形成の圧力は、形成チャンバー内の真空雰囲気圧力
である。形成膜厚は、基材表面に析出堆積した層の厚み
であり、結晶粒径は、その層内のＡｌを主成分とする結
晶の平均粒径である（試料毎に各３個の試片の表面を走
査型電子顕微鏡で観察）。Rmax in the base material column in the table is the JI of the main surface of the base material.
This is the surface roughness based on S. Connection layer 1 (first connection layer)
And among the materials in the column for forming the connection layer 2 (second connection layer),
99.9Al is a foil made of a pure Al material containing 99.9% by weight of Al, M5 is a foil made of 5% by weight of Mg and the balance is Al, and M5S10 is a foil of 5% by weight of Mg and 10% by weight of Si. , The remaining portion being Al. M5 + M5S10
Is a brazing material (brazing sheet) in which a foil of M5 and a foil of M5S10 are pressure-bonded and integrated. Similarly, M0.5, M
M and S such as 1, S10, etc. are alloy components of Mg and S
i, and the following numerical values indicate their content (% by weight). ΔL indicates how much the main surface of the connection layer is smaller than that of the base material, that is, its dimensional difference. For example, in the sample 1, since the dimension in the longitudinal direction of the main surface of the base material is 75 mm, the same direction of the connection layers 1 and 2 is 500 μm (0.5
mm) 74.5 mm short. The formation temperature of the connection layer is
It is not the temperature of the evaporation source but the temperature of the surface of the substrate to be deposited. The forming pressure is a vacuum atmosphere pressure in the forming chamber. The formed film thickness is the thickness of the layer deposited and deposited on the surface of the base material, and the crystal grain size is the average grain size of the crystal mainly composed of Al in the layer (three specimens for each sample). Is observed with a scanning electron microscope).
【００３７】試料２３は、第一・第二の接続層を表に付
記した条件にて、試料１と同じ材質のアルミニウムペー
ストを積層印刷塗布し、焼き付けたものである。試料２
４のＳｉＮ，ＳｉＣはそれぞれの基材が、前記のＳｉ3
Ｎ4およびＳｉＣセラミックスであることを示す。試料
２６は、試料１と同じＡｌＮ基材の主面を予め苛性ソー
ダに浸漬して、厚み１０μｍアルミナの層を形成したも
のである。Sample 23 is obtained by printing and baking an aluminum paste of the same material as that of sample 1 under the conditions described in the table for the first and second connection layers. Sample 2
4 of SiN, SiC has respective substrate, wherein the Si 3
It indicates N 4 and SiC ceramics. In sample 26, the same main surface of the AlN substrate as in sample 1 was immersed in caustic soda in advance to form a 10 μm-thick alumina layer.
【００３８】[0038]
【表１】 [Table 1]
【００３９】[0039]
【表２】 [Table 2]
【００４０】試料２７は、接続層１を付与せず、基材上
に直接接続層２を付与したもの、試料２８は、接続層１
にＭｇを５重量％、残部Ａｌの組成の合金を、試料２９
は、Ｓｉを１０重量％、残部Ａｌの組成の合金をそれぞ
れ試料４と同じ条件で真空蒸着し、その後試料９と同じ
接続層を付与したものである。The sample 27 was obtained by directly providing the connection layer 2 on the substrate without providing the connection layer 1, and the sample 28 was obtained by providing the connection layer 1
An alloy having a composition of 5% by weight of Mg and the balance of Al
Is obtained by vacuum-depositing an alloy having a composition of 10% by weight of Si and the balance of Al under the same conditions as in Sample 4, and then providing the same connection layer as in Sample 9.
【００４１】次いで試料１から２９の各種接続層を形成
した試片の第二の接続層の主面上に、導体回路層（回路
層）を形成した。まず第二の接続層の主面に比べ長手・
幅両方向とも５００μｍ（０．５ｍｍ）短く、純度が９
９．９％、厚み４００μｍ（０．４ｍｍ）の純Ａｌの箔
を用意した。これを各試料の第二の接続層の上に載せ、
１．４×１０-3Ｐａの真空中、試料１〜６については６
５０℃、試料７以降ついては６００℃にて３０分加熱し
て、回路層を形成した。予め回路層の金属泊の主面外周
サイズと接続層のそれとの寸法差は、長手方向・幅方向
ともそれらの両端でそれぞれ２５０μｍ（０．２５ｍ
ｍ）ずつほぼ均等に配分されるように配置し（つまり長
手方向・幅方向とも外周全長で接続層のそれに対し５０
０μｍ小さいサイズ）、上部から位置決め冶具を兼ねた
グラファイトのブロックにて、５０ｇ／ｃｍ2の荷重を
かけ、回路層の位置ずれを防止した。その結果当初配置
位置に対し、長手方向・幅方向ともずれは無かった。ま
た回路層の厚みは、当初と変わらなかった。Next, a conductor circuit layer (circuit layer) was formed on the main surface of the second connection layer of each of the test pieces on which the various connection layers of Samples 1 to 29 were formed. First, compared to the main surface of the second connection layer,
500 μm (0.5 mm) shorter in both width directions, purity 9
A 9.9% pure Al foil having a thickness of 400 μm (0.4 mm) was prepared. Put this on the second connection layer of each sample,
In a vacuum of 1.4 × 10 −3 Pa, 6
The circuit layer was formed by heating at 50 ° C., and the sample 7 and thereafter at 600 ° C. for 30 minutes. The dimensional difference between the outer circumference of the main surface of the metal layer of the circuit layer and that of the connection layer is 250 μm (0.25 m) at both ends in both the longitudinal and width directions.
m) so as to be distributed approximately evenly at a time (that is, 50% of the length of the connection layer in the longitudinal direction and the width direction with respect to that of the connection layer).
A load of 50 g / cm 2 was applied from above with a graphite block serving also as a positioning jig to prevent the circuit layer from shifting. As a result, there was no shift in the longitudinal direction and the width direction from the initial arrangement position. The thickness of the circuit layer was not different from the initial one.
【００４２】接続後の各試料は、回路層から接続層の外
周に至るメニスカスの裾の部分の接続層主面に対する角
度を測った。各試料とも５個の平均を採った。その結果
試料２６，２７は、ほぼ９０゜、試料１１では７０゜で
あり、それ以外の試料では５０〜６０゜であった。次い
で回路層および接続層の露呈面全面に、無電解めっき法
により厚み２μｍニッケル（Ｎｉ）めっき層を形成し
た。For each sample after connection, the angle of the bottom of the meniscus from the circuit layer to the outer periphery of the connection layer was measured with respect to the main surface of the connection layer. The average of five samples was taken for each sample. As a result, Samples 26 and 27 were almost 90 °, Sample 11 was 70 °, and the other samples were 50 to 60 °. Next, a nickel (Ni) plating layer having a thickness of 2 μm was formed on the entire exposed surfaces of the circuit layer and the connection layer by an electroless plating method.
【００４３】このアセンブリーにて各試料の回路層主面
と基材との接続状況を超音波探傷した（全数）。その際
試料の回路層側からその全面にわたって探触子を走査
し、基材との界面からのエコーの強さの分布を画像処理
し、標準試片のそれと比較することによって、健全な接
続面積の割合を確認した（表２の接続面積率の値、各試
料とも３０個の平均）。なお試料１と６の接続層１の上
に試料７と同じ接続層２を積層し、上記と同じ回路層を
接続したところ、これらの試料の接続面積率は９５％程
度であった。With this assembly, the connection status between the main surface of the circuit layer of each sample and the substrate was subjected to ultrasonic flaw detection (total number). At this time, the probe is scanned from the circuit layer side of the sample over the entire surface, the distribution of the intensity of the echo from the interface with the base material is image-processed, and compared with that of the standard sample, the sound connection area (The value of the connection area ratio in Table 2, the average of 30 samples for each sample). When the same connection layer 2 as that of the sample 7 was laminated on the connection layer 1 of the samples 1 and 6 and the same circuit layer was connected, the connection area ratio of these samples was about 95%.
【００４４】さらに各試料から３個ずつ抜き取り、アセ
ンブリーの基材から回路層に至る断面を研磨し、１００
０倍の走査型電子顕微鏡によって、同部分の欠陥の有無
を確認した。また、合金成分及び酸素の分布状態を質量
分析法による元素分析およびＴＥＭ像の観察によって確
認した。以上の結果は下記のとおりであった。Further, three samples were taken out from each sample, and the cross section from the base material of the assembly to the circuit layer was polished,
The presence or absence of a defect in the same portion was confirmed by a scanning electron microscope of 0 magnification. The distribution states of the alloy components and oxygen were confirmed by elemental analysis by mass spectrometry and observation of a TEM image. The above results were as follows.
【００４５】（１）接続層１を形成しなかった試料２７
では、各接続界面に微細なピンホールがみられたが、基
材に酸化層を形成した試料２６も含め、それ以外の試料
には、クラックやピンホール等の欠陥は、確認されなか
った。(1) Sample 27 without connection layer 1
In this example, fine pinholes were observed at each connection interface, but defects such as cracks and pinholes were not observed in samples other than Sample 26 including an oxide layer formed on the substrate.
【００４６】（２）試料２６では接続層１と基材との界
面付近に多量の酸素が確認されたが、本発明の試料で
は、ほとんど確認されなかった。(2) In sample 26, a large amount of oxygen was observed near the interface between the connection layer 1 and the substrate, but almost no oxygen was observed in the sample of the present invention.
【００４７】（３）接続層が二層形成された試料では、
回路層が加熱接続されると、接続層１に接続層２の合金
成分であるＳｉが拡散していた。なお接続層のＭｇ成分
は、接続時に揮散し、ほとんど確認されなかった。また
この成分は、接続層２から回路層にも拡散していたが、
回路層の表面に向かって漸減しており、それらが拡散し
た厚みは最大で回路層の厚みの１／２未満であった。(3) In a sample in which two connection layers are formed,
When the circuit layer was heated and connected, Si as an alloy component of the connection layer 2 was diffused into the connection layer 1. The Mg component in the connection layer volatilized during connection, and was hardly observed. This component was also diffused from the connection layer 2 to the circuit layer,
The thickness gradually decreased toward the surface of the circuit layer, and the thickness at which they diffused was at most less than half the thickness of the circuit layer.
【００４８】その後回路層の主面にＰｂ−Ｓｎ系共晶半
田にて、長さ・幅とも１ｍｍで、厚みが０．３ｍｍのシ
リコン（Ｓｉ）半導体チップをダイボンディングし半導
体装置を作製した。この状態で各試料とも１０台ずつ用
意して、冷熱サイクル試験を行った。それらの結果を表
２の該当欄に示す。なお冷熱サイクル試験は、−５５℃
で３０分保持後１２５℃で３０分保持する温度サイクル
を１サイクルとし、試料に損傷が生じるまでこれを繰り
返す手順にて３５００回まで行った。なお表２の冷熱サ
イクル欄に記載の損傷の生じたサイクル数は、各試料と
も１０台の内の最短回数のものの回数値とした。なお
「＞３５００」と記載のものは、３５００回まで問題の
なかったものである。接続面積率と冷熱サイクルの結果
ならびにその結果からの判明点について表２にまとめ
た。Thereafter, a silicon (Si) semiconductor chip having a length and width of 1 mm and a thickness of 0.3 mm was die-bonded to the main surface of the circuit layer with a Pb-Sn eutectic solder to produce a semiconductor device. In this state, 10 samples were prepared for each sample, and a cooling / heating cycle test was performed. The results are shown in the corresponding columns of Table 2. The cooling / heating cycle test was performed at -55 ° C.
The temperature cycle of holding at 125 ° C. for 30 minutes after holding for 30 minutes was one cycle, and this was repeated up to 3,500 times until the sample was damaged. In addition, the number of cycles in which damage occurred as described in the column of the cooling / heating cycle in Table 2 was the frequency value of the shortest number of the ten samples for each sample. Those described as ">3500" have no problem up to 3500 times. Table 2 summarizes the results of the connection area ratio and the cooling / heating cycle and the points found from the results.
【００４９】[0049]
【表３】 [Table 3]
【００５０】実施例２ 実施例１の試料４，９および２４と同じ基材を用い、そ
の上下両主面とも実施例１と同様の構成の接続層を形成
した（それぞれの接続層１と２の形成方法は、実施例１
に示した手順と同じ）。Example 2 Using the same base material as the samples 4, 9 and 24 of Example 1, connection layers having the same structure as that of Example 1 were formed on both upper and lower main surfaces thereof (the respective connection layers 1 and 2). The method of forming is described in Example 1.
Same as the procedure shown in).
【００５１】又別途実施例１と同じサイズの回路層形成
用のＡｌ金属箔と、同じ材質のフィンとベース板を冷却
構造体として準備した。これらを接続層を形成した一方
の主面側には、実施例１と同様にして回路層とＳｉ半導
体チップを接続し、他方の主面側には冷却構造体を接続
した。このようなフィン又はベース板付きの半導体装置
をそれぞれの基材試料毎に１０台ずつ作製した。その断
面構造を図１（イ）（ロ）に模式的に示す。（イ）はフ
ィン付の例で、（ロ）はベース板付の例である。Separately, an Al metal foil for forming a circuit layer having the same size as in Example 1, fins and a base plate of the same material were prepared as a cooling structure. The circuit layer and the Si semiconductor chip were connected to one main surface side on which the connection layer was formed in the same manner as in Example 1, and a cooling structure was connected to the other main surface side. Ten such semiconductor devices each having a fin or a base plate were manufactured for each base material sample. The cross-sectional structure is schematically shown in FIGS. (A) is an example with a fin, and (B) is an example with a base plate.
【００５２】図１で１はセラミックス絶縁基材、２は接
続層、３は回路層、４はＳｉ半導体チップ、５は冷却構
造体である。In FIG. 1, 1 is a ceramic insulating substrate, 2 is a connection layer, 3 is a circuit layer, 4 is a Si semiconductor chip, and 5 is a cooling structure.
【００５３】なお、同図（イ）、（ロ）において、２つ
の接続層の断面の外側形状とし、基材主面と同層との間
で形成されるメニスカスの角度を８０°以下に制御する
ため、図に記載されたように接続層の中間に純アルミニ
ウム（Ａｌ）の層を残すようにした。具体的には純Ａｌ
のシートの両側に、融点が純Ａｌよりも低いＡｌ−Ｓｉ
−Ｍｇ系合金（試料４の接続層２に同じ）からなるシー
トを圧延接着したブレージングシートロウ材を使い、こ
れを基材と冷却構造体の間に挟んで、Ａｌ−Ｓｉ−Ｍｇ
系ロウ材の融点と純Ａｌとの融点の間の温度に加熱し
て、これらを接続した。その結果図に示すように、基材
と冷却構造体の間の接続層によって形成されるメニスカ
スの基材面とのなす角度は、６０°以下となった。なお
この角度を８０°以下に制御するためには、図２に示す
ように予め冷却構造体の面に堀状の溝６を設けてもよい
ことも確認された。この場合には、溝６の外縁は、基板
を上面から見た時に上部の回路層の外縁よりも内側に入
るようにする。またこの溝は、溶融したロウ材が冷却構
造体の面上に広がらないようにして、上記同様基材との
メニスカス角度を制御する働きをする。したがって、形
成する溝の内容量は、適正に制御する必要がある。In FIGS. 7A and 7B, the outer shape of the cross section of the two connection layers is set, and the angle of the meniscus formed between the main surface of the base material and the same layer is controlled to 80 ° or less. To this end, a layer of pure aluminum (Al) was left in the middle of the connection layer as shown in the figure. Specifically, pure Al
Al-Si with melting point lower than pure Al
A brazing sheet brazing material obtained by rolling and bonding a sheet made of a Mg-based alloy (same as the connection layer 2 of the sample 4), and sandwiching this between a base material and a cooling structure to form an Al-Si-Mg
These were heated to a temperature between the melting point of the brazing material and the melting point of pure Al, and these were connected. As a result, as shown in the figure, the angle between the meniscus formed by the connection layer between the base material and the cooling structure and the base material surface was 60 ° or less. It was also confirmed that a moat-shaped groove 6 may be provided in advance on the surface of the cooling structure as shown in FIG. 2 in order to control this angle to 80 ° or less. In this case, the outer edge of the groove 6 is located inside the outer edge of the upper circuit layer when the substrate is viewed from above. The grooves also serve to control the meniscus angle with the substrate as described above, by preventing the molten brazing material from spreading on the surface of the cooling structure. Therefore, it is necessary to appropriately control the capacity of the groove to be formed.
【００５４】冷却構造体の絶縁基板との接続面の外寸
は、長さが８０ｍｍ、幅が６０ｍｍであり、高さの外寸
はいずれの冷却構造体も２３ｍｍとした。The external dimensions of the connecting surface of the cooling structure with the insulating substrate were 80 mm in length and 60 mm in width, and the external dimensions of the height were 23 mm for all the cooling structures.
【００５５】フィン形状のものは、図１のｔが３ｍｍ、
Ｔが２０ｍｍ、フィンの部分の配置ピッチｌ，ｌ′は、
いずれも２．５ｍｍとした。In the case of the fin shape, t in FIG.
T is 20 mm, and the arrangement pitch l, l ′ of the fin portion is
Each was 2.5 mm.
【００５６】その後図示しないが、このアセンブリーを
ハウジングし冷却構造体側に水冷ジャケットを取付けた
パワーモジュールを作製して、１２時間実動させ、その
際のＳｉ半導体チップの表面温度を同チップに熱電対を
接触させて比較した。なお室温は２５℃である。その結
果表３の結果を得た。（１０台での平均）Thereafter, although not shown, a power module having this assembly as a housing and a water cooling jacket attached to the cooling structure side was manufactured and operated for 12 hours, and the surface temperature of the Si semiconductor chip at that time was measured by a thermocouple. Were brought into contact with each other for comparison. The room temperature is 25 ° C. As a result, the results shown in Table 3 were obtained. (Average of 10 units)
【００５７】[0057]
【表４】 [Table 4]
【００５８】なお以上のアセンブリーを実施例１と同じ
ヒートサイクル試験をかけたところ、いずれも３５００
回のサイクル負荷後の損傷は確認されなかった。When the above assembly was subjected to the same heat cycle test as in Example 1, all were subjected to 3500
No damage was observed after one cycle load.
【００５９】以上の様に本発明の接続層構成によってＳ
ｉ半導体チップの実装と同時に絶縁基板の他方の面にＡ
ｌを主成分とする冷却構造体を高い信頼性で装着するこ
とができることが分かった。As described above, according to the connection layer structure of the present invention, S
i At the same time as the mounting of the semiconductor chip,
It has been found that the cooling structure mainly composed of 1 can be mounted with high reliability.
【００６０】[0060]
【発明の効果】以上詳述したように、本発明の接続構造
によって過酷なパワーモジュールの実動条件下において
も、従来になく高い寿命信頼性のセラミックス絶縁基板
を得ることができる。As described above in detail, the connection structure of the present invention makes it possible to obtain a ceramic insulating substrate having a longer life reliability than ever before even under severe operating conditions of a power module.
【図１】半導体装置の模式図で、（イ）はフィン付の例
で、（ロ）はベース板付の例である。FIGS. 1A and 1B are schematic views of a semiconductor device, wherein FIG. 1A is an example with a fin, and FIG. 1B is an example with a base plate.
【図２】図１のものに溝を設けた例である。FIG. 2 is an example in which a groove is provided in FIG.
１ セラミックス絶縁基板 ２ 接続層 ３ 回路層 ４ Ｓｉ半導体チップ ５ 冷却構造体 ６ 溝 REFERENCE SIGNS LIST 1 ceramic insulating substrate 2 connection layer 3 circuit layer 4 Si semiconductor chip 5 cooling structure 6 groove
───────────────────────────────────────────────────── フロントページの続き (72)発明者 桧垣 賢次郎 兵庫県伊丹市昆陽北一丁目１番１号 住友 電気工業株式会社伊丹製作所内 Ｆターム(参考） 5F036 AA01 BC06 BD03 BD14 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kenjiro Higaki 1-1-1 Kunyokita, Itami-shi, Hyogo F-term in Sumitomo Electric Industries, Ltd. Itami Works (reference) 5F036 AA01 BC06 BD03 BD14
Claims (7)
たは両方の主面上に、 Ａｌおよび／又は、Ａｌとの合金化によりその融点を下
げる合金成分とを含む接続層と、Ａｌとその合金成分と
を含み、接続層よりもＡｌ量の多い回路層とが、順次形
成されており、 回路層の側面全周の端が、接続層の側面全周の端よりも
５０μｍ以上内側になるように配置されているととも
に、 回路層中には接続層の合金成分が拡散しており、その合
金成分の量が、表面に向かって減少している半導体用絶
縁基板。1. A connection layer containing, on one or both main surfaces of an insulating base material made of ceramics, Al and / or an alloy component for lowering the melting point thereof by alloying with Al; And a circuit layer having a larger amount of Al than the connection layer is sequentially formed, and the end of the entire side surface of the circuit layer is located at least 50 μm inside the end of the entire side surface of the connection layer. An insulating substrate for a semiconductor in which an alloy component of a connection layer is diffused in a circuit layer while being disposed, and an amount of the alloy component decreases toward a surface.
金成分を含むメニスカスが形成されている請求項１に記
載の半導体装置用絶縁基板。2. The insulating substrate for a semiconductor device according to claim 1, wherein a meniscus containing Al and its alloy component is formed all around the side surface of the circuit layer.
続層と回路層が接続され、他方の主面上に、前記接続層
を介して冷却構造体が接続されている請求項１または２
に記載の半導体装置用絶縁基板。3. The cooling structure according to claim 1, wherein the connection layer and the circuit layer are connected to one main surface of the insulating base material, and a cooling structure is connected to the other main surface via the connection layer. 1 or 2
4. The insulating substrate for a semiconductor device according to claim 1.
化珪素、炭化珪素を主成分としたセラミックスである請
求項１ないし３のいずれかに記載の半導体装置用絶縁基
板。4. The insulating substrate for a semiconductor device according to claim 1, wherein said insulating base is a ceramic containing aluminum nitride, silicon nitride, and silicon carbide as main components.
縁基板を用いた半導体装置。5. A semiconductor device using the insulating substrate according to claim 1.
基材上に形成される接続層と回路層の原料であるＡｌ、
Ａｌとの合金化によりその融点を下げる合金成分を含む
金属素材群とを準備する工程と、 絶縁基材の片方または両方の主面上に、金属素材群の内
の少なくとも１種を含み、接続層を形成する工程と、 接続層を構成する金属素材よりもＡｌ量が多く、主面外
寸が接続層のそれよりも全周にわたって５０μｍ以上小
さい回路層の素材を準備する工程と、 この回路層の素材を接続層上に配置し、非酸化性雰囲気
中、接続層を構成する金属の融点以上、回路層の素材の
融点以下の温度下で加熱して回路層を形成する工程とを
含む半導体用絶縁基板の製造方法。6. An insulating base material made of ceramics, and Al, which is a raw material of a connection layer and a circuit layer formed on the insulating base material,
Preparing a metal material group containing an alloy component that lowers its melting point by alloying with Al; and connecting at least one of the metal material groups to one or both main surfaces of the insulating base material, A step of forming a layer; a step of preparing a circuit layer material having a larger amount of Al than the metal material constituting the connection layer and having a main surface outer dimension smaller than that of the connection layer by 50 μm or more over the entire circumference; Arranging the material of the layer on the connection layer, and heating in a non-oxidizing atmosphere at a temperature equal to or higher than the melting point of the metal constituting the connection layer and equal to or lower than the melting point of the material of the circuit layer to form a circuit layer. A method for manufacturing an insulating substrate for a semiconductor.
層と、第一の接続層よりも合金成分の多い第二の接続層
とを形成する工程である請求項６記載の半導体装置用絶
縁基板の製造方法。7. The step of forming the connection layer includes the steps of: a first connection layer including at least one of the metal material groups; and a second connection layer having a larger alloy component than the first connection layer. 7. The method for manufacturing an insulating substrate for a semiconductor device according to claim 6, wherein the step of forming the insulating substrate is performed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35212399A JP2001168250A (en) | 1999-12-10 | 1999-12-10 | Insulating substrate for semiconductor device, semiconductor device using that and manufacturing method of substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35212399A JP2001168250A (en) | 1999-12-10 | 1999-12-10 | Insulating substrate for semiconductor device, semiconductor device using that and manufacturing method of substrate |
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|---|---|
| JP2001168250A true JP2001168250A (en) | 2001-06-22 |
Family
ID=18421942
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35212399A Pending JP2001168250A (en) | 1999-12-10 | 1999-12-10 | Insulating substrate for semiconductor device, semiconductor device using that and manufacturing method of substrate |
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| JP (1) | JP2001168250A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003090277A1 (en) * | 2002-04-19 | 2003-10-30 | Mitsubishi Materials Corporation | Circuit board, process for producing the same and power module |
| KR20120062751A (en) * | 2009-09-09 | 2012-06-14 | 미쓰비시 마테리알 가부시키가이샤 | Method for producing substrate for power module with heat sink, substrate for power module with heat sink, and power module |
| JP2015072957A (en) * | 2013-10-02 | 2015-04-16 | 日産自動車株式会社 | Junction structure of insulation substrate and cooler, manufacturing method thereof, power semiconductor module and manufacturing method thereof |
| JP2017123373A (en) * | 2016-01-05 | 2017-07-13 | 昭和電工株式会社 | Insulating substrate and method for producing the same |
| KR20190008275A (en) * | 2016-06-16 | 2019-01-23 | 미쓰비시덴키 가부시키가이샤 | Heat-dissipating base plate for semiconductor mounting and manufacturing method thereof |
| JPWO2019039258A1 (en) * | 2017-08-25 | 2020-09-17 | 京セラ株式会社 | Package and electronic device for mounting electronic components |
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| JPH1065075A (en) * | 1996-08-22 | 1998-03-06 | Mitsubishi Materials Corp | Ceramic circuit board with heat sink |
| JPH10270596A (en) * | 1997-03-26 | 1998-10-09 | Mitsubishi Materials Corp | Ceramic circuit substrate with heat sink |
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| JPS593077A (en) * | 1982-06-29 | 1984-01-09 | 株式会社東芝 | Method of bonding ceramic member and metal |
| JPH02196074A (en) * | 1989-01-25 | 1990-08-02 | Dowa Mining Co Ltd | Production of ceramics-metal joined body |
| JPH09275165A (en) * | 1996-02-07 | 1997-10-21 | Hitachi Ltd | Circuit board and semiconductor device using the same |
| JPH1065075A (en) * | 1996-08-22 | 1998-03-06 | Mitsubishi Materials Corp | Ceramic circuit board with heat sink |
| JPH10270596A (en) * | 1997-03-26 | 1998-10-09 | Mitsubishi Materials Corp | Ceramic circuit substrate with heat sink |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003090277A1 (en) * | 2002-04-19 | 2003-10-30 | Mitsubishi Materials Corporation | Circuit board, process for producing the same and power module |
| US7128979B2 (en) | 2002-04-19 | 2006-10-31 | Mitsubishi Materials Corporation | Circuit board, method of producing same, and power module |
| CN100364078C (en) * | 2002-04-19 | 2008-01-23 | 三菱麻铁里亚尔株式会社 | Circuit board, process for producing the same and power module |
| KR20120062751A (en) * | 2009-09-09 | 2012-06-14 | 미쓰비시 마테리알 가부시키가이샤 | Method for producing substrate for power module with heat sink, substrate for power module with heat sink, and power module |
| KR101690820B1 (en) | 2009-09-09 | 2016-12-28 | 미쓰비시 마테리알 가부시키가이샤 | Method for producing substrate for power module with heat sink, substrate for power module with heat sink, and power module |
| JP2015072957A (en) * | 2013-10-02 | 2015-04-16 | 日産自動車株式会社 | Junction structure of insulation substrate and cooler, manufacturing method thereof, power semiconductor module and manufacturing method thereof |
| JP2017123373A (en) * | 2016-01-05 | 2017-07-13 | 昭和電工株式会社 | Insulating substrate and method for producing the same |
| KR20190008275A (en) * | 2016-06-16 | 2019-01-23 | 미쓰비시덴키 가부시키가이샤 | Heat-dissipating base plate for semiconductor mounting and manufacturing method thereof |
| KR102159517B1 (en) | 2016-06-16 | 2020-09-24 | 미쓰비시덴키 가부시키가이샤 | Radiation base plate for semiconductor mounting and manufacturing method thereof |
| JPWO2019039258A1 (en) * | 2017-08-25 | 2020-09-17 | 京セラ株式会社 | Package and electronic device for mounting electronic components |
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