JP2001110582A - Backlight unit and liquid crystal display device - Google Patents
Backlight unit and liquid crystal display deviceInfo
- Publication number
- JP2001110582A JP2001110582A JP28400099A JP28400099A JP2001110582A JP 2001110582 A JP2001110582 A JP 2001110582A JP 28400099 A JP28400099 A JP 28400099A JP 28400099 A JP28400099 A JP 28400099A JP 2001110582 A JP2001110582 A JP 2001110582A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- supply potential
- cold
- liquid crystal
- cold cathode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
Landscapes
- Circuit Arrangements For Discharge Lamps (AREA)
- Discharge-Lamp Control Circuits And Pulse- Feed Circuits (AREA)
- Inverter Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、液晶表示装置に
関し、より特定的には、複数の冷陰極管を点灯する液晶
表示装置のバックライトユニットおよびそれを用いた液
晶表示装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a backlight unit of a liquid crystal display device for lighting a plurality of cold cathode tubes and a liquid crystal display device using the same.
【０００２】[0002]
【従来の技術】一般に、液晶表示装置には光源としてバ
ックライトが用いられる。そして、液晶表示装置が大画
面化、高輝度化を要求されるに伴い、複数の冷陰極管が
必要になるとともに大画面化に伴いサイド型、直下型等
多様な冷陰極管の配置を要求される。2. Description of the Related Art Generally, a liquid crystal display device uses a backlight as a light source. As the liquid crystal display device is required to have a large screen and high luminance, a plurality of cold cathode tubes are required, and with the large screen, various cold cathode tubes such as a side type and a direct type are required. Is done.
【０００３】複数の冷陰極管を点灯する場合、従来の冷
陰極管用自励式インバータでは、インバータトランスの
出力を複数にする方式がある。[0003] When a plurality of cold cathode tubes are turned on, a conventional self-excited inverter for a cold cathode tube has a system in which an inverter transformer has a plurality of outputs.
【０００４】図３は、インバータトランスの出力を複数
にする従来例を示す回路図である。図３を参照して、実
装基板１００には、電源電位Ｖｃｃと接地電位ＧＮＤが
与えられ、複数の冷陰極管１０２、１０４が接続され
る。FIG. 3 is a circuit diagram showing a conventional example in which an inverter transformer has a plurality of outputs. Referring to FIG. 3, power supply potential Vcc and ground potential GND are applied to mounting substrate 100, and a plurality of cold cathode tubes 102 and 104 are connected.
【０００５】実装基板１００は、電源電位Ｖｃｃに一方
端が接続されるコイルＬ１００と、コイルＬ１００の他
方端にその一方端が接続される抵抗Ｒ１００と、抵抗Ｒ
１００の他方端にベースが接続されるトランジスタＱ１
００と、トランジスタＱ１００のエミッタにそのエミッ
タが接続されるトランジスタＱ１０１と、トランジスタ
Ｑ１００のコレクタとトランジスタＱ１０１のコレクタ
の間に接続されるキャパシタＣ１００とを含む。トラン
ジスタＱ１００、Ｑ１０１のエミッタはともに接地電位
ＧＮＤに結合される。The mounting substrate 100 includes a coil L100 having one end connected to the power supply potential Vcc, a resistor R100 having one end connected to the other end of the coil L100, and a resistor R100.
100 whose base is connected to the other end of transistor 100
00, a transistor Q101 whose emitter is connected to the emitter of the transistor Q100, and a capacitor C100 connected between the collector of the transistor Q100 and the collector of the transistor Q101. The emitters of transistors Q100 and Q101 are both coupled to ground potential GND.
【０００６】実装基板１００は、さらに、インバータト
ランスＴ１００とインバータトランスＴ１００の２次側
巻線の一方端にその一方端が接続されるバラストコンデ
ンサＣ１０１、１０２とを含む。インバータトランスＴ
１００の２次側巻線の他方端は接地電位ＧＮＤと結合さ
れ、実装基板外部ではバラストコンデンサＣ１０１には
冷陰極管１０２が接続され、バラストコンデンサＣ１０
２には冷陰極管１０４が接続される。[0006] The mounting board 100 further includes an inverter transformer T100 and ballast capacitors C101 and C102 whose one ends are connected to one end of a secondary winding of the inverter transformer T100. Inverter transformer T
100, the other end of the secondary winding is coupled to the ground potential GND. Outside the mounting board, a cold cathode tube 102 is connected to the ballast capacitor C101, and the ballast capacitor C10
A cold cathode tube 104 is connected to 2.
【０００７】すなわち、インバータトランスＴ１００の
２次側巻線の両端間にバラストコンデンサＣ１０１と冷
陰極管１０２とが直列に接続され、それらと並列にバラ
ストコンデンサＣ１０２と冷陰極管１０４とが直列に接
続される。That is, the ballast capacitor C101 and the cold cathode tube 102 are connected in series between both ends of the secondary winding of the inverter transformer T100, and the ballast capacitor C102 and the cold cathode tube 104 are connected in parallel with them. Is done.
【０００８】インバータトランスＴ１００は、１次側に
第１の巻線と第２の巻線とを有する。第１の巻線の中点
にはコイルＬ１００を介して電源電位Ｖｃｃが与えられ
る。第１の巻線の一方端はトランジスタＱ１００のコレ
クタに接続され、第１の巻線の他方端はトランジスタＱ
１０１のコレクタに接続される。インバータトランスＴ
１００の１次側の第２の巻線の一方端はトランジスタＱ
１０１のベースに接続され、他方端はトランジスタＱ１
００のベースに接続される。[0008] The inverter transformer T100 has a first winding and a second winding on the primary side. The power supply potential Vcc is applied to the middle point of the first winding via the coil L100. One end of the first winding is connected to the collector of transistor Q100, and the other end of the first winding is connected to transistor Q100.
101 is connected to the collector. Inverter transformer T
One end of the second winding on the primary side of the transistor 100 is connected to the transistor Q
101 and the other end is connected to the transistor Q1.
00 is connected to the base.
【０００９】トランジスタＱ１００、Ｑ１０１、キャパ
シタＣ１００、抵抗Ｒ１００およびコイルＬ１００は、
インバータトランスの１次側の巻線とともにロイヤー発
振回路を構成する。The transistors Q100 and Q101, the capacitor C100, the resistor R100 and the coil L100
A lower oscillation circuit is configured together with the primary winding of the inverter transformer.
【００１０】図４は、図３に示した実装基板１００のイ
ンバータトランスの１次側のロイヤー発振回路を共通化
し、基板を分割した例である。FIG. 4 shows an example in which the lower-layer oscillation circuit on the primary side of the inverter transformer of the mounting board 100 shown in FIG. 3 is shared and the board is divided.
【００１１】図４を参照して、実装基板１００ａは、イ
ンバータトランスＴ１００の２次側巻線の両端間にはバ
ラストコンデンサＣ１０１と冷陰極管１０２とが直列接
続される。他の実装基板１００ａに実装される回路構成
は、図３に示した実装基板１００に実装される回路と同
様であるので説明は繰返さない。Referring to FIG. 4, on a mounting board 100a, a ballast capacitor C101 and a cold cathode tube 102 are connected in series between both ends of a secondary winding of an inverter transformer T100. The circuit configuration mounted on other mounting substrate 100a is the same as the circuit mounted on mounting substrate 100 shown in FIG. 3, and therefore description thereof will not be repeated.
【００１２】分割された実装基板１００ｂは、インバー
タトランスＴ１０１とバラストコンデンサＣ１０２とを
含む。インバータトランスＴ１０１の１次側には第１の
コイルのみがあり、この第１のコイルはインバータトラ
ンスＴ１００の１次側の第１のコイルとそれぞれ一方
端、他方端および中点同士が接続される。インバータト
ランスＴ１０１の２次側巻線の両端間にはバラストコン
デンサＣ１０２と冷陰極管１０４とが直列接続される。
そして、インバータトランスＴ１０１の２次側巻線の他
方端は、実装基板１から接地電位の供給を受ける。The divided mounting board 100b includes an inverter transformer T101 and a ballast capacitor C102. Only the first coil is provided on the primary side of the inverter transformer T101, and this first coil is connected to the first coil on the primary side of the inverter transformer T100 at one end, the other end, and the middle point, respectively. . A ballast capacitor C102 and a cold cathode tube 104 are connected in series between both ends of the secondary winding of the inverter transformer T101.
The other end of the secondary winding of the inverter transformer T101 receives the ground potential from the mounting board 1.
【００１３】[0013]
【発明が解決しようとする課題】従来の冷陰極管用自励
式インバータ基板では、多様な冷陰極管配置かつ複数の
冷陰極管に対し、実装基板の分割をするには次のような
問題があった。In a conventional self-excited inverter board for a cold cathode fluorescent lamp, there are the following problems in dividing a mounting board into various cold cathode fluorescent lamps and a plurality of cold cathode fluorescent lamps. Was.
【００１４】図３に示したようなインバータトランスの
出力を複数にする方式では、トランス２次側出力に複数
のバラストコンデンサを並列に備え、複数の冷陰極管に
対し各々高電圧配線をする必要がある。In the method of making the output of the inverter transformer plural as shown in FIG. 3, it is necessary to equip the secondary output of the transformer with a plurality of ballast capacitors in parallel and to connect high voltage wiring to each of the plurality of cold cathode tubes. There is.
【００１５】この方式では、一つのトランスから複数の
冷陰極管に各々高電圧配線を施す必要がある。一般に、
インバータトランスの２次側の電圧は瞬間的には１００
０Ｖを超えるような高電圧になり、定常状態においても
およそ８００Ｖ程度の高電圧が出力されている。In this method, it is necessary to provide high voltage wiring from one transformer to a plurality of cold cathode tubes. In general,
The voltage on the secondary side of the inverter transformer is 100
The high voltage exceeds 0 V, and a high voltage of about 800 V is output even in a steady state.
【００１６】多様な冷陰極管配置によっては高電圧配線
の配線長が異なり、かつ高電圧にもかかわらず配線長を
長くする必要があり、安全性・信頼性が低下する。ま
た、配線浮遊容量や接地された導体に対するＡＣ結合に
よるリーク電流の増加に伴いインバータの効率が低下す
る。つまり、高周波の信号が配線を通過する際に損失が
生じてしまう。The wiring length of the high-voltage wiring differs depending on various cold-cathode tube arrangements, and it is necessary to increase the wiring length in spite of the high voltage, which lowers the safety and reliability. In addition, the efficiency of the inverter decreases with an increase in leakage current due to wiring stray capacitance and AC coupling to a grounded conductor. That is, loss occurs when a high-frequency signal passes through the wiring.
【００１７】さらには、各々の冷陰極管に対するリーク
電流のアンバランスが発生するため、液晶表示装置とし
ての輝度バランスが取れない。なお、トランスが一つし
かないため実装基板の分割ができないとともに各冷陰極
管を独立に調光することができない。Furthermore, since the imbalance of the leak current to each cold cathode tube occurs, the luminance balance as the liquid crystal display device cannot be obtained. In addition, since there is only one transformer, the mounting substrate cannot be divided and each cold cathode tube cannot be independently dim.
【００１８】１次側のロイヤー発振回路を共通に使用す
る図４に示したような構成にすれば、複数のトランスを
備えているので、リーク電流の増加防止および液晶表示
装置における構造設計の簡易化のための実装基板の分割
が一応できる。In the configuration shown in FIG. 4 in which the primary side lower oscillation circuit is commonly used, since a plurality of transformers are provided, it is possible to prevent an increase in leakage current and to simplify the structural design of the liquid crystal display device. The mounting substrate can be divided for the sake of convenience.
【００１９】しかし、トランス１次側のロイヤー発振回
路の電圧は、トランス一次側のコイル成分により一次電
源電位より高電圧になる。一次電源電位が１０Ｖ程度だ
とすると、ロイヤー発振回路の電圧は４０〜５０Ｖにな
り、１次側とはいえ高い上に高周波である。However, the voltage of the lower oscillating circuit on the primary side of the transformer becomes higher than the primary power supply potential due to the coil component on the primary side of the transformer. Assuming that the primary power supply potential is about 10 V, the voltage of the lower oscillation circuit is 40 to 50 V, which is high on the primary side and high frequency.
【００２０】それにもかかわらず、高電圧、高周波であ
るロイヤー発振回路の発振信号を伝達する配線を基板間
に設ける必要がある。そのため、ノイズ発生の原因にな
るとともに、安全性・信頼性が問題となる。Nevertheless, it is necessary to provide a wiring for transmitting a high voltage, high frequency oscillation signal of the lower oscillation circuit between the substrates. For this reason, noise is generated, and safety and reliability become problems.
【００２１】また、ロイヤー発振回路の発振信号を各々
のトランスに伝達する配線が長くなり、発振不良の原因
となる。なお、この方式もロイヤー発振回路が複数のト
ランスに対し共通であるため各冷陰極管を独立に調光す
ることができない。Further, the length of the wiring for transmitting the oscillation signal of the lower oscillation circuit to each transformer becomes longer, which causes oscillation failure. In this method, since the lower oscillation circuit is common to a plurality of transformers, it is not possible to independently control the light of each cold cathode tube.
【００２２】本発明は、このような課題を解決したもの
であり、多様な冷陰極管配置かつ複数の冷陰極管に対
し、同期をとりながら独立に調光できる機能を有し、か
つ、安全性・信頼性の向上、ノイズの抑制、リーク電流
の増加防止に伴う低消費電力化を実現し、さらには、液
晶表示装置における構造設計の簡易化かつ小型化・軽量
化に伴うコスト低減が可能な液晶表示装置の提供を目的
とする。The present invention has solved the above-mentioned problem, and has a function of enabling a dimming of a plurality of cold-cathode tubes independently of each other while synchronizing with each other. Low power consumption due to improvement in reliability and performance, suppression of noise, and prevention of increase in leak current.Furthermore, it is possible to simplify the structural design of liquid crystal display devices and reduce costs due to miniaturization and weight reduction. It is intended to provide a simple liquid crystal display device.
【００２３】[0023]
【課題を解決するための手段】請求項１に記載のバック
ライトユニットは、複数の冷陰極管を点灯するためのバ
ックライトユニットであって、複数の冷陰極管は、複数
の群に分割され、第１の電源電位と第１の電源電位より
高い第２の電源電位を受けてクロック信号と制御信号と
を出力する制御回路と、複数の群にそれぞれ対応して設
けられ、クロック信号および制御信号に応じて冷陰極管
を駆動する高電圧パルスを発生する複数の冷陰極管駆動
回路と、複数の冷陰極管駆動回路にそれぞれ対応して設
けられる複数の実装基板とを備える。A backlight unit according to claim 1 is a backlight unit for lighting a plurality of cold cathode tubes, wherein the plurality of cold cathode tubes are divided into a plurality of groups. A control circuit for receiving a first power supply potential and a second power supply potential higher than the first power supply potential and outputting a clock signal and a control signal, and a control circuit provided corresponding to each of the plurality of groups; A plurality of cold cathode tube driving circuits for generating high voltage pulses for driving the cold cathode tubes in response to signals, and a plurality of mounting substrates provided corresponding to the plurality of cold cathode tube driving circuits, respectively.
【００２４】請求項２に記載のバックライトユニット
は、請求項１に記載のバックライトユニットの構成にお
いて、制御信号およびクロック信号の振幅は、第１の電
源電位と第２の電源電位との電位差以下であり、高電圧
パルスの振幅は、第１の電源電位と第２の電源電位との
電位差より大きい。According to a second aspect of the present invention, in the configuration of the backlight unit according to the first aspect, the amplitude of the control signal and the clock signal is equal to the potential difference between the first power supply potential and the second power supply potential. The amplitude of the high voltage pulse is larger than the potential difference between the first power supply potential and the second power supply potential.
【００２５】請求項３に記載のバックライトユニット
は、請求項１に記載のバックライトユニットの構成に加
えて、複数の実装基板は、第１、第２の実装基板を含
み、制御回路は、第１の実装基板に実装され、制御信号
とクロック信号とを第１の実装基板から第２の実装基板
へと伝達する配線群をさらに備える。According to a third aspect of the present invention, in addition to the configuration of the backlight unit in the first aspect, the plurality of mounting boards include first and second mounting boards, and the control circuit includes: A wiring group mounted on the first mounting board and transmitting a control signal and a clock signal from the first mounting board to the second mounting board is further provided.
【００２６】請求項４に記載のバックライトユニット
は、請求項１に記載のバックライトユニットの構成に加
えて、各冷陰極管駆動回路は、対応する群に含まれる複
数の冷陰極管にそれぞれ対応する複数のインバータトラ
ンスを含む。According to a fourth aspect of the present invention, in addition to the configuration of the backlight unit according to the first aspect, each of the CCFL driving circuits includes a plurality of CCFLs respectively corresponding to a plurality of CCFLs included in a corresponding group. Includes a corresponding plurality of inverter transformers.
【００２７】請求項５に記載の液晶表示装置は、液晶パ
ネルと、液晶パネルのバックライトに使用される複数の
冷陰極管と、第１の電源電位と第１の電源電位より高い
第２の電源電位を受けてクロック信号と制御信号とを出
力する制御回路とを備え、複数の冷陰極管は、複数の群
に分割され、複数の群にそれぞれ対応して設けられ、ク
ロック信号および制御信号に応じて冷陰極管を駆動する
高電圧パルスを発生する複数の冷陰極管駆動回路と、複
数の冷陰極管駆動回路にそれぞれ対応して設けられる複
数の実装基板とをさらに備える。According to a fifth aspect of the present invention, there is provided a liquid crystal display device comprising: a liquid crystal panel; a plurality of cold cathode tubes used for a backlight of the liquid crystal panel; a first power supply potential; and a second power supply potential higher than the first power supply potential. A control circuit for receiving a power supply potential and outputting a clock signal and a control signal; wherein the plurality of cold cathode tubes are divided into a plurality of groups, provided corresponding to the plurality of groups, respectively, and the clock signal and the control signal are provided. And a plurality of mounting substrates provided corresponding to the plurality of CCFL drive circuits, respectively.
【００２８】請求項６に記載の液晶表示装置は、請求項
５に記載の液晶表示装置の構成において、制御信号およ
びクロック信号の振幅は、第１の電源電位と第２の電源
電位との電位差以下であり、高電圧パルスの振幅は、第
１の電源電位と第２の電源電位との電位差より大きい。According to a sixth aspect of the present invention, in the liquid crystal display device according to the fifth aspect, the amplitude of the control signal and the clock signal is equal to the potential difference between the first power supply potential and the second power supply potential. The amplitude of the high voltage pulse is larger than the potential difference between the first power supply potential and the second power supply potential.
【００２９】請求項７に記載の液晶表示装置は、請求項
５に記載の液晶表示装置の構成に加えて、複数の実装基
板は、第１、第２の実装基板を含み、制御回路は、第１
の実装基板に実装され、制御信号とクロック信号とを第
１の実装基板から第２の実装基板へと伝達する配線群を
さらに備える。According to a seventh aspect of the present invention, in addition to the configuration of the liquid crystal display of the fifth aspect, the plurality of mounting boards include first and second mounting boards, and the control circuit includes: First
And a wiring group mounted on the first mounting board for transmitting a control signal and a clock signal from the first mounting board to the second mounting board.
【００３０】請求項８に記載の液晶表示装置は、請求項
５に記載の液晶表示装置の構成に加えて、各冷陰極管駆
動回路は、対応する群に含まれる複数の冷陰極管にそれ
ぞれ対応する複数のインバータトランスを含む。In the liquid crystal display device according to the eighth aspect, in addition to the configuration of the liquid crystal display device according to the fifth aspect, each of the cold cathode tube driving circuits includes a plurality of cold cathode tube driving circuits included in a corresponding group. Includes a corresponding plurality of inverter transformers.
【００３１】請求項９に記載の液晶表示装置は、請求項
５に記載の液晶表示装置の構成に加えて、液晶パネルは
四角形の形状を有し、複数の実装基板は、第１、第２の
実装基板を含み、複数の冷陰極管のうち四角形の第１の
辺に対応して設けられる第１の冷陰極管は、第１の実装
基板から高電圧パルスを受け、複数の冷陰極管のうち第
１の辺に対向する四角形の第２の辺に対応して設けられ
る第２の冷陰極管は、第２の実装基板から高電圧パルス
を受ける。In the liquid crystal display device according to the ninth aspect, in addition to the configuration of the liquid crystal display device according to the fifth aspect, the liquid crystal panel has a rectangular shape, and the plurality of mounting substrates are formed of first and second substrates. The first cold cathode tube provided corresponding to the first side of the quadrangle of the plurality of cold cathode tubes receives a high voltage pulse from the first mounting substrate, and includes a plurality of cold cathode tubes. The second cold cathode tube provided corresponding to the second side of the rectangle facing the first side receives a high voltage pulse from the second mounting substrate.
【００３２】[0032]
【発明の実施の形態】以下において、本発明の実施の形
態について図面を参照して詳しく説明する。なお、図中
同一符号は同一または相当部分を示す。Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.
【００３３】図１は、本発明の実施の形態に係る液晶表
示装置１の構成を概略的に示す平面構造図である。FIG. 1 is a plan view schematically showing a configuration of a liquid crystal display device 1 according to an embodiment of the present invention.
【００３４】図１を参照して、液晶パネル２と、液晶パ
ネル２をエッジ方向から照らす冷陰極管８〜２２と、冷
陰極管８〜１４に対応して設けられる実装基板４と、冷
陰極管１６〜１８に対応して設けられる実装基板６とを
含む。冷陰極管８〜２２と実装基板４、６とはバックラ
イトユニットと呼ばれる。図１では、実施例として、４
辺に冷陰極管を各２灯配置し、合計８灯の冷陰極管を備
えたエッジライト方式のバックライトユニットを液晶パ
ネルに装着し、裏面から見た状態を示している。Referring to FIG. 1, a liquid crystal panel 2, cold cathode tubes 8 to 22 illuminating liquid crystal panel 2 from the edge direction, a mounting substrate 4 provided corresponding to cold cathode tubes 8 to 14, and a cold cathode And a mounting board 6 provided corresponding to the tubes 16 to 18. The cold cathode tubes 8 to 22 and the mounting substrates 4 and 6 are called a backlight unit. In FIG. 1, as an embodiment, 4
The figure shows a state in which two cold cathode tubes are arranged on each side, and an edge light type backlight unit having a total of eight cold cathode tubes is mounted on a liquid crystal panel and viewed from the back.
【００３５】実装基板４は、制御回路２４と、他励発振
出力回路２６と、コネクタ２８、３０とを含む。他励発
振出力回路２６は、冷陰極管を接続するための端子対Ｔ
Ｂ１、ＴＢ２、ＴＲ１、ＴＲ２を含む。The mounting board 4 includes a control circuit 24, a separately excited oscillation output circuit 26, and connectors 28 and 30. The separately excited oscillation output circuit 26 has a terminal pair T for connecting a cold cathode tube.
B1, TB2, TR1, and TR2.
【００３６】実装基板６は、他励発振出力回路３２と、
コネクタ３４とを含む。他励発振出力回路３２は、冷陰
極管を接続するための端子対ＴＢ３、ＴＢ４、ＴＲ３、
ＴＲ４とを含む。The mounting board 6 includes a separately excited oscillation output circuit 32,
And a connector 34. The separately excited oscillation output circuit 32 includes a pair of terminals TB3, TB4, TR3,
TR4.
【００３７】コネクタ３０には、外部から与えられる１
０〜１２Ｖ程度の１次電源等が接続される。コネクタ３
４と２８とは外部配線によって接続される。The connector 30 has an externally supplied 1
A primary power supply of about 0 to 12 V is connected. Connector 3
4 and 28 are connected by external wiring.
【００３８】図２は、図１に示した実装基板４、６の詳
細な構成を示す回路図である。図２を参照して、実装基
板４は、制御回路２４と、他励発振出力回路２６とを含
む。FIG. 2 is a circuit diagram showing a detailed configuration of the mounting boards 4 and 6 shown in FIG. Referring to FIG. 2, mounting substrate 4 includes a control circuit 24 and a separately excited oscillation output circuit 26.
【００３９】制御回路２４は、電源電位Ｖｃｃに一端が
結合されるヒューズＦ１と、クロック信号ＣＬＫを発生
するクロック発生回路Ｂ１と、外部から制御信号Ｓ１を
受け応じて調光用ＰＷＭ（Pulse Width Modulation）信
号ＳＳ１を発生する調光用ＰＷＭ信号発生回路Ｂ２と、
外部から制御信号Ｓ２を受け応じて調光用ＰＷＭ信号Ｓ
Ｓ２を発生する調光用ＰＷＭ信号発生回路Ｂ３とを含
む。The control circuit 24 has a fuse F1 having one end coupled to the power supply potential Vcc, a clock generation circuit B1 for generating a clock signal CLK, and a dimming PWM (Pulse Width Modulation) in response to a control signal S1 from the outside. ) A dimming PWM signal generation circuit B2 for generating a signal SS1,
PWM signal S for dimming in response to control signal S2 from outside
And a dimming PWM signal generation circuit B3 for generating S2.
【００４０】図示していないが、クロック発生回路Ｂ１
は、電源電位Ｖｃｃと接地電位ＧＮＤから動作電源電流
をうけ、クロック信号ＣＬＫの振幅は、電源電位Ｖｃｃ
より大きくなることはない。同様に、図示していない
が、調光用ＰＷＭ信号発生回路Ｂ２、Ｂ３は、電源電位
Ｖｃｃと接地電位ＧＮＤから動作電源電流をうけ、調光
用ＰＷＭ信号ＳＳ１、ＳＳ２の振幅は、電源電位Ｖｃｃ
より大きくなることはない。すなわち、クロック信号Ｃ
ＬＫ、調光用ＰＷＭ信号ＳＳ１、ＳＳ２はいわゆる小信
号であるといえる。Although not shown, the clock generation circuit B1
Receives the operating power supply current from the power supply potential Vcc and the ground potential GND, and the amplitude of the clock signal CLK is
It cannot be larger. Similarly, although not shown, the dimming PWM signal generation circuits B2 and B3 receive an operation power supply current from the power supply potential Vcc and the ground potential GND, and the amplitude of the dimming PWM signals SS1 and SS2 is equal to the power supply potential Vcc.
It cannot be larger. That is, the clock signal C
It can be said that the LK and the dimming PWM signals SS1 and SS2 are so-called small signals.
【００４１】他励発振出力回路２６は、ヒューズＦ１の
他方端にその一方端が接続されるヒューズＦ２と、ヒュ
ーズＦ２の他方端に接続されるコイルＬ１と、クロック
信号ＣＬＫを受けて反転し逆相クロック信号ｈ１を出力
するインバータゲートＧ９と、クロック信号ＣＬＫと調
光用ＰＷＭ信号ＳＳ１とを受けるＡＮＤゲートＧ１と、
ゲートにＡＮＤゲートＧ１の出力を受けソースおよびサ
ブストレートが接地された電界効果形トランジスタ（Ｆ
ＥＴ）Ｑ１と、逆相クロック信号ｈ１および調光用ＰＷ
Ｍ信号ＳＳ１を受けるＡＮＤゲートＧ２と、ＡＮＤゲー
トＧ２の出力をゲートに受けソースおよびサブストレー
トが接地された電界効果形トランジスタＱ２とを含む。The separately excited oscillation output circuit 26 receives a clock signal CLK, inverts and reverses a fuse F2 having one end connected to the other end of the fuse F1 and a coil L1 connected to the other end of the fuse F2. An inverter gate G9 that outputs the phase clock signal h1, an AND gate G1 that receives the clock signal CLK and the dimming PWM signal SS1,
A field-effect transistor (F) whose gate receives the output of AND gate G1 and whose source and substrate are grounded
ET) Q1, the antiphase clock signal h1 and the dimming PW
An AND gate G2 receiving the M signal SS1, and a field effect transistor Q2 receiving the output of the AND gate G2 at its gate and having its source and substrate grounded.
【００４２】他励発振出力回路２６は、さらに、外部に
接続される冷陰極管８、１０にそれぞれ対応して設けら
れるインバータトランスＴ１、Ｔ２と、インバータトラ
ンスＴ１の１次側巻線の両端間に接続されるキャパシタ
Ｃ１と、インバータトランスＴ１の２次側巻線の両端間
に冷陰極管８と直列に接続されるバラストコンデンサＣ
５と、インバータトランスＴ２の２次側巻線の両端間に
冷陰極管１０と直列に接続されるバラストコンデンサＣ
６とを含む。The separately excited oscillation output circuit 26 further includes inverter transformers T1 and T2 provided corresponding to the cold cathode tubes 8 and 10 connected to the outside, respectively, and both ends of the primary winding of the inverter transformer T1. And a ballast capacitor C connected in series with the cold-cathode tube 8 between both ends of the secondary winding of the inverter transformer T1.
And a ballast capacitor C connected in series with the cold-cathode tube 10 between both ends of the secondary winding of the inverter transformer T2.
6 is included.
【００４３】インバータトランスＴ１、Ｔ２の１次側巻
線の中点にはともにコイルＬ１、ヒューズＦ２を介して
電源電位Ｖｃｃが与えられる。また、インバータトラン
スＴ２の１次コイルの両端はインバータトランスＴ１の
１次側巻線と並列に接続されている。インバータトラン
スＴ１、Ｔ２の２次側巻線の冷陰極管に接続される側
は、接地電位に結合されている。The power supply potential Vcc is applied to the middle point between the primary windings of the inverter transformers T1 and T2 via the coil L1 and the fuse F2. Both ends of the primary coil of the inverter transformer T2 are connected in parallel with the primary winding of the inverter transformer T1. The sides of the secondary windings of the inverter transformers T1 and T2 connected to the cold cathode tubes are coupled to the ground potential.
【００４４】他励発振出力回路２６は、さらに、ヒュー
ズＦ１の他方端にその一方端が接続されるヒューズＦ３
と、ヒューズＦ３の他方端に接続されるコイルＬ２と、
クロック信号ＣＬＫを受けて反転し逆相クロック信号ｈ
２を出力するインバータゲートＧ１０と、クロック信号
ＣＬＫと調光用ＰＷＭ信号ＳＳ２とを受けるＡＮＤゲー
トＧ３と、ゲートにＡＮＤゲートＧ３の出力を受けソー
スおよびサブストレートが接地された電界効果形トラン
ジスタＱ３と、逆相クロック信号ｈ２および調光用ＰＷ
Ｍ信号ＳＳ２を受けるＡＮＤゲートＧ４と、ＡＮＤゲー
トＧ４の出力をゲートに受けソースおよびサブストレー
トが接地された電界効果形トランジスタＱ４とを含む。The separately excited oscillation output circuit 26 further includes a fuse F3 having one end connected to the other end of the fuse F1.
And a coil L2 connected to the other end of the fuse F3;
The inverted clock signal h is inverted upon receiving the clock signal CLK.
2, an AND gate G3 receiving the clock signal CLK and the dimming PWM signal SS2, a field effect transistor Q3 receiving the output of the AND gate G3 at the gate and grounding the source and the substrate. , Antiphase clock signal h2 and dimming PW
An AND gate G4 receiving the M signal SS2, and a field effect transistor Q4 receiving the output of the AND gate G4 at its gate and having its source and substrate grounded.
【００４５】他励発振出力回路２６は、さらに、外部に
接続される冷陰極管１２、１４にそれぞれ対応して設け
られるインバータトランスＴ３、Ｔ４と、インバータト
ランスＴ３の１次側巻線の両端間に接続されるキャパシ
タＣ２と、インバータトランスＴ３の２次側巻線の両端
間に冷陰極管１２と直列に接続されるバラストコンデン
サＣ７と、インバータトランスＴ４の２次側巻線の両端
間に冷陰極管１４と直列に接続されるバラストコンデン
サＣ８とを含む。The separately-excited oscillation output circuit 26 further includes inverter transformers T3 and T4 provided corresponding to the cold cathode tubes 12 and 14 connected to the outside, respectively, and both ends of the primary winding of the inverter transformer T3. , A ballast capacitor C7 connected in series with the cold-cathode tube 12 between both ends of the secondary winding of the inverter transformer T3, and a cold capacitor between both ends of the secondary winding of the inverter transformer T4. And a ballast capacitor C8 connected in series with the cathode tube 14.
【００４６】インバータトランスＴ３、Ｔ４の１次側巻
線の中点にはともにコイルＬ２、ヒューズＦ３を介して
電源電位Ｖｃｃが与えられる。また、インバータトラン
スＴ４の１次コイルの両端はインバータトランスＴ３の
１次側巻線と並列に接続されている。インバータトラン
スＴ３、Ｔ４の２次側巻線の冷陰極管に接続される側
は、接地電位に結合されている。The power supply potential Vcc is applied to the middle point between the primary windings of the inverter transformers T3 and T4 via the coil L2 and the fuse F3. Both ends of the primary coil of the inverter transformer T4 are connected in parallel with the primary winding of the inverter transformer T3. The side of the secondary winding of each of the inverter transformers T3 and T4 connected to the cold cathode tube is coupled to the ground potential.
【００４７】実装基板４は、コネクタ２８をさらに含
む。コネクタ２８は、端子ａ〜ｅを含む。端子ａにはヒ
ューズＦ１を介して電源電位Ｖｃｃが与えられる。端子
ｅは接地電位と結合されている。端子ｂはクロック信号
ＣＬＫが出力される。端子ｃ、端子ｄからはそれぞれ調
光用ＰＷＭ信号ＳＳ１、ＳＳ２が出力される。The mounting board 4 further includes a connector 28. The connector 28 includes terminals a to e. Power supply potential Vcc is applied to terminal a via fuse F1. Terminal e is coupled to ground potential. The terminal b receives the clock signal CLK. The dimming PWM signals SS1 and SS2 are output from the terminals c and d, respectively.
【００４８】実装基板６は、コネクタ３４と他励起発振
出力回路３２とを含む。コネクタ３４の端子ａ〜ｅはそ
れぞれコネクタ２８の端子ａ〜ｅと外部配線によって接
続されている。The mounting board 6 includes a connector 34 and another excitation oscillation output circuit 32. The terminals a to e of the connector 34 are connected to the terminals a to e of the connector 28 by external wiring, respectively.
【００４９】他励発振出力回路３２は、コネクタ３４の
ａ端子に一方端が接続されるヒューズＦ４と、ヒューズ
Ｆ４の他方端に接続されるコイルＬ３と、クロック信号
ＣＬＫをコネクタ３４のｂ端子を介して受け、反転して
逆相クロック信号ｈ３を出力するインバータゲートＧ１
１と、クロック信号ＣＬＫと調光用ＰＷＭ信号ＳＳ１と
をそれぞれコネクタ３４のｂ、ｃ端子を介して受けるＡ
ＮＤゲートＧ５と、ゲートにＡＮＤゲートＧ５の出力を
受けソースおよびサブストレートが接地された電界効果
形トランジスタＱ５と、逆相クロック信号ｈ３および調
光用ＰＷＭ信号ＳＳ１を受けるＡＮＤゲートＧ６と、Ａ
ＮＤゲートＧ６の出力をゲートに受けソースおよびサブ
ストレートが接地された電界効果形トランジスタＱ６と
を含む。The separately-excited oscillation output circuit 32 connects a terminal F to the terminal a of the connector 34, a coil L 3 connected to the other end of the fuse F 4, and a clock signal CLK to the terminal b of the connector 34. Inverter gate G1 receiving and inverting and outputting inverted phase clock signal h3
A receiving the clock signal CLK and the dimming PWM signal SS1 via the b and c terminals of the connector 34, respectively.
An ND gate G5, a field-effect transistor Q5 having a gate receiving the output of the AND gate G5 and a source and a substrate grounded, an AND gate G6 receiving an inverted-phase clock signal h3 and a dimming PWM signal SS1, and A
And a field effect transistor Q6 having its gate receiving the output of ND gate G6 and having its source and substrate grounded.
【００５０】他励発振出力回路３２は、さらに、外部に
接続される冷陰極管１６、１８にそれぞれ対応して設け
られるインバータトランスＴ５、Ｔ６と、インバータト
ランスＴ５の１次側巻線の両端間に接続されるキャパシ
タＣ３と、インバータトランスＴ５の２次側巻線の両端
間に冷陰極管１６と直列に接続されるバラストコンデン
サＣ９と、インバータトランスＴ６の２次側巻線の両端
間に冷陰極管１８と直列に接続されるバラストコンデン
サＣ１０とを含む。The separately-excited oscillation output circuit 32 further includes inverter transformers T5 and T6 provided corresponding to the cold cathode tubes 16 and 18 connected to the outside, respectively, and both ends of the primary winding of the inverter transformer T5. , A ballast capacitor C9 connected in series with the cold-cathode tube 16 between both ends of the secondary winding of the inverter transformer T5, and a cold capacitor between both ends of the secondary winding of the inverter transformer T6. A ballast capacitor C10 connected in series with the cathode tube 18;
【００５１】インバータトランスＴ５、Ｔ６の１次側巻
線の中点にはともにコイルＬ３、ヒューズＦ４を介して
電源電位Ｖｃｃが与えられる。また、インバータトラン
スＴ６の１次コイルの両端はインバータトランスＴ５の
１次側巻線と並列に接続されている。インバータトラン
スＴ５、Ｔ６の２次側巻線の冷陰極管に接続される側
は、接地電位に結合されている。The power supply potential Vcc is applied to the center of the primary windings of the inverter transformers T5 and T6 via the coil L3 and the fuse F4. Both ends of the primary coil of the inverter transformer T6 are connected in parallel with the primary winding of the inverter transformer T5. The sides of the secondary windings of the inverter transformers T5 and T6 connected to the cold cathode tubes are coupled to the ground potential.
【００５２】他励発振出力回路３２は、さらに、コネク
タ３４のａ端子に一方端が接続されるヒューズＦ５と、
ヒューズＦ５の他方端に接続されるコイルＬ４と、クロ
ック信号ＣＬＫをコネクタ３４のｂ端子を介して受けて
反転し逆相クロック信号ｈ４を出力するインバータゲー
トＧ１２と、クロック信号ＣＬＫと調光用ＰＷＭ信号Ｓ
Ｓ２とをそれぞれコネクタ３４のｂ、ｄ端子を介して受
けるＡＮＤゲートＧ７と、ゲートにＡＮＤゲートＧ７の
出力を受けソースおよびサブストレートが接地された電
界効果形トランジスタＱ７と、逆相クロック信号ｈ４お
よび調光用ＰＷＭ信号ＳＳ２を受けるＡＮＤゲートＧ８
と、ＡＮＤゲートＧ８の出力をゲートに受けソースおよ
びサブストレートが接地された電界効果形トランジスタ
Ｑ８とを含む。The separately excited oscillation output circuit 32 further includes a fuse F5 having one end connected to the terminal a of the connector 34,
A coil L4 connected to the other end of the fuse F5, an inverter gate G12 which receives the clock signal CLK via the terminal b of the connector 34 and inverts the inverted clock signal to output the inverted clock signal h4, a clock signal CLK and a dimming PWM signal Signal S
S2 through the b and d terminals of the connector 34, an AND gate G7, an output of the AND gate G7 at the gate, a field-effect transistor Q7 having a source and a substrate grounded, an antiphase clock signal h4 and AND gate G8 receiving PWM signal SS2 for dimming
And a field effect transistor Q8 having its gate receiving the output of AND gate G8 and having its source and substrate grounded.
【００５３】他励発振出力回路３２は、さらに、外部に
接続される冷陰極管２０、２２にそれぞれ対応して設け
られるインバータトランスＴ７、Ｔ８と、インバータト
ランスＴ７の１次側巻線の両端間に接続されるキャパシ
タＣ４と、インバータトランスＴ７の２次側巻線の両端
間に冷陰極管２０と直列に接続されるバラストコンデン
サＣ１１と、インバータトランスＴ８の２次側巻線の両
端間に冷陰極管２２と直列に接続されるバラストコンデ
ンサＣ１２とを含む。The separately excited oscillation output circuit 32 further includes inverter transformers T7 and T8 provided corresponding to the cold cathode tubes 20 and 22 connected to the outside, respectively, and both ends of the primary winding of the inverter transformer T7. , A ballast capacitor C11 connected in series with the cold-cathode tube 20 between both ends of the secondary winding of the inverter transformer T7, and a cold capacitor between both ends of the secondary winding of the inverter transformer T8. A ballast capacitor C12 connected in series with the cathode tube 22;
【００５４】インバータトランスＴ７、Ｔ８の１次側巻
線の中点にはともに電源電位ＶｃｃがコイルＬ４、ヒュ
ーズＦ５を介して与えられる。また、インバータトラン
スＴ８の１次コイルの両端はインバータトランスＴ７の
１次側巻線と並列に接続されている。インバータトラン
スＴ５、Ｔ６の２次側巻線の冷陰極管に接続される側
は、接地電位に結合されている。The power supply potential Vcc is applied to the middle point between the primary windings of the inverter transformers T7 and T8 via the coil L4 and the fuse F5. Both ends of the primary coil of the inverter transformer T8 are connected in parallel with the primary winding of the inverter transformer T7. The sides of the secondary windings of the inverter transformers T5 and T6 connected to the cold cathode tubes are coupled to the ground potential.
【００５５】次に、実装基板４、６における回路動作に
ついて簡単に説明する。クロック発生回路Ｂ１により生
成される他励式インバータの発振周波数を決定するクロ
ック信号ＣＬＫは、スイッチング素子Ｑ１〜Ｑ４をプッ
シュプル駆動するために、ＡＮＤゲートＧ１、Ｇ３へ送
られる。また、クロック信号ＣＬＫは、インバータゲー
トＧ９、Ｇ１０により反転され、反転クロック信号ｈ
１、ｈ２がＡＮＤゲートＧ２、Ｇ４へ送られる。Next, the circuit operation on the mounting boards 4 and 6 will be briefly described. The clock signal CLK generated by the clock generation circuit B1 and determining the oscillation frequency of the separately-excited inverter is sent to the AND gates G1 and G3 in order to push-pull the switching elements Q1 to Q4. The clock signal CLK is inverted by the inverter gates G9 and G10, and the inverted clock signal h
1, h2 are sent to AND gates G2, G4.
【００５６】図示していないが、クロック発生回路Ｂ１
は、電源電位Ｖｃｃと接地電位ＧＮＤから動作電源電流
をうけ、クロック信号ＣＬＫの振幅は、電源電位Ｖｃｃ
より大きくなることはない。すなわち、クロック信号Ｃ
ＬＫはいわゆる小信号であるといえる。Although not shown, the clock generation circuit B1
Receives the operating power supply current from the power supply potential Vcc and the ground potential GND, and the amplitude of the clock signal CLK is
It cannot be larger. That is, the clock signal C
LK can be said to be a so-called small signal.
【００５７】なお、単一クロック発生回路Ｂ１が逆位相
出力を有する場合は、インバータゲートＧ９、Ｇ１０を
省略できる。When the single clock generation circuit B1 has an opposite phase output, the inverter gates G9 and G10 can be omitted.
【００５８】スイッチング素子Ｑ１〜Ｑ４をＰＷＭ制御
し、冷陰極管８〜１４を調光制御するＰＷＭ信号ＳＳ
１、ＳＳ２は、調光用ＰＷＭ信号発生回路Ｂ２、Ｂ３に
より生成され、調光用ＰＷＭ信号ＳＳ１は、ＡＮＤゲー
トＧ１、Ｇ２に送られ、調光用ＰＷＭ信号ＳＳ２は、Ａ
ＮＤゲートＧ３、Ｇ４へ送られる。A PWM signal SS for performing PWM control of the switching elements Q1 to Q4 and dimming control of the cold cathode tubes 8 to 14.
1 and SS2 are generated by dimming PWM signal generation circuits B2 and B3, the dimming PWM signal SS1 is sent to AND gates G1 and G2, and the dimming PWM signal SS2 is
It is sent to ND gates G3 and G4.
【００５９】図示していないが、調光用ＰＷＭ信号発生
回路Ｂ２、Ｂ３は、電源電位Ｖｃｃと接地電位ＧＮＤか
ら動作電源電流をうけ、調光用ＰＷＭ信号ＳＳ１、ＳＳ
２の振幅は、電源電位Ｖｃｃより大きくなることはな
い。すなわち、調光用ＰＷＭ信号ＳＳ１、ＳＳ２はいわ
ゆる小信号であるといえる。Although not shown, the dimming PWM signal generation circuits B2 and B3 receive the operation power supply current from the power supply potential Vcc and the ground potential GND, and receive the dimming PWM signals SS1 and SS3.
2 does not become larger than the power supply potential Vcc. That is, it can be said that the dimming PWM signals SS1 and SS2 are so-called small signals.
【００６０】電源電位Ｖｃｃは、コイルＬ１、Ｌ２を介
してインバータトランスＴ１〜Ｔ４の中点へ接続され
る。The power supply potential Vcc is connected to the middle points of the inverter transformers T1 to T4 via the coils L1 and L2.
【００６１】ＡＮＤゲートＧ１には、クロック信号ＣＬ
Ｋと、調光用ＰＷＭ信号発生回路Ｂ２より生成される調
光用ＰＷＭ信号ＳＳ１が入力される。ＡＮＤゲートＧ２
には、クロック信号ＣＬＫと逆相のクロック信号ｈ１
と、調光用ＰＷＭ信号発生回路Ｂ２により生成される調
光用ＰＷＭ信号ＳＳ１が入力される。The AND gate G1 has a clock signal CL
K and the dimming PWM signal SS1 generated by the dimming PWM signal generation circuit B2 are input. AND gate G2
Includes a clock signal h1 having a phase opposite to that of the clock signal CLK.
And the dimming PWM signal SS1 generated by the dimming PWM signal generation circuit B2.
【００６２】そのため、調光用ＰＷＭ信号ＳＳ１がＨ
（ハイ）レベルの間、インバータトランスＴ１、Ｔ２の
１次巻線に接続されるスイッチング素子Ｑ１、Ｑ２がプ
ッシュプル駆動され、冷陰極管８、１０はＰＷＭ調光さ
れる。Therefore, the PWM signal SS1 for dimming becomes H
During the (high) level, the switching elements Q1, Q2 connected to the primary windings of the inverter transformers T1, T2 are push-pull driven, and the cold cathode tubes 8, 10 are subjected to PWM dimming.
【００６３】ＡＮＤゲートＧ３には、クロック信号ＣＬ
Ｋと、調光用ＰＷＭ信号発生回路Ｂ３より生成される調
光用ＰＷＭ信号ＳＳ２が入力される。ＡＮＤゲートＧ４
には、クロック信号ＣＬＫと逆相のクロック信号ｈ２
と、調光用ＰＷＭ信号発生回路Ｂ３により生成される調
光用ＰＷＭ信号ＳＳ２が入力される。The clock signal CL is supplied to the AND gate G3.
K and the dimming PWM signal SS2 generated by the dimming PWM signal generation circuit B3 are input. AND gate G4
Includes a clock signal h2 having a phase opposite to that of the clock signal CLK.
And the dimming PWM signal SS2 generated by the dimming PWM signal generation circuit B3.
【００６４】そのため、調光用ＰＷＭ信号ＳＳ２がＨ
（ハイ）レベルの間、インバータトランスＴ３、Ｔ４の
１次巻線に接続されるスイッチング素子Ｑ３、Ｑ４がプ
ッシュプル駆動され、冷陰極管１２、１４はＰＷＭ調光
される。Therefore, the dimming PWM signal SS2 becomes H
During the (high) level, the switching elements Q3, Q4 connected to the primary windings of the inverter transformers T3, T4 are push-pull driven, and the cold cathode tubes 12, 14 are subjected to PWM dimming.
【００６５】以上説明したように、冷陰極管８、１０お
よび冷陰極管１２、１４は、単一のクロック信号ＣＬＫ
に同期して動作するため、それぞれの冷陰極管も同期し
て動作しチラツキが防止される。また、冷陰極管８、１
０と冷陰極管１２、１４とは別々の調光用ＰＷＭ信号に
より調光される。As described above, the cold cathode tubes 8, 10 and the cold cathode tubes 12, 14 are provided with a single clock signal CLK.
, The respective cold cathode tubes also operate in synchronism to prevent flicker. In addition, the cold cathode tubes 8, 1
0 and the cold cathode tubes 12 and 14 are dimmed by separate dimming PWM signals.
【００６６】冷陰極管８、１０は、調光用ＰＷＭ信号Ｓ
Ｓ１で調光され、冷陰極管１２、１４は、調光用ＰＷＭ
信号ＳＳ２で調光されるため独立に調光することができ
る。この調光用ＰＷＭ信号発生回路は、調光したい冷陰
極管の数量に対応して複数個設けても良い。もしくはい
くつかの冷陰極管を組合わせたグループの数に対応し
て、複数個用意しても良い。また各々の冷陰極管を独立
に調光させる必要がない場合は、調光用ＰＷＭ信号発生
回路を一つで構成し、各ＡＮＤゲートの入力に接続す
る。The cold-cathode tubes 8 and 10 receive a PWM signal S for dimming.
The dimming is performed in S1, and the cold cathode fluorescent lamps 12 and 14 are dimmed PWM.
Since the dimming is performed by the signal SS2, the dimming can be performed independently. The PWM signal generating circuit for dimming may be provided in a plurality corresponding to the number of cold cathode tubes to be dimmed. Alternatively, a plurality of cold-cathode tubes may be prepared in accordance with the number of groups. If it is not necessary to dimming each cold-cathode tube independently, a single dimming PWM signal generating circuit is formed and connected to the input of each AND gate.
【００６７】実装基板６上の他励発振出力回路３２は、
実装基板４の他励発振出力回路２６と同様の動作をす
る。この実装基板６の他励発振出力回路３２へ、実装基
板４の制御回路から、１次側電源電位Ｖｃｃ、接地ＧＮ
Ｄ、クロック発生回路Ｂ１で生成されたクロック信号Ｃ
ＬＫ、調光用ＰＷＭ信号発生回路Ｂ２で生成された調光
用ＰＷＭ信号ＳＳ１、調光用ＰＷＭ信号発生回路Ｂ３で
生成された調光用ＰＷＭ信号ＳＳ２がコネクタ等の接続
手段を介して伝達される。The separately excited oscillation output circuit 32 on the mounting board 6
The same operation as the separately excited oscillation output circuit 26 of the mounting board 4 is performed. From the control circuit of the mounting substrate 4 to the separately excited oscillation output circuit 32 of the mounting substrate 6,
D, clock signal C generated by clock generation circuit B1
LK, the dimming PWM signal SS1 generated by the dimming PWM signal generation circuit B2, and the dimming PWM signal SS2 generated by the dimming PWM signal generation circuit B3 are transmitted through connection means such as a connector. You.
【００６８】そのため、実装基板６の他励発振出力回路
３２は、実装基板４の他励発振出力回路２６と同じ制御
回路の単一のクロック信号ＣＬＫで発振周波数が制御さ
れるため、実装基板４と実装基板６のインバータトラン
スＴ１〜Ｔ８にそれぞれ接続された冷陰極管１〜８は同
期して動作しチラツキが防止される。The oscillation frequency of the separately-excited oscillation output circuit 32 of the mounting board 6 is controlled by a single clock signal CLK of the same control circuit as that of the separately-excited oscillation output circuit 26 of the mounting board 4. The cold cathode tubes 1 to 8 connected to the inverter transformers T1 to T8 of the mounting board 6 operate in synchronization with each other to prevent flicker.
【００６９】また、実装基板６のインバータトランスＴ
５、Ｔ６は、調光用ＰＷＭ信号ＳＳ１で調光され、イン
バータトランスＴ７、Ｔ８は、調光用ＰＷＭ信号ＳＳ２
で調光される。したがって、実装基板４に接続された冷
陰極管８、１０と実装基板６に接続された冷陰極管１
６、１８とは同じ調光制御がされ、実装基板４に接続さ
れた冷陰極管１２、１４と実装基板６に接続された冷陰
極管２０、２２とは同じ調光制御がされる。The inverter transformer T of the mounting board 6
5, T6 is dimmed by the dimming PWM signal SS1, and the inverter transformers T7, T8 are dimmed by the dimming PWM signal SS2.
Is dimmed. Therefore, the cold cathode tubes 8 and 10 connected to the mounting substrate 4 and the cold cathode tubes 1 connected to the mounting substrate 6
The same dimming control is performed on the cold cathode tubes 6 and 18 and the same dimming control is performed on the cold cathode tubes 12 and 14 connected to the mounting board 4 and the cold cathode tubes 20 and 22 connected to the mounting board 6.
【００７０】なお、実装基板４、６間を接続する信号に
保護回路等の信号があれば随時追加しても良い。It should be noted that if there is a signal of a protection circuit or the like as a signal connecting between the mounting boards 4 and 6, it may be added as needed.
【００７１】再び、図１を参照して、４辺に２灯ずつ配
置された冷陰極管のバックライトに対し、複数の他励式
インバータを小信号ラインと１次側電源電位のみの接続
で実装基板を分割している。したがって、安全性・信頼
性の向上を図りながらノイズの抑制ができる。Referring again to FIG. 1, a plurality of separately-excited inverters are mounted on the backlights of the cold-cathode tubes arranged on each of the four sides by connecting only the small signal line and the primary-side power supply potential. The substrate is divided. Therefore, noise can be suppressed while improving safety and reliability.
【００７２】同時に、実装基板４を冷陰極管８〜１４に
対し近接させ、実装基板６を冷陰極管１６〜２２に対し
て近接させたバックライトユニットの構造配置にするこ
とにより、インバータトランスの２次側巻線の高電圧配
線側を各冷陰極管の電極に最短で配線することができ
る。At the same time, by mounting the mounting substrate 4 close to the cold cathode tubes 8 to 14 and the mounting substrate 6 close to the cold cathode tubes 16 to 22, the backlight unit is arranged in a structural arrangement. The high voltage wiring side of the secondary winding can be wired to the electrode of each cold cathode tube in the shortest possible time.
【００７３】このように実装基板を分割し高電圧配線側
を最短にすることができるので、安全性・信頼性の向上
を図りながら、配線浮遊容量や接地された導体に対する
リーク電流の低減による低消費電力化が実現できる。As described above, since the mounting substrate can be divided and the high-voltage wiring side can be minimized, the safety and reliability can be improved, and the floating stray capacitance and the leakage current to the grounded conductor can be reduced. Power consumption can be realized.
【００７４】また、出力の高電圧配線を同じ程度に短い
配線長にすることで各々の冷陰極管に対するリーク電流
のアンバランスが小さくなり液晶表示装置としての輝度
バランスが改善される。Further, by making the output high-voltage wires as short as possible, the imbalance of the leak current to each cold-cathode tube is reduced, and the luminance balance as a liquid crystal display device is improved.
【００７５】以上、本発明を実施例に基づき具体的に説
明したが、その要旨を逸脱しない範囲で変更可能であ
る。例えば、本実施の形態では実装基板を実装基板１、
２と２枚に分割しているが、実装基板２を実装基板３、
４・・・と、３枚以上とし、各実装基板間を１次側電源
電位、小信号ラインを接続した構成であっても良い。As described above, the present invention has been specifically described based on the embodiments. However, the present invention can be modified without departing from the gist thereof. For example, in the present embodiment, the mounting substrate is the mounting substrate 1,
2 and two, but the mounting substrate 2 is
4... And three or more, and a primary power supply potential and a small signal line may be connected between the mounting boards.
【００７６】また、実施例の図２に示す実装基板４の制
御回路２４と、他励発振出力回路２６の実装基板を分割
しても良い。制御回路基板を別にすることで、複数の別
基板に実装された他励発振出力回路は同じ基板を使用す
ることができる。The control circuit 24 of the mounting board 4 shown in FIG. 2 of the embodiment and the mounting board of the separately excited oscillation output circuit 26 may be divided. By separately providing the control circuit board, the separately excited oscillation output circuit mounted on a plurality of separate boards can use the same board.
【００７７】このように実装基板を容易に分割できるの
で、液晶表示装置における大画面、高輝度化に伴い複数
の冷陰極管を多様な冷陰極管配置にする際に構造設計の
簡易化と実装基板の小型化・軽量化に伴うコスト低減を
図ることができる。Since the mounting substrate can be easily divided in this manner, when a plurality of cold cathode tubes are arranged in various cold cathode tubes in accordance with a large screen and high brightness in the liquid crystal display device, the structure can be simplified and the mounting can be simplified. Cost reduction accompanying downsizing and weight reduction of the substrate can be achieved.
【００７８】今回開示された実施の形態はすべての点で
例示であって制限的なものではないと考えられるべきで
ある。本発明の範囲は上記した説明ではなくて特許請求
の範囲によって示され、特許請求の範囲と均等の意味お
よび範囲内でのすべての変更が含まれることが意図され
る。The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
【００７９】[0079]
【発明の効果】請求項１、２に記載のバックライトユニ
ットは、多様な冷陰極管配置かつ複数の冷陰極管に対
し、安全性・信頼性の向上、ノイズの抑制、リーク電流
の増加防止に伴う低消費電力化を実現することができ
る。According to the backlight unit of the present invention, safety and reliability can be improved, noise can be suppressed, and leak current can be prevented from increasing in a variety of cold-cathode tube arrangements and a plurality of cold-cathode tubes. , Low power consumption can be realized.
【００８０】請求項３に記載のバックライトユニット
は、請求項１に記載のバックライトユニットの奏する効
果に加えて、基板を２分割した場合に安全性・信頼性の
向上、ノイズの抑制、リーク電流の増加防止に伴う低消
費電力化を実現することができる。According to the backlight unit of the third aspect, in addition to the effects of the backlight unit of the first aspect, when the substrate is divided into two, the safety / reliability is improved, noise is suppressed, and leakage is reduced. It is possible to realize low power consumption accompanying prevention of an increase in current.
【００８１】請求項４に記載のバックライトユニット
は、請求項１に記載のバックライトユニットの奏する効
果に加え、１つの冷陰極管ごとにインバータトランスを
設けるので、各冷陰極管ごとに明るさ等の調整ができ
る。According to the backlight unit of the fourth aspect, in addition to the effect of the backlight unit of the first aspect, since an inverter transformer is provided for each cold cathode tube, the brightness of each cold cathode tube is increased. Etc. can be adjusted.
【００８２】請求項５、６に記載の液晶表示装置は、多
様な冷陰極管配置かつ複数の冷陰極管に対し、安全性・
信頼性の向上、ノイズの抑制、リーク電流の増加防止に
伴う低消費電力化を実現することができる。The liquid crystal display device according to the fifth and sixth aspects of the present invention can provide various cold-cathode tube arrangements and a plurality of
It is possible to achieve improvement in reliability, suppression of noise, and reduction in power consumption due to prevention of increase in leak current.
【００８３】請求項７に記載の液晶表示装置は、請求項
５に記載の液晶表示装置の奏する効果に加えて、基板を
２分割した場合に安全性・信頼性の向上、ノイズの抑
制、リーク電流の増加防止に伴う低消費電力化を実現す
ることができる。According to the liquid crystal display device of the seventh aspect, in addition to the effects of the liquid crystal display device of the fifth aspect, when the substrate is divided into two, the safety and reliability are improved, noise is suppressed, and leakage is reduced. It is possible to realize low power consumption accompanying prevention of an increase in current.
【００８４】請求項８に記載の液晶表示装置は、請求項
５に記載の液晶表示装置の奏する効果に加え、１つの冷
陰極管ごとにインバータトランスを設けるので、各冷陰
極管ごとに明るさ等の調整ができる。In the liquid crystal display device according to the eighth aspect, in addition to the effect of the liquid crystal display device according to the fifth aspect, since an inverter transformer is provided for each cold cathode tube, the brightness of each cold cathode tube is increased. Etc. can be adjusted.
【００８５】請求項９に記載の液晶表示装置は、請求項
５に記載の液晶表示装置の奏する効果に加えて、液晶パ
ネルが四角形の場合に、離れた配置となる対向する辺に
対応して設けられる２つの冷陰極管にそれぞれ対応して
基板を分割配置できるので、高電圧パルスの印可される
配線を短くすることができる。したがって、出力の高電
圧配線を同じ程度に短い配線長にすることで各々の冷陰
極管に対するリーク電流のアンバランスが小さくなり液
晶表示装置としての輝度バランスが改善される。According to the liquid crystal display device of the ninth aspect, in addition to the effects of the liquid crystal display device of the fifth aspect, when the liquid crystal panel is a quadrangle, the liquid crystal display device corresponds to opposing sides that are separated from each other. Since the substrates can be divided and arranged corresponding to the two provided cold cathode tubes, the wiring to which the high voltage pulse is applied can be shortened. Accordingly, by making the output high-voltage wires as short as possible, the imbalance of the leak current with respect to each cold-cathode tube is reduced, and the luminance balance as a liquid crystal display device is improved.
【図１】 本発明の実施の形態に係る液晶表示装置１の
構成を概略的に示す平面構造図である。FIG. 1 is a plan view schematically showing a configuration of a liquid crystal display device 1 according to an embodiment of the present invention.
【図２】 図１に示した実装基板４、６の詳細な構成を
示す回路図である。FIG. 2 is a circuit diagram showing a detailed configuration of mounting boards 4 and 6 shown in FIG.
【図３】 インバータトランスの出力を複数にする従来
例を示す回路図である。FIG. 3 is a circuit diagram showing a conventional example in which an inverter transformer has a plurality of outputs.
【図４】 図３に示した実装基板１００のインバータト
ランスの１次側のロイヤー発振回路を共通化し、基板を
分割した例を示した回路図である。4 is a circuit diagram showing an example in which a lower-layer oscillation circuit on the primary side of the inverter transformer of the mounting board 100 shown in FIG. 3 is shared and the board is divided.
１ 液晶表示装置、２ 液晶パネル、８〜２２ 冷陰極
管、４，６ 実装基板、２４ 制御回路、２６，３２
他励発振出力回路、２８，３０，３４ コネクタ、Ｂ１
クロック発生回路、Ｂ２，Ｂ３ 調光用ＰＷＭ信号発
生回路、Ｆ１〜Ｆ５ ヒューズ、Ｌ１〜Ｌ４ コイル、
Ｇ９〜Ｇ１２ インバータゲート、Ｇ１〜Ｇ８ ＡＮＤ
ゲート、Ｑ１〜Ｑ８ 電界効果形トランジスタ、Ｃ１〜
Ｃ４ キャパシタ、Ｔ１〜Ｔ８ インバータトランス、
Ｃ５〜Ｃ１２ バラストコンデンサ。DESCRIPTION OF SYMBOLS 1 Liquid crystal display device, 2 liquid crystal panel, 8-22 cold-cathode tube, 4,6 mounting board, 24 control circuit,
Separately-excited oscillation output circuit, 28, 30, 34 connector, B1
Clock generation circuit, B2, B3 dimming PWM signal generation circuit, F1 to F5 fuses, L1 to L4 coil,
G9-G12 Inverter gate, G1-G8 AND
Gate, Q1-Q8 Field-effect transistor, C1-
C4 capacitor, T1-T8 inverter transformer,
C5 to C12 ballast capacitors.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） // Ｈ０５Ｂ 41/02 Ｈ０５Ｂ 41/02 Ｚ (72)発明者 大浦 久治 熊本県菊池郡西合志町御代志997番地 株 式会社アドバンスト・ディスプレイ内 Ｆターム(参考） 3K072 AA01 AA19 AB02 BA03 BC03 BC07 GA02 GB14 GC04 HA10 HB03 3K098 CC07 CC41 CC56 CC57 DD01 DD22 DD37 DD45 EE14 EE31 5H007 AA00 BB03 CA02 CB01 CB04 CB06 CC32 EA02 HA04 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) // H05B 41/02 H05B 41/02 Z (72) Inventor Hisaharu Oura 997 Miyoshi, Nishigoshi-cho, Kikuchi-gun, Kumamoto Prefecture F-term in the Advanced Display Co., Ltd. (reference)
Claims (9)
ライトユニットであって、 前記複数の冷陰極管は、複数の群に分割され、 第１の電源電位と前記第１の電源電位より高い第２の電
源電位を受けてクロック信号と制御信号とを出力する制
御回路と、 前記複数の群にそれぞれ対応して設けられ、前記クロッ
ク信号および前記制御信号に応じて前記冷陰極管を駆動
する高電圧パルスを発生する複数の冷陰極管駆動回路
と、 前記複数の冷陰極管駆動回路にそれぞれ対応して設けら
れる複数の実装基板とを備える、バックライトユニッ
ト。1. A backlight unit for lighting a plurality of cold-cathode tubes, wherein the plurality of cold-cathode tubes are divided into a plurality of groups, and a first power supply potential and a first power supply potential A control circuit that receives a high second power supply potential and outputs a clock signal and a control signal, and is provided corresponding to each of the plurality of groups, and drives the cold-cathode tube according to the clock signal and the control signal A backlight unit, comprising: a plurality of cold-cathode tube driving circuits for generating a high-voltage pulse;
振幅は、前記第１の電源電位と前記第２の電源電位との
電位差以下であり、 前記高電圧パルスの振幅は、前記第１の電源電位と前記
第２の電源電位との電位差より大きい、請求項１に記載
のバックライトユニット。2. An amplitude of the control signal and the clock signal is equal to or less than a potential difference between the first power supply potential and the second power supply potential, and an amplitude of the high voltage pulse is equal to the first power supply potential. 2. The backlight unit according to claim 1, wherein the backlight unit is larger than a potential difference between the first power supply potential and the second power supply potential.
板から前記第２の実装基板へと伝達する配線群をさらに
備える、請求項１に記載のバックライトユニット。3. The plurality of mounting boards include first and second mounting boards, the control circuit is mounted on the first mounting board, and the control circuit transmits the control signal and the clock signal to the first mounting board. The backlight unit according to claim 1, further comprising: a wiring group that transmits from the mounting board to the second mounting board.
れ対応する複数のインバータトランスを含む、請求項１
に記載のバックライトユニット。4. The cold-cathode tube driving circuit includes a plurality of inverter transformers respectively corresponding to the plurality of cold-cathode tubes included in the corresponding group.
The backlight unit according to item 1.
極管と、 第１の電源電位と前記第１の電源電位より高い第２の電
源電位を受けてクロック信号と制御信号とを出力する制
御回路とを備え、 前記複数の冷陰極管は、複数の群に分割され、 前記複数の群にそれぞれ対応して設けられ、前記クロッ
ク信号および前記制御信号に応じて前記冷陰極管を駆動
する高電圧パルスを発生する複数の冷陰極管駆動回路
と、 前記複数の冷陰極管駆動回路にそれぞれ対応して設けら
れる複数の実装基板とをさらに備える、液晶表示装置。5. A liquid crystal panel, a plurality of cold cathode tubes used for a backlight of the liquid crystal panel, and a clock signal receiving a first power supply potential and a second power supply potential higher than the first power supply potential. And a control circuit for outputting a control signal. The plurality of cold cathode tubes are divided into a plurality of groups, provided in correspondence with the plurality of groups, respectively, and according to the clock signal and the control signal. A liquid crystal display device further comprising: a plurality of cold cathode tube driving circuits for generating a high voltage pulse for driving the cold cathode tube; and a plurality of mounting substrates provided respectively corresponding to the plurality of cold cathode tube driving circuits.
振幅は、前記第１の電源電位と前記第２の電源電位との
電位差以下であり、 前記高電圧パルスの振幅は、前記第１の電源電位と前記
第２の電源電位との電位差より大きい、請求項５に記載
の液晶表示装置。6. An amplitude of the control signal and the clock signal is equal to or less than a potential difference between the first power supply potential and the second power supply potential, and an amplitude of the high voltage pulse is equal to the first power supply potential. The liquid crystal display device according to claim 5, wherein the potential difference is larger than a potential difference between the first power supply potential and the second power supply potential.
板から前記第２の実装基板へと伝達する配線群をさらに
備える、請求項５に記載の液晶表示装置。7. The plurality of mounting boards include first and second mounting boards, wherein the control circuit is mounted on the first mounting board, and controls the control signal and the clock signal in the first mounting board. The liquid crystal display device according to claim 5, further comprising: a group of wirings that transmits from the mounting substrate to the second mounting substrate.
れ対応する複数のインバータトランスを含む、請求項５
に記載の液晶表示装置。8. The cold cathode tube driving circuit includes a plurality of inverter transformers respectively corresponding to the plurality of cold cathode tubes included in the corresponding group.
3. The liquid crystal display device according to 1.
して設けられる第１の冷陰極管は、前記第１の実装基板
から前記高電圧パルスを受け、 前記複数の冷陰極管のうち前記第１の辺に対向する前記
四角形の第２の辺に対応して設けられる第２の冷陰極管
は、前記第２の実装基板から前記高電圧パルスを受け
る、請求項５に記載の液晶表示装置。9. The liquid crystal panel has a quadrangular shape, the plurality of mounting substrates include first and second mounting substrates, and a first side of the square among the plurality of cold cathode tubes. A first cold-cathode tube provided correspondingly receives the high-voltage pulse from the first mounting board, and the second side of the quadrilateral facing the first side of the plurality of cold-cathode tubes The liquid crystal display device according to claim 5, wherein a second cold-cathode tube provided corresponding to (c) receives the high-voltage pulse from the second mounting substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28400099A JP4071405B2 (en) | 1999-10-05 | 1999-10-05 | Liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28400099A JP4071405B2 (en) | 1999-10-05 | 1999-10-05 | Liquid crystal display |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2001110582A true JP2001110582A (en) | 2001-04-20 |
| JP2001110582A5 JP2001110582A5 (en) | 2006-01-05 |
| JP4071405B2 JP4071405B2 (en) | 2008-04-02 |
Family
ID=17673005
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28400099A Expired - Fee Related JP4071405B2 (en) | 1999-10-05 | 1999-10-05 | Liquid crystal display |
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| Country | Link |
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