JP2001044142A - Method of cutting silicon wafer - Google Patents

Method of cutting silicon wafer

Info

Publication number
JP2001044142A
JP2001044142A JP21361399A JP21361399A JP2001044142A JP 2001044142 A JP2001044142 A JP 2001044142A JP 21361399 A JP21361399 A JP 21361399A JP 21361399 A JP21361399 A JP 21361399A JP 2001044142 A JP2001044142 A JP 2001044142A
Authority
JP
Japan
Prior art keywords
silicon wafer
tape
cutting
protective tape
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21361399A
Other languages
Japanese (ja)
Inventor
Takashi Hosaka
俊 保坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP21361399A priority Critical patent/JP2001044142A/en
Publication of JP2001044142A publication Critical patent/JP2001044142A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)

Abstract

PROBLEM TO BE SOLVED: To protect a silicon wafer from breaking when the protection tape is peeled by attaching a protection tape for grinding the rear surface to the front surface and then grinding the rear surface while the protection tape is adhered. SOLUTION: A protection tape 12 for processing the rear surface is adhered (a) to the front surface of a silicon wafer 11. This protection tape 12 is a transparent tape. Next, the rear surface of the silicon wafer 11 is ground using a rear surface grinding apparatus to obtain the silicon wafer 11a of the desired thickness (b). Next, while the transparent protection tape 12 is adhered, the rear surface of the silicon wafer 11a is adhered to a dicing tape 13 held with a dicing ring 14 (c). Next, the patterns of semiconductor devices and scribe lines on the surface of the silicon wafer 11a are read from over the transparent protection tape 12 and a semiconductor chip 15 including the predetermined pattern is cut and isolated by inserting a blade end point from the transparent protection tape 12.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【発明の属する技術分野】本発明はシリコンウエハの切
断方法に関する。The present invention relates to a method for cutting a silicon wafer.

【従来の技術】従来のシリコンウエハの裏面研削（バッ
クグラインド、以下「ＢＧ」と略する）からシリコンウ
エハの切断方法を図２（ａ）、図２（ｂ）に示す。従
来、図２(ａ)に示すように、シリコンウエハ２１の半導
体素子のある側（これを以下「シリコンウエハの表面」
と称する）にＢＧする時の保護テープ２２を貼る。次に
図２(ｂ)に示すように裏面研削装置を用いシリコンウエ
ハ２１の半導体素子のない側（これを以下「シリコンウ
エハの裏面」と称する）を削り、所望の厚みのシリコン
ウエハ２１ａを得る。次に、図２(ｃ)に示すように保護
テープ２２を剥がす。次に、図２(ｄ)に示すようにシリ
コンウエハ２１ａの裏面にダイシングテープ２３を貼
る。ダイシングテープ２３は、ダイシングリング２４に
より保持されているが、ダイシングリング２４は無くて
も良い。次に、図２(ｅ)に示すようにダイシング装置を
用い、シリコンウエハ２１ａの表面から刃を入れてシリ
コンウエハ２１ａを所望のパターンに沿って切断し、半
導体チップ２５を得る。2. Description of the Related Art FIGS. 2 (a) and 2 (b) show a conventional method of cutting a silicon wafer from back grinding (back grinding, hereinafter abbreviated as "BG"). Conventionally, as shown in FIG. 2A, a side of a silicon wafer 21 on which a semiconductor element is provided (hereinafter referred to as a “surface of a silicon wafer”).
Protective tape 22 for BG is applied. Next, as shown in FIG. 2 (b), the side of the silicon wafer 21 without the semiconductor elements (hereinafter referred to as the "backside of the silicon wafer") is shaved using a backside grinding device to obtain a silicon wafer 21a having a desired thickness. . Next, the protective tape 22 is peeled off as shown in FIG. Next, as shown in FIG. 2D, a dicing tape 23 is attached to the back surface of the silicon wafer 21a. Although the dicing tape 23 is held by the dicing ring 24, the dicing ring 24 may not be provided. Next, as shown in FIG. 2E, using a dicing apparatus, a blade is inserted from the surface of the silicon wafer 21a, and the silicon wafer 21a is cut along a desired pattern to obtain a semiconductor chip 25.

【発明が解決しようとする課題】半導体素子を有するチ
ップ（以下、半導体チップと称する）の厚みは、薄くな
ってきている。例えば、ＩＣカードに搭載する半導体チ
ップの厚みは１００μｍ以下の厚みが要求されてきてい
る。当然、半導体チップの集合体であるシリコンウエハ
の厚みも、１００μｍ以下が要求されるため、図２(ｂ)
において、シリコンウエハ２１ａの厚みは１００μｍ以
下となる。ところが、図２(ｃ)において、１００μｍ以
下となったシリコンウエハ２１ａと保護テープ２２を分
離する事は非常に困難で、保護テープ２２を剥がす時に
シリコンウエハ２１ａが割れてしまう。仮に、この段階
で上手にシリコンウエハ２１ａと保護テープ２３を分離
したとしても、図２(ｄ)に示すダイシングテープ２３を
貼り終えるまでに、薄くなったシリコンウエハ２１ａを
割らずに処理する事も非常に困難である。The thickness of a chip having a semiconductor element (hereinafter referred to as a semiconductor chip) has been reduced. For example, a semiconductor chip mounted on an IC card is required to have a thickness of 100 μm or less. Naturally, the thickness of the silicon wafer, which is an aggregate of semiconductor chips, is also required to be 100 μm or less.
, The thickness of the silicon wafer 21a is 100 μm or less. However, in FIG. 2C, it is very difficult to separate the protection tape 22 from the silicon wafer 21a having a thickness of 100 μm or less, and the silicon wafer 21a breaks when the protection tape 22 is peeled off. Even if the silicon wafer 21a and the protective tape 23 are well separated at this stage, the processing may be performed without breaking the thinned silicon wafer 21a by the time the dicing tape 23 shown in FIG. Very difficult.

【課題を解決するための手段】上記の問題点を解決する
ために、本発明はＢＧ用の保護テープを表面に貼り、保
護テープを貼ったままＢＧを行なった後、保護テープを
剥がさずにシリコンウエハの裏面をダイシングテープに
貼りつけ、その後、保護テープを剥がすようにした。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention applies a BG protective tape to the surface, performs BG with the protective tape attached, and does not peel off the protective tape. The back surface of the silicon wafer was attached to a dicing tape, and then the protective tape was peeled off.

【発明の実施の形態】本発明は、薄くなって割れやすい
シリコンウエハの半導体保護チップのダイシング方法を
提供するものである。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides a method for dicing a semiconductor protection chip of a silicon wafer which is thin and easily cracked.

【実施例１】図１は、本発明の第１の実施例を示す。図
１(ａ)に示すように、シリコンウエハ１１の表面にＢＧ
用の保護テープ１２を貼る。この保護テープ１２は、透
明のテープである。ここで言う「透明」とは、ダイシン
グ時にシリコンウエハのスクライブラインのパターンを
この透明の保護テープを介して装置が読み取ることがで
きるという意味である。次に図１(ｂ)に示すように、裏
面研削装置を用いてシリコンウエハ１１の裏面を研削し
所望の厚みのシリコンウエハ１１ａを得る。次に図１
(ｃ)に示すように、透明の保護テープ１２を貼りつけた
ままシリコウエハ１１ａの裏面を、ダイシングリング１
４に保持されたダイシングテープ１３に貼りつける。次
に図１(ｄ)に示すように、透明の保護テープ１２の上か
らシリコンウエハ１１ａの表面にある半導体素子および
スクライブラインなどのパターンを読み取り、透明の保
護テープ１２から刃先を入れ所望のパターンの入った半
導体チップ１５を切断分離する。Embodiment 1 FIG. 1 shows a first embodiment of the present invention. As shown in FIG. 1A, the surface of the silicon wafer 11 is BG
A protective tape 12 for use. This protective tape 12 is a transparent tape. The term "transparent" as used herein means that the apparatus can read the pattern of the scribe line of the silicon wafer at the time of dicing via the transparent protective tape. Next, as shown in FIG. 1B, the back surface of the silicon wafer 11 is ground using a back surface grinding device to obtain a silicon wafer 11a having a desired thickness. Next, FIG.
As shown in (c), the back surface of the silicon wafer 11a is fixed to the dicing ring 1 with the transparent protective tape 12 adhered thereto.
4 is attached to the dicing tape 13 held. Next, as shown in FIG. 1 (d), a pattern of semiconductor elements and scribe lines on the surface of the silicon wafer 11a is read from above the transparent protective tape 12, and a cutting edge is inserted from the transparent protective tape 12 to obtain a desired pattern. Is cut and separated.

【実施例２】図３は、本発明の第２の実施例を示す。図
３(ａ)に示すように、シリコンウエハ３１の表面にＢＧ
用の保護テープ３２を貼る。次に図３(ｂ)に示すよう
に、裏面研削装置を用いてシリコンウエハ３１の裏面を
研削し所望の厚みのシリコンウエハ３１ａを得る。次に
図３(ｃ)に示すように、保護テープ３２を貼りつけたま
まシリコウエハ３１ａの裏面を、ダイシングリング３４
に保持されたダイシングテープ３３に貼りつける。次に
図３(ｄ)に示すように、保護テープ３２を剥がす。シリ
コンウエハ３１ａに対して、ダイシングテープ３３より
保護テープ３２の方の粘着力を弱くしておく事で、保護
テープ３２を容易に剥がす事ができる。また、ＢＧ用の
保護テープ３２に紫外線照射により粘着力を弱める事が
できる紫外線照射テープを用い、図３(ｂ)すなわちシリ
コンウエハ３１の裏面を研削した後に紫外線照射を行
い、シリコンウエハ３１ａと保護テープ３２の粘着力を
弱める事もできる。ここで、紫外線照射を行う時期であ
るが、ダイシングテープ３３にやはり紫外線照射により
粘着力を弱める事ができる紫外線照射テープ(以下「ダ
イシング用ＵＶテープ」と述べる)を用いた場合は、図
３(ｃ)に示すダイシングテープ３３を貼りつける前に紫
外線照射を行う必要がある。ダイシングテープ３３を貼
りつけた後に紫外線照射を行えば 、ダイシング用ＵＶ
テープの粘着力も弱くなるからである。ダイシングテー
プ３３にダイシング用ＵＶテープを用いなければ、紫外
線照射を行う時期は、ダイシングテープ３３を貼る前で
も良いし、ダイシングテープ３３を貼った後でも良い。
次に図３(ｅ)に示すように、シリコンウエハ３１ａの表
から刃先を入れ所望のパターンの入った半導体チップ３
５を切断分離する。Embodiment 2 FIG. 3 shows a second embodiment of the present invention. As shown in FIG. 3A, BG is
A protective tape 32 for use. Next, as shown in FIG. 3B, the back surface of the silicon wafer 31 is ground using a back surface grinding device to obtain a silicon wafer 31a having a desired thickness. Next, as shown in FIG. 3 (c), the back surface of the silicon wafer 31a is
Is attached to the dicing tape 33 held in the above. Next, as shown in FIG. 3D, the protective tape 32 is peeled off. By making the adhesive strength of the protective tape 32 weaker than that of the dicing tape 33 with respect to the silicon wafer 31a, the protective tape 32 can be easily peeled off. FIG. 3 (b), that is, the back surface of the silicon wafer 31 is ground and then irradiated with ultraviolet light to protect the silicon wafer 31a. The adhesive strength of the tape 32 can be reduced. Here, it is time to perform the ultraviolet irradiation. When an ultraviolet irradiation tape (hereinafter, referred to as “UV tape for dicing”) is used for the dicing tape 33, the adhesive strength of which can also be reduced by the ultraviolet irradiation, FIG. It is necessary to perform ultraviolet irradiation before the dicing tape 33 shown in c) is attached. If UV irradiation is performed after the dicing tape 33 is attached, UV for dicing can be obtained.
This is because the adhesive strength of the tape is also weakened. If a UV tape for dicing is not used for the dicing tape 33, the ultraviolet irradiation may be performed before the dicing tape 33 is applied or after the dicing tape 33 is applied.
Next, as shown in FIG. 3E, a semiconductor chip 3 having a desired pattern is inserted from the front surface of the silicon wafer 31a.
5 is cut and separated.

【効果】以上説明したように、シリコンウエハが薄くな
った後は、シリコンウエハに対してＢＧ用保護テープま
たはダイシングテープがシリコンウエハに貼りついてい
るので、シリコンウエハが割れる事はない。すなわち、
薄くなったシリコンウエハの補強をＢＧ用保護テープま
たはダイシングテープが果たしている。実施例では、シ
リコンウエハについて説明したが、他の基板の切断に関
しても同様の方法を使うことができることはいうまでも
ない。As described above, after the silicon wafer is thinned, the silicon wafer is not broken because the BG protection tape or the dicing tape is attached to the silicon wafer. That is,
The protection tape for BG or the dicing tape plays the role of reinforcing the thinned silicon wafer. Although a silicon wafer has been described in the embodiment, it goes without saying that the same method can be used for cutting other substrates.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明のシリコンウエハの研削および個片切断
の第１の実施例を示す図である。FIG. 1 is a view showing a first embodiment of grinding and cutting individual pieces of a silicon wafer according to the present invention.

【図２】従来のシリコンウエハの研削および個片切断の
方法を示す図である。FIG. 2 is a diagram showing a conventional method of grinding and cutting individual pieces of a silicon wafer.

【図３】本発明のシリコンウエハの研削および個片切断
の第２の実施例を示す図である。FIG. 3 is a view showing a second embodiment of grinding and individual cutting of a silicon wafer according to the present invention.

【符号の説明】[Explanation of symbols]

１１、１１ａ、２１、２１ａ、３１、３１ａ シリコ
ンウエハ（基板） １２、２２、３２ ＢＧ用保護テープ １３、２３、３３ ダイシングテープ １４、２４、３４ ダイシングリング １５、２５、３５ 半導体チップ11, 11a, 21, 21a, 31, 31a Silicon wafer (substrate) 12, 22, 32 BG protection tape 13, 23, 33 Dicing tape 14, 24, 34 Dicing ring 15, 25, 35 Semiconductor chip

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 所望の厚みまで研削し、その後個片に切
断する基板において、 研削する面と反対の面に裏面研削保護用の保護テープを
貼る工程と、 裏面研削装置を用いて研削する工程を有するシリコンウ
エハの切断方法。1. A step of applying a protective tape for backside grinding protection to a surface opposite to a surface to be ground on a substrate to be ground to a desired thickness and then cutting into pieces, and a step of grinding using a backside grinding device. A method for cutting a silicon wafer, comprising: 【請求項２】 所望の厚みまで研削し、その後個片に切
断する基板において、 研削する面と反対の面に裏面研削保護用の透明保護テー
プを貼る工程と、 裏面研削装置を用いて研削する工程と、 透明保護テープを貼りつけたまま個片切断用のテープに
研削された面を貼りつける工程と、 透明保護テープの上から基板のパターンを読み取り、透
明保護テープから基板を個片に切断する工程とを有する
シリコンウエハの切断方法。2. A step of applying a transparent protective tape for protecting the back surface on the surface opposite to the surface to be ground on a substrate to be ground to a desired thickness and then cutting into individual pieces, and grinding using a back surface grinding device. The process of attaching the ground surface to the tape for cutting individual pieces while attaching the transparent protective tape, and reading the pattern of the substrate from above the transparent protective tape and cutting the substrate into individual pieces from the transparent protective tape And a step of cutting the silicon wafer. 【請求項３】 所望の厚みまで研削し、その後個片に切
断する基板において、 研削する面と反対の面に裏面研削保護用の保護テープを
貼る工程と、 裏面研削装置を用いて研削する工程と、 保護テープを貼りつけたまま個片切断用のテープに研削
された面を貼りつける工程と、 個片切断用のテープを裏面に貼りつけた状態で表面に貼
りつけた保護テープを剥がす工程と基板を個片に切断す
る工程とを有するシリコンウエハの切断方法。3. A step of applying a protective tape for backside grinding protection to a surface opposite to a surface to be ground on a substrate to be ground to a desired thickness and then cutting into pieces, and a step of grinding using a backside grinding device. And a step of attaching the ground surface to the tape for cutting individual pieces with the protective tape still attached, and a step of peeling off the protective tape attached to the front face with the tape for cutting individual pieces attached to the back face And a step of cutting the substrate into individual pieces. 【請求項４】 裏面研削保護用の保護テープと基板との
粘着力は、個片切断用のテープと基板との粘着力よりも
弱い第３項記載のシリコンウエハの切断方法4. The method for cutting a silicon wafer according to claim 3, wherein the adhesive force between the protective tape for back surface grinding protection and the substrate is weaker than the adhesive force between the tape for cutting individual pieces and the substrate. 【請求項５】 裏面研削保護用の保護テープは紫外線照
射により粘着力を弱める事のできるテープを用い、基板
を裏面研削した後に、基板に貼りつけた裏面研削用の保
護テープに紫外線照射を行う工程を付加する第３項記載
のシリコンウエハの切断方法。5. A protective tape for backside grinding protection is a tape whose adhesive strength can be weakened by irradiating ultraviolet rays, and after irradiating the backside of the substrate, irradiating the protective tape for backside grinding attached to the substrate with ultraviolet rays. 4. The method for cutting a silicon wafer according to claim 3, wherein a step is added.
JP21361399A 1999-07-28 1999-07-28 Method of cutting silicon wafer Pending JP2001044142A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21361399A JP2001044142A (en) 1999-07-28 1999-07-28 Method of cutting silicon wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21361399A JP2001044142A (en) 1999-07-28 1999-07-28 Method of cutting silicon wafer

Publications (1)

Publication Number Publication Date
JP2001044142A true JP2001044142A (en) 2001-02-16

Family

ID=16642086

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21361399A Pending JP2001044142A (en) 1999-07-28 1999-07-28 Method of cutting silicon wafer

Country Status (1)

Country Link
JP (1) JP2001044142A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003060972A1 (en) * 2002-01-15 2003-07-24 Sekisui Chemical Co., Ltd. Ic chip manufacturing method
KR20040004768A (en) * 2002-07-05 2004-01-16 삼성전기주식회사 Dicing method micro electro-mechanical system chip
JP2005228794A (en) * 2004-02-10 2005-08-25 Tokyo Seimitsu Co Ltd Method of manufacturing chip
WO2006014003A1 (en) * 2004-08-03 2006-02-09 The Furukawa Electric Co., Ltd. Semiconductor device manufacturing method and tape for processing wafer
CN101312118B (en) * 2007-05-25 2011-08-31 日东电工株式会社 Protection method of semiconductor wafer
EP2680322A1 (en) * 2012-06-28 2014-01-01 Nitto Denko Corporation Method of manufacturing an led

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003060972A1 (en) * 2002-01-15 2003-07-24 Sekisui Chemical Co., Ltd. Ic chip manufacturing method
US6939741B2 (en) 2002-01-15 2005-09-06 Sekisui Chemical Co., Ltd. IC chip manufacturing method
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