JP2001042344A - Liquid crystal display device and its production - Google Patents
Liquid crystal display device and its productionInfo
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- JP2001042344A JP2001042344A JP11215041A JP21504199A JP2001042344A JP 2001042344 A JP2001042344 A JP 2001042344A JP 11215041 A JP11215041 A JP 11215041A JP 21504199 A JP21504199 A JP 21504199A JP 2001042344 A JP2001042344 A JP 2001042344A
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- film
- insulating film
- liquid crystal
- crystal display
- etching
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- Thin Film Transistor (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【発明の属する技術分野】本発明は、ＴＦＴを用いた液
晶表示装置に関し、特に、画素電極の構造とその製造方
法に関するものである。The present invention relates to a liquid crystal display device using a TFT, and more particularly, to a structure of a pixel electrode and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来の液晶表示装置の製造方法を、画素
電極の形成工程に焦点を絞って、図５の製造工程断面図
を参照しながら説明する。2. Description of the Related Art A conventional method of manufacturing a liquid crystal display device will be described with reference to a manufacturing process sectional view of FIG.
【０００３】図５（ａ）に示した第１の従来例では、Ｉ
ＴＯ層を形成後、パッシベーション層を形成せずに各画
素を分離していた。そのためＩＴＯスパッタ時、ドライ
エッチング時に発生した導電性の異物３０、配向膜ラビ
ング工程で発生した導電性の異物３１が隣接画素分離部
分３２に付着し、隣接する画素電極２６を短絡して２個
対点欠陥を引き起していた。In the first conventional example shown in FIG.
After forming the TO layer, each pixel was separated without forming a passivation layer. Therefore, conductive foreign matter 30 generated during ITO sputtering and dry etching and conductive foreign matter 31 generated during the alignment film rubbing process adhere to the adjacent pixel separation portion 32, and short-circuit the adjacent pixel electrode 26 to form two pairs. Point defects were caused.
【０００４】又、図５（ｂ）に示した第２の従来例で
は、ＩＴＯ層を分離後にパッシベーション層を追加した
場合でも、パッシベーション膜４７形成後に発生した異
物５１に関しては効果があるが、形成前に画素電極４６
間の隣接画素分離部分５２に付着していた異物５０につ
いては効果がない。In the second conventional example shown in FIG. 5B, even when a passivation layer is added after the separation of the ITO layer, the foreign matter 51 generated after the formation of the passivation film 47 is effective, but it is not formed. Before the pixel electrode 46
There is no effect on the foreign matter 50 attached to the adjacent pixel separation portion 52 between them.
【０００５】[0005]
【発明が解決しようとする課題】液晶表示装置の製造の
際に、隣接する２個の画素が短絡することで発生する２
個対点欠陥が発生している。この原因は、ＩＴＯ層から
なる画素電極２６が導電性の異物３０により短絡される
ために発生することが判明している。２個対点欠陥が生
じた場合、パネルは不良品となるので、歩留まりを著し
く悪化させる。このため、導電性の異物による短絡を防
ぐ素子構造が必要となる。When a liquid crystal display device is manufactured, two adjacent pixels are short-circuited.
An individual point defect has occurred. It has been found that this occurs because the pixel electrode 26 made of the ITO layer is short-circuited by the conductive foreign matter 30. When two pairs of point defects occur, the panel becomes a defective product, which significantly reduces the yield. For this reason, an element structure for preventing a short circuit due to conductive foreign matter is required.
【０００６】本発明の目的は、液晶表示装置の製造工程
において、画素電極の短絡を生じさせる異物が発生して
も、短絡に到らない画素電極の構造及びその製造方法を
提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a structure of a pixel electrode which does not cause a short circuit even when a foreign substance causing a short circuit of the pixel electrode occurs in a manufacturing process of a liquid crystal display device, and a method of manufacturing the same. .
【０００７】[0007]
【課題を解決するための手段】本発明の液晶表示装置
は、基板上に形成された複数の素子と、前記素子を含む
前記基板を覆う絶縁膜と、前記素子上の前記絶縁膜の所
定領域に設けられた開口部と、前記絶縁膜上に設けられ
前記開口部を通して前記素子と接続する導電膜と、前記
導電膜を覆い、かつ、前記導電膜に対して庇となる保護
絶縁膜とを含むことを特徴とし、前記導電膜が透明導電
膜であり、前記保護絶縁膜がシリコン酸化膜又はシリコ
ン窒化膜からなり、前記絶縁膜が平坦化処理された平坦
化絶縁膜である、というもので、具体的には、前記素子
が薄膜トランジスタである、というものである。A liquid crystal display device according to the present invention comprises a plurality of elements formed on a substrate, an insulating film covering the substrate including the elements, and a predetermined region of the insulating film on the elements. An opening provided in the insulating film, a conductive film provided on the insulating film and connected to the element through the opening, and a protective insulating film covering the conductive film and serving as an eaves for the conductive film. Wherein the conductive film is a transparent conductive film, the protective insulating film is made of a silicon oxide film or a silicon nitride film, and the insulating film is a planarized insulating film subjected to a planarization process. Specifically, the element is a thin film transistor.
【０００８】本発明の液晶表示装置の製造方法は、複数
の素子が絶縁膜に覆われた基板を用意し、前記素子の上
の前記絶縁膜の所定領域を除去して前記絶縁膜に開口部
を設け、前記開口部を含む前記絶縁膜上に導電膜、保護
絶縁膜を順に堆積させ、前記保護絶縁膜と前記導電膜を
順にエッチング除去して前記保護絶縁膜を前記導電膜に
対して庇とすることを特徴とし、前記保護絶縁膜がシリ
コン酸化膜又はシリコン窒化膜からなり、第１のエッチ
ングの形態として、前記エッチングがドライエッチング
により行われ、前記ドライエッチングが、ヨウ化水素
（ＨＩ）ガスを用いたＲＦプラズマドライエッチングで
あり、前記ヨウ化水素ガスのガス流量が１００〜３００
ｃｃｍ、真空度が１．０〜１．３Ｐａ、ＲＦ電力が５０
０〜１０００Ｗの条件の下に行われる、というものであ
り、その結果、前記ドライエッチングが、前記導電膜の
前記シリコン酸化膜又は前記シリコン窒化膜に対するエ
ッチングレートが１よりも大きいドライエッチングとな
る、というものである。According to a method of manufacturing a liquid crystal display device of the present invention, a substrate in which a plurality of elements are covered with an insulating film is prepared, a predetermined region of the insulating film on the element is removed, and an opening is formed in the insulating film. A conductive film and a protective insulating film are sequentially deposited on the insulating film including the opening, and the protective insulating film and the conductive film are removed by etching in order to cover the protective insulating film with respect to the conductive film. Wherein the protective insulating film is made of a silicon oxide film or a silicon nitride film, and the first etching is performed by dry etching, and the dry etching is performed by hydrogen iodide (HI). RF plasma dry etching using a gas, wherein the gas flow rate of the hydrogen iodide gas is 100 to 300.
ccm, vacuum degree is 1.0 to 1.3 Pa, RF power is 50
The dry etching is performed under a condition of 0 to 1000 W, and as a result, the dry etching is a dry etching in which the etching rate of the conductive film with respect to the silicon oxide film or the silicon nitride film is larger than 1. That is.
【０００９】前記保護絶縁膜がシリコン酸化膜又はシリ
コン窒化膜からなる本発明の製造方法の第２のエッチン
グの形態として、前記エッチングがウェットエッチング
により行われ、前記ウェットエッチングが、前記シリコ
ン酸化膜又は前記シリコン窒化膜をマスクとして塩酸
（ＨＣｌ）により行われる、というものである。As a second etching mode of the manufacturing method according to the present invention, wherein the protective insulating film is made of a silicon oxide film or a silicon nitride film, the etching is performed by wet etching, and the wet etching is performed by the silicon oxide film or the silicon oxide film. It is performed with hydrochloric acid (HCl) using the silicon nitride film as a mask.
【００１０】最後に、上記製造方法における導電膜と保
護絶縁膜とが、真空中で連続して堆積される、というも
のである。[0010] Finally, the conductive film and the protective insulating film in the above manufacturing method are continuously deposited in a vacuum.
【００１１】[0011]
【発明の実施の形態】本発明の基本的な構成は、ＴＦＴ
回路を用いた液晶表示装置において、ＩＴＯ画素電極の
上にパッシベーション層が形成されており、ドライエッ
チにより隣接する画素を分離する際、ＩＴＯ画素電極層
をパッシベーション層に対して横方向に意図的にオーバ
ーエッチングさせることで、ＩＴＯ画素電極の端がパッ
シベーション層の端よりも内側後退し、パッシベーショ
ン層がＩＴＯ画素電極に対して庇状の断面構造を持つこ
とを特徴とする。DESCRIPTION OF THE PREFERRED EMBODIMENTS The basic structure of the present invention is a TFT
In a liquid crystal display device using a circuit, a passivation layer is formed on an ITO pixel electrode, and when an adjacent pixel is separated by dry etching, the ITO pixel electrode layer is intentionally laterally formed with respect to the passivation layer. By over-etching, the edge of the ITO pixel electrode recedes inward from the edge of the passivation layer, and the passivation layer has an eave-like cross-sectional structure with respect to the ITO pixel electrode.
【００１２】図１は、本発明の基本的な構造を示す画素
電極及びＴＦＴ回路近傍の断面図である。FIG. 1 is a sectional view showing the basic structure of the present invention in the vicinity of a pixel electrode and a TFT circuit.
【００１３】ガラス基板１上にＴＦＴ回路２が形成され
ており、その上を有機材料からなる平坦化絶縁膜３が形
成されている。平坦化絶縁膜３にはＴＦＴ回路２と電気
的接続をとるための開口部４が設けられ、そこを通して
平坦化絶縁膜３上にＩＴＯ層５からなる画素電極６が形
成されている。この画素電極６の上にはシリコン酸化膜
（ＳｉＯ２）８又はシリコン窒化膜（ＳｉＮｘ）９から
なるパッシベーション膜７が形成されており、パッシベ
ーション膜７と画素電極６とは、その断面構造におい
て、画素電極６が上部のパッシベーション膜７よりも内
側に後退した形状となっている。A TFT circuit 2 is formed on a glass substrate 1, on which a planarizing insulating film 3 made of an organic material is formed. An opening 4 for making electrical connection with the TFT circuit 2 is provided in the planarizing insulating film 3, and a pixel electrode 6 made of an ITO layer 5 is formed on the planarizing insulating film 3 through the opening 4. A passivation film 7 made of a silicon oxide film (SiO 2) 8 or a silicon nitride film (SiNx) 9 is formed on the pixel electrode 6. The passivation film 7 and the pixel electrode 6 have a cross-sectional structure of a pixel. The electrode 6 has a shape recessed inside the upper passivation film 7.
【００１４】次に、本発明の基本的な構造を実現させる
本発明の製造方法の第１の実施形態を、図２を用いて説
明する。Next, a first embodiment of the manufacturing method of the present invention for realizing the basic structure of the present invention will be described with reference to FIG.
【００１５】まず、ガラス基板１上にＴＦＴ回路２を形
成し、ＴＦＴ回路２を覆う絶縁膜を堆積させ、更に平坦
化処理を施して平坦化絶縁膜３を形成する。続いて、Ｔ
ＦＴ回路２の上の平坦化絶縁膜３の所定領域をエッチン
グ除去して開口部４を設け、開口部４を含む平坦化絶縁
膜３の全面に画素電極となるＩＴＯ層５をスパッタ法に
より堆積する（図２（ａ））。First, a TFT circuit 2 is formed on a glass substrate 1, an insulating film covering the TFT circuit 2 is deposited, and a flattening process is performed to form a flattening insulating film 3. Then, T
A predetermined region of the flattening insulating film 3 on the FT circuit 2 is removed by etching to form an opening 4, and an ITO layer 5 serving as a pixel electrode is deposited on the entire surface of the flattening insulating film 3 including the opening 4 by a sputtering method. (FIG. 2A).
【００１６】次に、ＩＴＯ層５の堆積に続きパッシベー
ション膜となるシリコン酸化膜（ＳｉＯ２）８をスパッ
タ法またはＣＶＤ法により堆積する（図２（ｂ））。Next, following the deposition of the ITO layer 5, a silicon oxide film (SiO2) 8 serving as a passivation film is deposited by a sputtering method or a CVD method (FIG. 2B).
【００１７】最後に、フォトレジスト膜１０を用いて、
ＲＦプラズマドライエッチングにより隣接画素を分離す
る。この時、エッチングガスにヨウ化水素（ＨＩ）を用
い、真空度１．３Ｐａ、ガス流量３００ｃｃｍ、投入Ｒ
Ｆ電力８００Ｗのエッチング条件の下にエッチングを行
うと、ＩＴＯ層５のエッチングレートがシリコン酸化膜
８のエッチングレートに対して５以上となる条件が得ら
れる。この条件により、シリコン酸化膜８とＩＴＯ層５
を１度のドライエッチングにより分離する。エッチング
の際には意図的にエッチング過剰となるように処理時間
を調整し、画素電極６がパッシベーション膜７よりも内
側に後退した断面構造を形成する（図２（ｃ））。Finally, using the photoresist film 10,
Adjacent pixels are separated by RF plasma dry etching. At this time, hydrogen iodide (HI) was used as an etching gas, the degree of vacuum was 1.3 Pa, the gas flow rate was 300 ccm, and the input R was
When the etching is performed under the etching condition of the F power of 800 W, the condition that the etching rate of the ITO layer 5 is 5 or more with respect to the etching rate of the silicon oxide film 8 is obtained. Under these conditions, the silicon oxide film 8 and the ITO layer 5
Are separated by one dry etching. At the time of etching, the processing time is adjusted so that the etching is intentionally excessive, thereby forming a cross-sectional structure in which the pixel electrode 6 is recessed inside the passivation film 7 (FIG. 2C).
【００１８】以下に、図３を用いて本発明の製造方法の
第１の実施形態の効果を説明する。The effect of the first embodiment of the manufacturing method of the present invention will be described below with reference to FIG.
【００１９】今回の発明の第１の実施形態により得られ
る画素電極の構造を用いれば、図３（ａ）に示すよう
に、ＩＴＯスパッタ時に発生した異物１０は、その後の
シリコン酸化膜８の堆積の段階でシリコン酸化膜８の下
に固定される。仮に隣接画素分離部分１２に付着してい
た場合でも異物１０の組成はＩＴＯであり、ドライエッ
チング処理時に選択比が十分に高い条件を用いるため、
切断されてしまい短絡の原因にはならない。これによ
り、パッシベーション膜７の下の互いに隣接する画素電
極６の絶縁が保証できる。If the structure of the pixel electrode obtained by the first embodiment of the present invention is used, as shown in FIG. 3A, the foreign matter 10 generated during the ITO sputtering Is fixed under the silicon oxide film 8 at this stage. Even if the foreign matter 10 adheres to the adjacent pixel separation portion 12, the composition of the foreign matter 10 is ITO, and a condition that the selectivity is sufficiently high during the dry etching process is used.
They are cut and do not cause a short circuit. Thereby, insulation of the adjacent pixel electrodes 6 under the passivation film 7 can be guaranteed.
【００２０】画素電極６分離後に異物１１が発生し、隣
接画素分離部分１２に付着しても、断面形状が庇状にな
っているため、隣接する画素電極６間の短絡は発生しな
い。このようにして、平坦化絶縁膜３の上での画素電極
６間の絶縁が保証される。Even if foreign matter 11 is generated after the separation of the pixel electrode 6 and adheres to the adjacent pixel separation portion 12, the short-circuit between the adjacent pixel electrodes 6 does not occur because the cross-sectional shape is an eaves shape. In this way, insulation between the pixel electrodes 6 on the planarization insulating film 3 is guaranteed.
【００２１】以上の効果により、導電性の異物による隣
接画素電極間の短絡を防止することができ、２個対点欠
陥の発生を防止できる。According to the above effects, a short circuit between adjacent pixel electrodes due to a conductive foreign substance can be prevented, and the occurrence of a two-pair defect can be prevented.
【００２２】又、隣接画素の絶縁が保証されるので、２
個対欠陥が発生しない。２個対欠陥が除去されること
で、液晶表示装置の歩留まりは必然的に向上する。Also, since insulation of adjacent pixels is guaranteed,
No individual defects occur. The removal of the two-pair defect necessarily increases the yield of the liquid crystal display device.
【００２３】更に、絶縁膜とＩＴＯは同じフォトレジス
トパターンで同時にエッチングするため、増加する工程
は絶縁膜堆積工程のみである。Further, since the insulating film and the ITO are simultaneously etched with the same photoresist pattern, the only step to increase is the insulating film depositing step.
【００２４】本発明の製造方法の第１の実施形態ではパ
ッシベーション膜７としてシリコン酸化膜を用いた例を
示したが、シリコン酸化膜に代えてシリコン窒化膜（Ｓ
ｉＮｘ）ても良い。In the first embodiment of the manufacturing method of the present invention, an example in which a silicon oxide film is used as the passivation film 7 has been described, but a silicon nitride film (S
iNx).
【００２５】本発明の製造方法の第２の実施形態とし
て、パッシベーション層としてシリコン窒化膜（ＳｉＮ
ｘ）を用いた場合の例を示す。図２（ａ）、（ｂ）まで
の製造工程は第１の実施形態と全く同じであるので説明
は省略し、図２（ｃ）のシリコン酸化膜８をシリコン窒
化膜９と読み替えて説明する。As a second embodiment of the manufacturing method of the present invention, a silicon nitride film (SiN
An example in the case of using x) is shown. 2 (a) and 2 (b) are exactly the same as those in the first embodiment, so that the description thereof will be omitted, and the description will be made with the silicon oxide film 8 in FIG. .
【００２６】パッシベーション層をシリコン窒化膜（Ｓ
ｉＮｘ）とした場合、エッチングガスにはヨウ化水素
（ＨＩ）を用い、ガス流量が１００〜３００ｃｃｍ、真
空度が１．０〜１．３Ｐａ、ＲＦ電力が５００〜１００
０Ｗの下のエッチングを行うと、ＩＴＯ層５のエッチン
グレートがシリコン窒化膜９のエッチングレートに対し
て５以上となる条件が得られる。シリコン酸化膜を用い
た場合と同様の効果により庇状の断面形状が形成可能で
ある。The passivation layer is formed of a silicon nitride film (S
iNx), hydrogen iodide (HI) is used as an etching gas, the gas flow rate is 100 to 300 ccm, the degree of vacuum is 1.0 to 1.3 Pa, and the RF power is 500 to 100.
When etching is performed under 0 W, a condition is obtained in which the etching rate of the ITO layer 5 is 5 or more with respect to the etching rate of the silicon nitride film 9. An eaves-like cross-sectional shape can be formed by the same effect as when a silicon oxide film is used.
【００２７】以上、本発明の第１、２の実施形態におい
ては、シリコン酸化膜とシリコン窒化膜を用いた例を示
したが、シリコン酸化膜又はシリコン窒化膜に代えて、
画素電極材料（第１、２の実施形態においてはＩＴＯ
層）のエッチングレートが相対的に大きくなる材料を適
宜選択して用いても良いことは言うまでもない。As described above, in the first and second embodiments of the present invention, an example in which a silicon oxide film and a silicon nitride film are used has been described.
Pixel electrode material (in the first and second embodiments, ITO
It goes without saying that a material having a relatively high etching rate of the layer may be appropriately selected and used.
【００２８】次に、本発明の製造方法の第３の実施形態
として、隣接画素電極の分離にドライエッチングとウェ
ットエッチングとの組み合わせを用いる製造方法を、Ｉ
ＴＯ層、パッシベーション層堆積後の製造工程に焦点を
絞って、図４を用いて説明する。Next, as a third embodiment of the manufacturing method of the present invention, a manufacturing method using a combination of dry etching and wet etching for separating adjacent pixel electrodes will be described.
A description will be given with reference to FIG.
【００２９】まず、ＣＦ４ガスを用いたプラズマドライ
エッチングにより、シリコン酸化膜１８をエッチングし
てパッシベーション膜１７を形成する（図４（ａ））。
続いて、ＣＦ４プラズマドライエッチングではＩＴＯ層
１５はエッチングされないため、オーバーエッチングに
よるＩＴＯ層１５のダメージを考慮する必要はない。よ
ってシリコン酸化膜がエッチング可能であれば条件は問
わない。１例として、ＣＦ４ガス流量４０ｃｃｍ、酸素
ガス流量１０ｃｃｍ、真空度１〜２０Ｐａ、投入ＲＦ電
力３００〜１０００Ｗのエッチング条件でシリコン酸化
膜のエッチングが可能である。First, the silicon oxide film 18 is etched by plasma dry etching using CF4 gas to form a passivation film 17 (FIG. 4A).
Subsequently, since the ITO layer 15 is not etched by CF4 plasma dry etching, it is not necessary to consider damage to the ITO layer 15 due to over-etching. Therefore, the condition does not matter as long as the silicon oxide film can be etched. As an example, the silicon oxide film can be etched under the conditions of a CF4 gas flow rate of 40 ccm, an oxygen gas flow rate of 10 ccm, a degree of vacuum of 1 to 20 Pa, and an applied RF power of 300 to 1000 W.
【００３０】次に、塩酸（ＨＣｌ）によりＩＴＯ層１５
をエッチング除去して画素電極１６を形成する（図４
（ｂ））。シリコン酸化膜からなるパッシベーション膜
１７はＨＣｌによってエッチングされないので、ＩＴＯ
層１５がエッチング可能であれば、塩酸の濃度は問わな
い。また、パッシベーション膜１７がエッチングマスク
の役割を果たすため、通常のエッチングの際に必要とな
るフォトレジストによるマスクパターン形成は不要であ
る。ドライエッチングのみを用いる場合に比べて、増加
する工程はＨＣｌによるウエットエッチング工程のみ
で、大幅な工程数の増加がなく、実施形態１、２と同様
の効果が得られる。Next, the ITO layer 15 is treated with hydrochloric acid (HCl).
Is removed by etching to form a pixel electrode 16 (FIG. 4).
(B)). Since the passivation film 17 made of a silicon oxide film is not etched by HCl, ITO
The concentration of hydrochloric acid does not matter as long as the layer 15 can be etched. In addition, since the passivation film 17 plays a role of an etching mask, it is not necessary to form a mask pattern by using a photoresist which is necessary for normal etching. Compared to the case where only dry etching is used, the number of steps to be increased is only a wet etching step using HCl, and the number of steps is not greatly increased, and the same effects as those of the first and second embodiments can be obtained.
【００３１】最後に、上記本発明の第１〜３の実施形態
において、ＩＴＯ層とそれに続く絶縁膜を真空中で連続
堆積する手法を採用すれば、ＩＴＯ層と絶縁膜界面が大
気に暴露されることがなくなり、パッシベーション層形
成前の洗浄工程が不要になって工程数を削減できるとと
もに、大気に暴露することで付着する可能性のある異物
を削減できる、という効果も得られる。Finally, in the above-described first to third embodiments of the present invention, if the method of continuously depositing the ITO layer and the subsequent insulating film in a vacuum is adopted, the interface between the ITO layer and the insulating film is exposed to the atmosphere. This eliminates the need for a cleaning step before the passivation layer is formed, thereby reducing the number of steps and reducing the number of foreign substances that may be attached by exposure to the atmosphere.
【００３２】[0032]
【発明の効果】本発明の液晶表示装置は、ＩＴＯ層をそ
の上のシリコン酸化膜と共に一度のドライエッチングで
分離し、更に、ＩＴＯ層をパッシベーション膜に対して
オーバーエッチングするので、パッシベーション膜の下
の画素電極は確実に隣接する画素電極から分離され、分
離後に異物が発生した場合でもパッシベーション膜の庇
に阻まれて画素電極間の短絡が発生しない。以上によ
り、隣接する画素電極間の絶縁性が保証される。According to the liquid crystal display device of the present invention, the ITO layer is separated by a single dry etching together with the silicon oxide film thereon, and the ITO layer is over-etched with respect to the passivation film. The pixel electrode is surely separated from the adjacent pixel electrode, and even if a foreign matter is generated after the separation, the pixel electrode is prevented by the eaves of the passivation film and no short circuit occurs between the pixel electrodes. As described above, insulation between adjacent pixel electrodes is guaranteed.
【００３３】又、ＩＴＯ層とパッシベーション層を連続
で成膜する方法を用いた場合、画素電極を形成後にパッ
シベーション層を堆積させた場合に生じる画素電極間の
導電性異物が発生しなくなるため、画素電極間の短絡を
更に減らすことができる。When a method of forming an ITO layer and a passivation layer successively is used, conductive foreign matter between the pixel electrodes, which is generated when the passivation layer is deposited after the formation of the pixel electrode, is not generated. Short circuits between the electrodes can be further reduced.
【００３４】これらの効果により、隣接画素の絶縁が保
証されるので、２個対欠陥が発生せず、２個対欠陥が除
去されることで、液晶表示装置の歩留まりは必然的に向
上する、という効果が得られる。By these effects, the insulation of the adjacent pixels is ensured, so that the two-pair defect does not occur and the two-pair defect is removed, whereby the yield of the liquid crystal display device is inevitably improved. The effect is obtained.
【図１】本発明の液晶表示装置における画素電極の構造
を示す断面図である。FIG. 1 is a cross-sectional view illustrating a structure of a pixel electrode in a liquid crystal display device of the present invention.
【図２】本発明の画素電極の構造を得るための本発明の
製造方法の第１の実施形態を、製造工程順に示す断面図
である。FIG. 2 is a sectional view showing a first embodiment of a manufacturing method of the present invention for obtaining a structure of a pixel electrode of the present invention in the order of manufacturing steps.
【図３】本発明の製造方法の第１の実施形態の効果を説
明するための断面図である。FIG. 3 is a cross-sectional view for explaining an effect of the first embodiment of the manufacturing method of the present invention.
【図４】本発明の画素電極の構造を得るための本発明の
製造方法の第２の実施形態を、製造工程順に示す断面図
である。FIG. 4 is a sectional view showing a second embodiment of the manufacturing method of the present invention for obtaining the structure of the pixel electrode of the present invention in the order of manufacturing steps.
【図５】従来の液晶表示装置の画素電極の製造方法にお
ける問題点を示す断面図である。FIG. 5 is a cross-sectional view showing a problem in a conventional method for manufacturing a pixel electrode of a liquid crystal display device.
１ ガラス基板 ２ ＴＦＴ回路 ３ 平坦化絶縁膜 ４ 開口部 ５、１５ ＩＴＯ層 ６、１６、２６、４６ 画素電極 ７、１７、４７ パッシベーション膜 ８ シリコン酸化膜 ９ シリコン窒化膜 １０、１１、３０、３１、５０、５１ 異物 １２、３２、５２ 隣接画素分離部分 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 TFT circuit 3 Flattening insulating film 4 Opening 5,15 ITO layer 6,16,26,46 Pixel electrode 7,17,47 Passivation film 8 Silicon oxide film 9 Silicon nitride film 10,11,30,31 , 50, 51 Foreign matter 12, 32, 52 Adjacent pixel separation part
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 29/786 Ｈ０１Ｌ 29/78 ６１９Ａ ５Ｇ４３５ Ｆターム(参考） 2H090 HA01 HB02X HC01 HC12 2H092 HA28 JA24 JB57 JB58 KB24 MA05 MA07 MA15 MA18 MA19 NA16 NA29 5C094 AA21 AA42 BA03 BA43 CA19 DA15 EA05 FA04 FB02 FB15 GB01 5F058 BA02 BA09 BB04 BB07 BC02 BC08 BF37 BF39 BH11 BJ03 5F110 AA30 DD02 HL07 NN02 NN23 NN24 NN34 NN35 QQ04 QQ05 QQ19 5G435 AA16 AA17 BB12 GG31 HH14 HH20 KK05 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI theme coat ゛ (Reference) H01L 29/786 H01L 29/78 619A 5G435 F-term (Reference) 2H090 HA01 HB02X HC01 HC12 2H092 HA28 JA24 JB57 JB58 KB24 MA05 MA07 MA15 MA18 MA19 NA16 NA29 5C094 AA21 AA42 BA03 BA43 CA19 DA15 EA05 FA04 FB02 FB15 GB01 5F058 BA02 BA09 BB04 BB07 BC02 BC08 BF37 BF39 BH11 BJ03 5F110 AA30 DD02 HL07 NN02 NN23 NN24 NN24 NN24 NN24 NN34
Claims (12)
素子を含む前記基板を覆う絶縁膜と、前記素子上の前記
絶縁膜の所定領域に設けられた開口部と、前記絶縁膜上
に設けられ前記開口部を通して前記素子と接続する導電
膜と、前記導電膜を覆い、かつ、前記導電膜に対して庇
となる保護絶縁膜とを含むことを特徴とする液晶表示装
置。A plurality of elements formed on a substrate; an insulating film covering the substrate including the elements; an opening provided in a predetermined region of the insulating film on the elements; A liquid crystal display device comprising: a conductive film provided on the substrate and connected to the element through the opening; and a protective insulating film that covers the conductive film and serves as an eaves for the conductive film.
記載の液晶表示装置。2. The method according to claim 1, wherein the conductive film is a transparent conductive film.
The liquid crystal display device as described in the above.
リコン窒化膜からなる請求項１又は２記載の液晶表示装
置。3. The liquid crystal display device according to claim 1, wherein said protective insulating film is made of a silicon oxide film or a silicon nitride film.
縁膜である請求項１、２又は３記載の液晶表示装置。4. The liquid crystal display device according to claim 1, wherein the insulating film is a planarized insulating film subjected to a planarization process.
項１、２、３又は４記載の液晶表示装置。5. The liquid crystal display device according to claim 1, wherein said element is a thin film transistor.
意し、前記素子の上の前記絶縁膜の所定領域を除去して
前記絶縁膜に開口部を設け、前記開口部を含む前記絶縁
膜上に導電膜、保護絶縁膜を順に堆積させ、前記保護絶
縁膜と前記導電膜を順にエッチング除去して前記保護絶
縁膜を前記導電膜に対して庇とすることを特徴とする液
晶表示装置の製造方法。6. A substrate in which a plurality of elements are covered with an insulating film is provided, a predetermined region of the insulating film over the elements is removed, an opening is provided in the insulating film, and the substrate includes the opening. A liquid crystal display, wherein a conductive film and a protective insulating film are sequentially deposited on an insulating film, and the protective insulating film and the conductive film are sequentially removed by etching to make the protective insulating film an eaves with respect to the conductive film. Device manufacturing method.
リコン窒化膜からなり、前記エッチングがドライエッチ
ングにより行われる請求項６記載の液晶表示装置の製造
方法。7. The method according to claim 6, wherein the protective insulating film is made of a silicon oxide film or a silicon nitride film, and the etching is performed by dry etching.
（ＨＩ）ガスを用いたＲＦプラズマドライエッチングで
あり、前記ヨウ化水素ガスのガス流量が１００〜３００
ｃｃｍ、真空度が１．０〜１．３Ｐａ、ＲＦ電力が５０
０〜１０００Ｗの条件の下に行われる請求項７記載の液
晶表示装置の製造方法。8. The dry etching is RF plasma dry etching using hydrogen iodide (HI) gas, and the gas flow rate of the hydrogen iodide gas is 100 to 300.
ccm, vacuum degree is 1.0 to 1.3 Pa, RF power is 50
The method according to claim 7, wherein the method is performed under a condition of 0 to 1000 W.
前記シリコン酸化膜又は前記シリコン窒化膜に対するエ
ッチングレートが１よりも大きいドライエッチングであ
る請求項７又は８記載の液晶表示装置の製造方法。9. The method for manufacturing a liquid crystal display device according to claim 7, wherein the dry etching is a dry etching in which an etching rate of the conductive film with respect to the silicon oxide film or the silicon nitride film is larger than 1.
シリコン窒化膜からなり、前記エッチングがウェットエ
ッチングにより行われる請求項６記載の液晶表示装置の
製造方法。10. The method according to claim 6, wherein the protection insulating film is made of a silicon oxide film or a silicon nitride film, and the etching is performed by wet etching.
コン酸化膜又は前記シリコン窒化膜をマスクとして塩酸
（ＨＣｌ）により行われる請求項１０記載の液晶表示装
置の製造方法。11. The method according to claim 10, wherein the wet etching is performed with hydrochloric acid (HCl) using the silicon oxide film or the silicon nitride film as a mask.
空中で連続して堆積される請求項６、７、８、９、１０
又は１１記載の液晶表示装置の製造方法。12. The method according to claim 6, wherein the conductive film and the protective insulating film are continuously deposited in a vacuum.
Or a method for manufacturing a liquid crystal display device according to item 11.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100444429C (en) * | 2004-12-14 | 2008-12-17 | 中华映管股份有限公司 | Active organic electroluminescent assembly array and manufacturing method thereof |
| WO2014157234A1 (en) | 2013-03-29 | 2014-10-02 | 昭和電工株式会社 | Method for producing transparent conductive substrate, and transparent conductive substrate |
-
1999
- 1999-07-29 JP JP21504199A patent/JP3393470B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100444429C (en) * | 2004-12-14 | 2008-12-17 | 中华映管股份有限公司 | Active organic electroluminescent assembly array and manufacturing method thereof |
| WO2014157234A1 (en) | 2013-03-29 | 2014-10-02 | 昭和電工株式会社 | Method for producing transparent conductive substrate, and transparent conductive substrate |
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