JP2001028379A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JP2001028379A JP2001028379A JP11201282A JP20128299A JP2001028379A JP 2001028379 A JP2001028379 A JP 2001028379A JP 11201282 A JP11201282 A JP 11201282A JP 20128299 A JP20128299 A JP 20128299A JP 2001028379 A JP2001028379 A JP 2001028379A
- Authority
- JP
- Japan
- Prior art keywords
- conductive paste
- mold resin
- cured
- semiconductor device
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の外形形
状、特に、電極にバンプを有する半導体装置とその製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an outer shape of a semiconductor device, and more particularly to a semiconductor device having bumps on electrodes and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来、シリコン・ウエハ上にフォトリソ
技術や拡散技術などを用いて作成された半導体装置をプ
リント基板に直接または間接的に実装できる形にする
為、実装時の接続用のリードフレームにチップをダイボ
ンドし、次にリードフレームとの接続をするため半導体
チップ上の外部接続電極をリードフレームをワイアーボ
ンディングで接続し、最後に樹脂でリードフレームの一
部とワイアーボンディングを含む半導体チップをモール
ドしていた。しかし、実装方法の変化とリードフレーム
へのボンディングの工程を合理化するためウエハ状態の
ままリードフレームの役割を果たす外部接続部材、例え
ばスタッドバンプやボールバンプを接合する方法が注目
されてきている。2. Description of the Related Art Conventionally, in order to form a semiconductor device formed on a silicon wafer using a photolithography technique or a diffusion technique on a printed circuit board directly or indirectly, a lead frame for connection at the time of mounting is used. The chip is die-bonded, and then the external connection electrodes on the semiconductor chip are connected to the lead frame by wire bonding in order to connect with the lead frame. Finally, a part of the lead frame and the semiconductor chip including wire bonding are bonded with resin. It had been molded. However, attention has been paid to a method of bonding an external connection member, such as a stud bump or a ball bump, which plays a role of a lead frame in a wafer state in order to change a mounting method and rationalize a process of bonding to a lead frame.
【０００３】ここで半導体チップ表面の電極に外部接続
用部材、例えばボールを直接接合すれば工程的にも簡素
であるが、外部からの応力がチップの電極に直接加わる
ため信頼性の確保が困難である。そこで一般的には応力
を緩和するバネ状の物を介して接合したり、弾性体を挟
むなどの方法が用いられている。そこで更に簡素な構造
を取る方法として半導体チップ上の電極から一度立ち上
げチップ表面からの距離を取ることでその応力を緩和さ
せる方法がある。この場合、電極表面から１００μｍ程
度の高さの銅の円柱状の柱（タワーバンプ）をメッキで
形成したりしている。[0003] Here, if an external connection member such as a ball is directly bonded to the electrode on the surface of the semiconductor chip, the process is simple, but external stress is directly applied to the electrode of the chip, so that it is difficult to ensure reliability. It is. Therefore, generally, a method of joining via a spring-like material to relieve stress or sandwiching an elastic body is used. Therefore, as a method of taking a simpler structure, there is a method of once raising the electrode from the semiconductor chip and increasing the distance from the chip surface to alleviate the stress. In this case, a copper column (tower bump) having a height of about 100 μm from the electrode surface is formed by plating.
【０００４】[0004]
【発明が解決しようとする課題】しかし、上記方法では
メッキで１００μｍの厚みを形成するために速くても３
００分以上の時間を必要とし、その間、高濃度の金属イ
オンが存在するメッキ液中にさらすことになる。これは
半導体素子の信頼性のダウンと生産コストのアップに繋
がる。However, according to the above-mentioned method, it is necessary to use a plating method to form a thickness of 100 μm at a minimum.
It requires more than 00 minutes, during which time it will be exposed to a plating solution in which high concentrations of metal ions are present. This leads to a decrease in the reliability of the semiconductor element and an increase in the production cost.
【０００５】[0005]
【課題を解決するための手段】本発明では上記問題点を
解決し、簡便かつ高信頼性で背の高い円柱状のタワーバ
ンプの構造と製造方法を提供する物である。つまり、請
求項１にかかる半導体装置は、半導体チップの外部接続
用電極に接続した導電性ペースト硬化物がモールド樹脂
に囲われ、該モールド樹脂表面に前記導電性ペーストが
露出し、前記導電性ペーストが露出した領域に外部接続
用の半田バンプが形成されていることを特徴とする。SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide a simple and high-reliable, tall, columnar tower bump structure and manufacturing method. In other words, the semiconductor device according to claim 1, wherein the cured conductive paste connected to the external connection electrode of the semiconductor chip is surrounded by the mold resin, and the conductive paste is exposed on the surface of the mold resin. Is characterized in that a solder bump for external connection is formed in a region where is exposed.
【０００６】また、請求項２にかかる半導体装置は、請
求項１記載の半導体装置において、前記半田バンプと前
記導電性ペーストの間に拡散防止金属層を備えることを
特徴とする。また、請求項３にかかる半導体装置は、請
求項１または２記載の半導体装置において、前記導電性
ペースト硬化物中の樹脂と前記モールド樹脂の混合物が
前記導電性ペーストと前記モールド樹脂界面に存在する
ことを特徴とする。また、請求項４にかかる半導体装置
は、請求項１乃至３記載の半導体装置において、前記導
電性ペースト硬化物の断面形状が前記モールド樹脂表面
側よりも半導体チップ側の方が大きいことを特徴とす
る。According to a second aspect of the present invention, in the semiconductor device according to the first aspect, a diffusion preventing metal layer is provided between the solder bump and the conductive paste. According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, a mixture of the resin in the cured conductive paste and the mold resin exists at the interface between the conductive paste and the mold resin. It is characterized by the following. A semiconductor device according to a fourth aspect is the semiconductor device according to the first to third aspects, wherein the cross-sectional shape of the cured conductive paste is larger on the semiconductor chip side than on the mold resin surface side. I do.
【０００７】また、請求項５にかかる半導体装置の製造
方法は、半導体チップ上にレジストを形成し、前記半導
体チップの外部接続用電極部分にレジスト開口部を形成
し、該開口部に導電性ペーストを埋め込み、該導電性ペ
ーストを硬化して導電性ペースト硬化物を形成し、前記
レジストを除去し、前記導電性ペースト硬化物が少なく
とも埋まる厚みまでモールド樹脂を成形し、該モールド
樹脂の表面を前記導電性ペースト硬化物が露出するまで
研磨することを特徴とする。また、請求項６にかかる半
導体装置の製造方法は、請求項５記載の半導体装置の製
造方法において、前記導電性ペースト硬化物が露出する
まで研磨した後、前記導電性ペースト硬化物が露出した
領域に拡散防止金属層を形成することを特徴とする。According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising forming a resist on a semiconductor chip, forming a resist opening in an external connection electrode portion of the semiconductor chip, and forming a conductive paste in the opening. Embedded, the conductive paste is cured to form a conductive paste cured product, the resist is removed, a mold resin is molded to a thickness at which the conductive paste cured product is at least buried, and the surface of the mold resin is The polishing is performed until the cured conductive paste is exposed. According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fifth aspect, after polishing until the hardened conductive paste is exposed, a region where the hardened conductive paste is exposed is provided. A diffusion preventing metal layer is formed thereon.
【０００８】[0008]
【発明の実施の形態】本発明で記載されている拡散防止
金属層とは、半田バンプと導電性ペースト硬化物との間
に存在し、拡散等の相互作用の影響を防止するためであ
る。金属材料としては、Ｎｉ、Ｔｉ、Ｗ等があり、製法
は蒸着法、スパッタ法、電解メッキ法、無電解メッキ法
等がある。また、導電性ペースト硬化物の樹脂とモール
ド樹脂との混合物は導電ペーストに含まれるエポキシと
モールド樹脂のエポキシ、フィラー等が混合されたもの
である。以下、本発明を実施例および比較例を挙げて説
明する。勿論、本発明は、以下の実施例のみに限定され
るものではなく、種々の変形が可能である。BEST MODE FOR CARRYING OUT THE INVENTION The diffusion preventing metal layer described in the present invention is present between a solder bump and a cured conductive paste to prevent the influence of interaction such as diffusion. Examples of the metal material include Ni, Ti, W, and the like, and the manufacturing method includes a vapor deposition method, a sputtering method, an electrolytic plating method, and an electroless plating method. The mixture of the resin of the cured conductive paste and the mold resin is a mixture of the epoxy contained in the conductive paste, the epoxy of the mold resin, a filler, and the like. Hereinafter, the present invention will be described with reference to Examples and Comparative Examples. Of course, the present invention is not limited to only the following embodiments, and various modifications are possible.
【０００９】[0009]
【実施例１】半導体チップの基板として、シリコンウェ
ハー基板が用いられ、半導体チップの外部接続用電極
（直径２００μｍのサイズ）上を開口部として、タムラ
科研製写真現像型ソルダーレジストインクＢＧＡ−５を
用いてメーカー標準工程でコーティングしオーバーコー
ト２０μｍを形成した（図２―Ｂ）。次にドライフィル
ムレジスト（旭化成工業（株）製サンフォート＃５０３
６）を２枚ラミネートし、前記２００μｍ直径開口部上
に同心円になるよう直径２５０μｍの開口を持つフォト
マスクを通して露光量１００ｍＪで露光、その後現像し
てレジストパターンを形成した（図２―Ｃ）。Example 1 A silicon wafer substrate was used as a substrate of a semiconductor chip, and a photo-developed solder resist ink BGA-5 manufactured by Tamura Kaken was used as an opening on an external connection electrode (size of 200 μm in diameter) of the semiconductor chip. It was used for coating by a manufacturer's standard process to form an overcoat of 20 μm (FIG. 2-B). Next, dry film resist (Sunfort # 503 manufactured by Asahi Kasei Corporation)
6) were laminated, exposed at a light exposure of 100 mJ through a photomask having an opening of 250 μm in diameter so as to be concentric with the opening of 200 μm in diameter, and then developed to form a resist pattern (FIG. 2-C).
【００１０】次に上記開口に、２００μｍ直径の穴を持
つステンレスマスクを当てて、旭化成工業（株）製導電
性ペースト（ＧＰ９１３）を印刷機を使って埋め込んだ
（図２―Ｄ）。次に、１８０度で１時間加熱し導電性ペ
ーストを硬化後１％苛性ソーダ液を吹き付けることでド
ライフィルムを除去した（図２−Ｅ）。その後、表面に
封止用エポキシ樹脂（米国アルファメタルズ社ＨＥＬ１
８）をペースト突起部が埋まる厚みまで封入し１６０度
３０分硬化させた（図２―Ｆ）。Next, a stainless steel mask having a hole having a diameter of 200 μm was applied to the opening, and a conductive paste (GP913) manufactured by Asahi Kasei Kogyo Co., Ltd. was embedded using a printing machine (FIG. 2-D). Next, after heating at 180 degrees for 1 hour to cure the conductive paste, a 1% caustic soda solution was sprayed to remove the dry film (FIG. 2-E). After that, an epoxy resin for encapsulation (HEL1 from Alpha Metals, USA)
8) was sealed until the paste protrusions were buried, and cured at 160 ° C. for 30 minutes (FIG. 2-F).
【００１１】その後、表面をベルト研磨機を用い＃６０
０ベルトで研磨し導電性ペーストの硬化物上の封止用エ
ポキシ樹脂が完全に除去されるまで研磨した。最後に、
＃１０００、＃２０００ベルトで研磨した（図２―
Ｇ）。次に、導電性ペースト硬化物のモールド樹脂表面
に露出した面を酸洗浄、パラジュウムによる活性化処理
（上村工業（株）ＫＡＴ−４５０）後、無電解ニッケル
メッキ（上村工業（株）ニムデンＮＰＲ−４）でニッケ
ル層５μｍを形成し、更にその上に上村工業（株）オー
リカルＴＫＫ無電解金メッキ液を使い金０．５μｍを形
成した。Thereafter, the surface is # 60 using a belt grinder.
This was polished with a zero belt and polished until the sealing epoxy resin on the cured product of the conductive paste was completely removed. Finally,
Polished with # 1000 and # 2000 belts (Fig. 2-
G). Next, the surface of the cured conductive paste exposed on the mold resin surface is subjected to acid washing, activation treatment with palladium (KAT-450, Uemura Kogyo Co., Ltd.), and then electroless nickel plating (Nimden NPR-, Uemura Kogyo Co., Ltd.). In step 4), a nickel layer having a thickness of 5 μm was formed, and a gold layer having a thickness of 0.5 μm was further formed thereon using an electroless gold plating solution of Uemura Kogyo Co., Ltd.
【００１２】次にスクリーン印刷機で共晶はんだペース
ト（石川金属製はんだペーストソルディムＢＨ６３Ｃ５
０１９Ｎ Ｂ５００Ｇ）を印刷、リフローし半球状はん
だバンプを形成した（図２―Ｈ）。最後にウエハをダイ
シングし、多数の半導体装置を得た。更にその後、室温
に放置したが外観の変化はなかった。尚、はんだバンプ
に直径０．２ｍｍの銅線をはんだ付けして引っ張り強度
を測定したところ、１００個の平均は３２１ｇ標準偏差
１５ｇであり、実装上問題ない強度を有していた。Next, a eutectic solder paste (Ishikawa Metal Solder Paste Soldim BH63C5) was used with a screen printing machine.
019NB500G) was printed and reflowed to form hemispherical solder bumps (FIG. 2-H). Finally, the wafer was diced to obtain a large number of semiconductor devices. After that, it was left at room temperature, but there was no change in appearance. Incidentally, when a copper wire having a diameter of 0.2 mm was soldered to the solder bumps and the tensile strength was measured, the average of 100 pieces was 321 g, the standard deviation was 15 g, and the strength was sufficient for mounting.
【００１３】[0013]
【実施例２】実施例１と同じウエハを用い、ドライフィ
ルムをラミネート後前記２００μｍ直径開口部上に同心
円になるよう直径２５０μｍの開口を持つようフォトマ
スクを通して露光量を４０ｍＪで露光し現像してレジス
トパターンを形成した。以降実施例１と全く同一の工程
で処理した。得られた半導体チップのはんだバンプと導
電性ペースト硬化物を含む面で切断し断面を観察した。
その結果、電極からはんだバンプをつなぐ導電ペースト
硬化物の形状は電極部分で直径２０５μｍ、はんだバン
プとの接続部で直径２５０μｍであった。そのため導電
ペースト硬化物部は素子のモールド樹脂から抜けない構
造となっていた。実施例１と同じ様にバンプの引っ張り
強度を測定したところ１００個の平均は６０２ｇ標準偏
差２７ｇであり極めて高い強度を有していた。Example 2 Using the same wafer as in Example 1, after laminating a dry film, exposing at a light exposure of 40 mJ through a photomask so as to have an opening of 250 μm in diameter so as to form a concentric circle on the opening of 200 μm in diameter, and developing. A resist pattern was formed. Thereafter, processing was performed in exactly the same steps as in Example 1. The obtained semiconductor chip was cut on a surface including the solder bumps and the cured conductive paste, and the cross section was observed.
As a result, the shape of the cured conductive paste connecting the electrodes to the solder bumps was 205 μm in diameter at the electrode portion and 250 μm in diameter at the connection with the solder bump. For this reason, the cured conductive paste portion has a structure that does not come off from the mold resin of the element. When the tensile strength of the bumps was measured in the same manner as in Example 1, the average of 100 bumps was 602 g and the standard deviation was 27 g, which was extremely high.
【００１４】[0014]
【比較例】実施例１の図２−Ｃの工程まで同様に進め
た。次に、電解メッキを施した。つまり、ダイシング時
点で削除される切り代部分で全電極に接続されたウエハ
外周部にマイナス電位、銅板をプラス電位としウエハを
硫酸銅メッキ液に挿入し、電解銅メッキを行った。COMPARATIVE EXAMPLE The process was carried out in the same manner up to the step shown in FIG. Next, electrolytic plating was performed. That is, the wafer was inserted into a copper sulfate plating solution at a negative potential and a copper plate at a positive potential at the outer peripheral portion of the wafer connected to all the electrodes at the cut-off portion removed at the time of dicing, and electrolytic copper plating was performed.
【００１５】メッキ電流密度はメッキの焼け（析出物が
多孔質状で赤茶色に変色すること）ない範囲で最大とし
たところ１．５Ａ／ｄｍ2となった。その結果レジスト
表面まで１００μｍのメッキ銅を析出させるため３００
分つまり６時間を要した。その後、１％苛性ソーダ液を
吹き付けることでドライフィルムを除去した。表面に封
止用エポキシ樹脂（米国アルファメタルズ社ＨＥＬ１
８）をペースト突起部が埋まる厚みまで封入し１６０度
３０分硬化させた。The maximum plating current density was 1.5 A / dm 2 when the plating current density was maximized in a range where burning of the plating was not caused (the precipitates were porous and discolored to reddish brown). As a result, 300 μm of plated copper was deposited up to the resist surface.
It took a minute or six hours. Thereafter, the dry film was removed by spraying a 1% sodium hydroxide solution. Epoxy resin for encapsulation on the surface (HEL Metals HEL1
8) was sealed until the paste protrusions were buried, and cured at 160 ° C. for 30 minutes.
【００１６】その後、表面をベルト研磨機を用い＃６０
０ベルトで研磨し導電性ペーストの硬化物上の封止用エ
ポキシ樹脂が完全に除去されるまで研磨した。最後に、
＃１０００、＃２０００ベルトで研磨した。次に導電性
ペースト硬化物のモールド樹脂表面に露出した面を酸洗
浄、パラジュウムによる活性化処理（上村工業（株）Ｋ
ＡＴ−４５０）後、無電解ニッケルメッキ（上村工業
（株）ニムデンＮＰＲ−４）でニッケル層５μｍを形成
し、更に、その上に上村工業（株）オーリカルＴＫＫ無
電解金メッキ液を使い金０．５μｍを形成した。After that, the surface is # 60 using a belt grinder.
This was polished with a zero belt and polished until the sealing epoxy resin on the cured product of the conductive paste was completely removed. Finally,
Polished with # 1000 and # 2000 belts. Next, the surface of the cured conductive paste exposed on the surface of the mold resin is washed with an acid and activated with palladium (Kemura Kogyo K.K.)
After AT-450), a nickel layer of 5 μm was formed by electroless nickel plating (Nimden NPR-4, Uemura Kogyo Co., Ltd.), and an electroless gold plating solution of Urimura Kogyo Co., Ltd. Orical TKK was used. 5 μm was formed.
【００１７】次にスクリーン印刷機で共晶はんだペース
ト（石川金属製はんだペーストソルディムＢＨ６３Ｃ５
０１９Ｎ Ｂ５００Ｇ）を印刷、リフローし半球状はん
だバンプを形成した。最後に、ウエハをダイシングし多
数の半導体装置を得た。しかし、ダイシング後室温で放
置したところ２日目にはんだバンプと封止樹脂の境界部
から青い結晶が析出してきた。分析したところ銅イオン
とナトリウムイオンが含まれていることが確認された。
これらのイオンは半導体装置の信頼性上悪影響の要因で
ある。Next, a eutectic solder paste (Ishikawa Metal Solder Paste Soldim BH63C5) was used with a screen printing machine.
019NB500G) was printed and reflowed to form hemispherical solder bumps. Finally, the wafer was diced to obtain a large number of semiconductor devices. However, when left at room temperature after dicing, blue crystals were deposited on the boundary between the solder bumps and the sealing resin on the second day. Analysis confirmed that copper ions and sodium ions were included.
These ions are a factor that adversely affects the reliability of the semiconductor device.
【００１８】[0018]
【発明の効果】以上の様に、１００μｍ程度の高さを持
つタワーバンプをメッキではなく、埋められた導電性ペ
ーストを硬化形成することによってメッキ液に長時間曝
す必要がない。メッキ液に長時間曝すために発生する金
属イオンなどによる汚染を無くし信頼性を高めることが
できた。また樹脂硬化物を含むバンプであり、しかもモ
ールド樹脂との混合物が存在するため、バンプがモール
ド樹脂に接着固定されかつ、樹脂の弾性を有するため熱
膨張率差による応力に破壊されることがないので熱負荷
による破壊耐性が高い。更に工程処理時間の短縮と設備
費を圧縮できコスト低減が達成できた。As described above, it is not necessary to expose the tower bump having a height of about 100 μm to the plating solution for a long time by forming the filled conductive paste by curing instead of plating. Contamination due to metal ions and the like generated due to prolonged exposure to the plating solution was eliminated, and reliability was improved. In addition, since the bumps include a cured resin and a mixture with the mold resin is present, the bumps are bonded and fixed to the mold resin and have elasticity of the resin, so that the bumps are not broken by stress due to a difference in thermal expansion coefficient. Therefore, the resistance to destruction by heat load is high. Further, the process processing time was shortened and the equipment cost was reduced, and the cost was reduced.
【図１】（Ａ）は、本発明の実施例１の断面模式図で、
（Ｂ）は、本発明の実施例２の断面模式図を示す。FIG. 1A is a schematic sectional view of Example 1 of the present invention.
(B) shows a schematic sectional view of Example 2 of the present invention.
【図２】本発明による半導体装置の製造工程のフロー図 （Ａ）半導体回路の形成（前工程）が終了し、電極７が
形成されバッファーコート９がされた物 （Ｂ）レジスト２２を塗布またはラミし、フォトマスク
２１を介して露光している状態 （Ｃ）レジストを現像し、バンプ形成予定箇所にレジス
ト開口部２３が形成された状態 （Ｄ）スクリーン印刷マスク２４を介してレジスト開口
部２３に導電性ペースト２６をスキージ２５により印刷
充填している状態 （Ｅ）加熱によりレジスト開口部２３の導電性ペースト
２６が硬化し導電性樹脂硬化物からなるバンプ２が形成
された状態 （Ｆ）ウエハ上の導電性樹脂硬化物からなるバンプ２以
上の厚みのモールド樹脂を塗布または射出成形しバンプ
２がモールド樹脂４に埋め込まれている状態 （Ｇ）モールド樹脂４から研磨しバンプ２が表面に露出
するまで研磨した状態 （Ｈ）表面に露出したバンプ２の表面にはんだの拡散防
止層５を形成後はんだボール３を形成した状態FIG. 2 is a flowchart of a manufacturing process of a semiconductor device according to the present invention. (A) A semiconductor circuit formation (pre-process) is completed, an electrode 7 is formed and a buffer coat 9 is formed. (B) A resist 22 is applied or coated. (C) A state in which the resist is developed and a resist opening 23 is formed at a position where a bump is to be formed. (D) A state in which the resist is developed through a screen printing mask 24. (E) A state in which the conductive paste 26 in the resist opening 23 is cured by heating to form bumps 2 made of a cured conductive resin (F) Wafer A state in which a mold resin having a thickness equal to or greater than the bump 2 made of the cured conductive resin is applied or injection-molded and the bump 2 is embedded in the mold resin 4 (G ) Polished from mold resin 4 and polished until bump 2 is exposed on the surface. (H) Solder ball 3 is formed after solder diffusion preventing layer 5 is formed on the surface of bump 2 exposed on the surface.
１ ：ウエハ ２ ：導電性樹脂硬化物からなるバンプ ２’：断面積が高さ方向変化している導電性樹脂硬化物 ３ ：はんだボール ４ ：モールド樹脂 ５ ：拡散防止層 ６ ：磁気収束チップ ７ ：電極 ８ ：半導体回路 ８’：磁気検出能力と有する半導体回路 ９ ：電極マスク層（バッファーコート） ２１ ：フォトマスク ２１ａ：遮光部 ２２ ：レジスト ２３ ：レジスト開口部 ２４ ：スクリーン印刷マスク ２５ ：スキージ ２６ ：導電性ペースト ２７ ：研磨されたモールド樹脂面 1: Wafer 2: Bump made of cured conductive resin 2 ': Cured conductive resin whose cross-sectional area changes in the height direction 3: Solder ball 4: Mold resin 5: Diffusion prevention layer 6: Magnetic focusing chip 7 : Electrode 8: Semiconductor circuit 8 ′: Semiconductor circuit having magnetic detecting ability 9: Electrode mask layer (buffer coat) 21: Photomask 21 a: Light shielding part 22: Resist 23: Resist opening 24: Screen printing mask 25: Squeegee 26 : Conductive paste 27: Polished mold resin surface
Claims (6)
た導電性ペースト硬化物がモールド樹脂に囲われ、該モ
ールド樹脂表面に前記導電性ペーストが露出し、前記導
電性ペーストが露出した領域に外部接続用の半田バンプ
が形成されていることを特徴とする半導体装置。1. A conductive paste cured product connected to an external connection electrode of a semiconductor chip is surrounded by a mold resin, the conductive paste is exposed on a surface of the mold resin, and an outside is formed in a region where the conductive paste is exposed. A semiconductor device having a connection solder bump formed thereon.
記半田バンプと前記導電性ペーストの間に拡散防止金属
層を備えることを特徴とする半導体装置。2. The semiconductor device according to claim 1, further comprising a diffusion preventing metal layer between said solder bump and said conductive paste.
いて、前記導電性ペースト硬化物中の樹脂と前記モール
ド樹脂の混合物が前記導電性ペーストと前記モールド樹
脂界面に存在することを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein a mixture of the resin in the cured conductive paste and the mold resin exists at an interface between the conductive paste and the mold resin. apparatus.
て、前記導電性ペースト硬化物の断面形状が前記モール
ド樹脂表面側よりも半導体チップ側の方が大きいことを
特徴とする半導体装置。4. The semiconductor device according to claim 1, wherein the cross-sectional shape of the cured conductive paste is larger on the semiconductor chip side than on the mold resin surface side.
記半導体チップの外部接続用電極部分にレジスト開口部
を形成し、該開口部に導電性ペーストを埋め込み、該導
電性ペーストを硬化して導電性ペースト硬化物を形成
し、前記レジストを除去し、前記導電性ペースト硬化物
が少なくとも埋まる厚みまでモールド樹脂を成形し、該
モールド樹脂の表面を前記導電性ペースト硬化物が露出
するまで研磨することを特徴とする半導体装置の製造方
法。5. A resist is formed on a semiconductor chip, a resist opening is formed in an external connection electrode portion of the semiconductor chip, a conductive paste is embedded in the opening, and the conductive paste is cured to form a conductive paste. Forming a conductive paste cured product, removing the resist, molding a mold resin to a thickness at which the conductive paste cured product is at least buried, and polishing the surface of the mold resin until the conductive paste cured product is exposed. A method for manufacturing a semiconductor device, comprising:
おいて、前記導電性ペースト硬化物が露出するまで研磨
した後、前記導電性ペースト硬化物が露出した領域に拡
散防止金属層を形成することを特徴とする半導体装置の
製造方法。6. The method of manufacturing a semiconductor device according to claim 5, wherein after the polishing of the cured conductive paste is exposed, a diffusion preventing metal layer is formed in a region where the cured conductive paste is exposed. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11201282A JP2001028379A (en) | 1999-07-15 | 1999-07-15 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11201282A JP2001028379A (en) | 1999-07-15 | 1999-07-15 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001028379A true JP2001028379A (en) | 2001-01-30 |
Family
ID=16438395
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11201282A Withdrawn JP2001028379A (en) | 1999-07-15 | 1999-07-15 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001028379A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002231856A (en) * | 2001-02-05 | 2002-08-16 | Sony Corp | Semiconductor device and its manufacturing method |
| WO2002097877A1 (en) * | 2001-05-28 | 2002-12-05 | Infineon Technologies Ag | A method of packaging a semiconductor chip |
| US6696317B1 (en) | 1999-11-04 | 2004-02-24 | Nec Electronics Corporation | Method of manufacturing a flip-chip semiconductor device with a stress-absorbing layer made of thermosetting resin |
| US7476968B2 (en) | 2003-10-09 | 2009-01-13 | Seiko Epson Corporation | Semiconductor device including an under electrode and a bump electrode |
| JP2011077230A (en) * | 2009-09-30 | 2011-04-14 | Seiko Instruments Inc | Electronic circuit component, and electronic apparatus |
| KR20200138632A (en) * | 2019-05-31 | 2020-12-10 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Integrated circuit package and method |
-
1999
- 1999-07-15 JP JP11201282A patent/JP2001028379A/en not_active Withdrawn
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6696317B1 (en) | 1999-11-04 | 2004-02-24 | Nec Electronics Corporation | Method of manufacturing a flip-chip semiconductor device with a stress-absorbing layer made of thermosetting resin |
| US6767761B2 (en) | 1999-11-04 | 2004-07-27 | Nec Electronics Corporation | Method of manufacturing a flip-chip semiconductor device with a stress-absorbing layer made of thermosetting resin |
| JP2002231856A (en) * | 2001-02-05 | 2002-08-16 | Sony Corp | Semiconductor device and its manufacturing method |
| JP4626063B2 (en) * | 2001-02-05 | 2011-02-02 | ソニー株式会社 | Manufacturing method of semiconductor device |
| WO2002097877A1 (en) * | 2001-05-28 | 2002-12-05 | Infineon Technologies Ag | A method of packaging a semiconductor chip |
| US7476968B2 (en) | 2003-10-09 | 2009-01-13 | Seiko Epson Corporation | Semiconductor device including an under electrode and a bump electrode |
| JP2011077230A (en) * | 2009-09-30 | 2011-04-14 | Seiko Instruments Inc | Electronic circuit component, and electronic apparatus |
| KR20200138632A (en) * | 2019-05-31 | 2020-12-10 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Integrated circuit package and method |
| US10950519B2 (en) | 2019-05-31 | 2021-03-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method |
| KR102308482B1 (en) * | 2019-05-31 | 2021-10-07 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Integrated circuit package and method |
| US11626339B2 (en) | 2019-05-31 | 2023-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method |
| US11935804B2 (en) | 2019-05-31 | 2024-03-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method |
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