JP2001019745A - Semiconductor device and its production - Google Patents

Semiconductor device and its production

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Publication number
JP2001019745A
JP2001019745A JP11192810A JP19281099A JP2001019745A JP 2001019745 A JP2001019745 A JP 2001019745A JP 11192810 A JP11192810 A JP 11192810A JP 19281099 A JP19281099 A JP 19281099A JP 2001019745 A JP2001019745 A JP 2001019745A
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor element
underfill material
circuit board
flux
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11192810A
Other languages
Japanese (ja)
Inventor
Yuji Sakamoto
有史 坂本
Masahiro Wada
雅浩 和田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Priority to JP11192810A priority Critical patent/JP2001019745A/en
Publication of JP2001019745A publication Critical patent/JP2001019745A/en
Pending legal-status Critical Current

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  • Compositions Of Macromolecular Compounds (AREA)
  • Epoxy Resins (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device excellent in reliability in the same manner as that of a conventional device in an area packaging method for sealing a semiconductor element, especially a semiconductor element having solder electrodes on a circuit surface by using an underfilling material. SOLUTION: This method for producing a semiconductor device comprising carrying out a flux treatment of solder electrodes and a circuit substrate, joining the circuit substrate to a semiconductor element, then sealing gaps between the semiconductor element and the circuit substrate with an underfilling material comprising an epoxy resin and an amine compound without conducting flux cleaning in an area packaging method for joining the circuit substrate to the semiconductor element having the solder electrodes installed in the circuit surface. The semiconductor element is prepared by the method.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、信頼性に優れ、か
つ組み立て工程を簡略できる半導体装置の製造方法及び
半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method and a semiconductor device which are excellent in reliability and can simplify an assembling process.

【0002】[0002]

【従来の技術】近年、半導体パッケージの軽薄短小化の
技術革新は目覚しいものがあり、さまざまなパッケージ
構造が提唱され、製品化されている。従来のリードフレ
ーム接合に代わり、半田のような突起電極により、回路
基板(マザーボード)に接合するエリア実装方式は特に重
要となってきている。
2. Description of the Related Art In recent years, there have been remarkable technological innovations in reducing the size and thickness of semiconductor packages, and various package structures have been proposed and commercialized. An area mounting method of bonding to a circuit board (mother board) by using a projecting electrode such as solder instead of the conventional lead frame bonding has become particularly important.

【0003】エリア実装方式の中で、半導体チップの回
路面に直接突起電極が具備されたフリップチップはパッ
ケージを最小化できる方法のひとつである。フリップチ
ップ実装は、半田電極の場合、半田電極の表面の酸化膜
を除去するためにフラックスで処理した後リフロー等の
方法で接合する。その為半田電極、回路基板等の周囲に
フラックスが残存するためこれを除去する洗浄を行った
後、液状樹脂(アンダーフィル材)で封止を行う。その
理由としては、直接回路基板(マザーボード)に突起電極
で接合すると、温度サイクル試験のような信頼性試験を
行った場合、半導体素子と回路基板の線膨張係数の差に
より電極接合部の電気的不良が発生するためである。
[0003] In the area mounting method, a flip chip in which a protruding electrode is directly provided on a circuit surface of a semiconductor chip is one of methods for minimizing a package. In flip-chip mounting, in the case of a solder electrode, the surface is treated with a flux to remove an oxide film on the surface of the solder electrode, and then joined by a method such as reflow. Therefore, the flux is left around the solder electrodes, the circuit board, and the like, so that cleaning is performed to remove the flux, followed by sealing with a liquid resin (underfill material). The reason is that when a bump is directly joined to a circuit board (motherboard) with a protruding electrode, when a reliability test, such as a temperature cycle test, is performed, the difference in the linear expansion coefficient between the semiconductor element and the circuit board causes the electrical connection of the electrode joint to become large. This is because a defect occurs.

【0004】アンダーフィル材による封止は、半導体素
子の一辺または複数面に液状封止樹脂を塗布し、毛細管
現象を利用して樹脂を回路基板と半導体素子の間隙に流
し込ませる。しかし、この方法はフラクッス処理、洗浄
を行うため工程が長くなりかつ洗浄廃液の処理問題等環
境管理を厳しくしなければならない。しかし、フラック
ス洗浄を省略するとアンダーフィル材との密着性が著し
く低下し、界面での剥離を生じ、強いては半田電極の電
気的接続信頼性にも影響を及ぼすおそれがある。
In sealing with an underfill material, a liquid sealing resin is applied to one side or a plurality of surfaces of a semiconductor element, and the resin is poured into a gap between the circuit board and the semiconductor element by utilizing a capillary phenomenon. However, this method requires a long process for performing fluxing and cleaning, and requires strict environmental management such as a problem of treating a cleaning waste liquid. However, if the flux cleaning is omitted, the adhesiveness with the underfill material is significantly reduced, peeling occurs at the interface, and the electrical connection reliability of the solder electrode may be adversely affected.

【0005】[0005]

【発明が解決しようとする課題】本発明は、アンダーフ
ィル材を用いて半導体素子、特に回路面に半田電極を有
する半導体素子を封止するエリア実装法において、フラ
ックス洗浄を行わずに従来と同様の信頼性に優れた半導
体装置を提供することにある。
SUMMARY OF THE INVENTION The present invention relates to an area mounting method for sealing a semiconductor element, particularly a semiconductor element having a solder electrode on a circuit surface, by using an underfill material. To provide a semiconductor device having excellent reliability.

【0006】[0006]

【課題を解決するための手段】本発明は、これらの問題
を解決するため鋭意検討した結果、回路基板に、回路面
に半田電極が具備された半導体素子を接合するエリア実
装法において、接合前に該半田電極及び該回路基板にフ
ラックス処理を施し、接合後、フラックス洗浄無しにア
ンダーフィル材で半導体素子と回路基板の間隙を封止し
て製造する半導体装置の製造方法である。
The present invention has been made as a result of intensive studies to solve these problems. As a result, the present invention relates to an area mounting method for bonding a semiconductor element having a solder electrode on a circuit surface to a circuit board. A flux treatment for the solder electrodes and the circuit board, and after bonding, sealing a gap between the semiconductor element and the circuit board with an underfill material without flux cleaning, thereby manufacturing the semiconductor device.

【0007】更に好ましい形態としては、該アンダーフ
ィル材が、液状エポキシ樹脂、硬化剤としてアミン化合
物からなり、該アンダーフィル材が平均粒径10ミクロ
ン以下、最大粒径50ミクロン以下の球状フィラーを含
み、該アミン化合物が液状芳香族アミンであり、該液状
芳香族アミンがジエチルジアミノジフェニルメタンであ
り、該フラックスが有機カルボン酸である半導体装置の
製造方法である。また、上記の半導体装置の製造方法に
より製造された半導体装置である。
In a more preferred embodiment, the underfill material comprises a liquid epoxy resin and an amine compound as a curing agent, and the underfill material contains a spherical filler having an average particle size of 10 μm or less and a maximum particle size of 50 μm or less. A semiconductor device, wherein the amine compound is a liquid aromatic amine, the liquid aromatic amine is diethyldiaminodiphenylmethane, and the flux is an organic carboxylic acid. Further, the present invention is a semiconductor device manufactured by the above-described method for manufacturing a semiconductor device.

【0008】[0008]

【発明の実施の形態】本発明で用いられるアンダーフィ
ル材の液状エポキシ樹脂は、既存のビスフェノール系ジ
グリシジルエーテル類、フェノールノボラックとエピク
ロルヒドリンとの反応で得られるグリシジルエーテルで
常温で液状のもの等、またはそれらを混合したものが挙
げられる。また、これらの液状樹脂にジヒドロキシナフ
タレンのジグリシジルエーテル、テトラメチルビフェノ
ールのジグリシジルエーテル等の結晶性のエポキシ樹脂
を混合し、液状にしたものを使用することもできる。
BEST MODE FOR CARRYING OUT THE INVENTION The liquid epoxy resin of the underfill material used in the present invention includes existing bisphenol-based diglycidyl ethers, glycidyl ether obtained by reacting phenol novolak with epichlorohydrin and liquid at room temperature, and the like. Or those obtained by mixing them are mentioned. Further, a liquid epoxy resin such as a diglycidyl ether of dihydroxynaphthalene or a diglycidyl ether of tetramethylbiphenol may be mixed with these liquid resins to make them liquid.

【0009】次にエポキシ樹脂の硬化剤としてはアミン
化合物であり、アミン化合物の例としては、脂肪族ポリ
アミン、ポリアミドアミン、芳香族アミン、イミダゾー
ル類、グアニジン類等が挙げられ、その中で耐熱性、接
着性を含めた信頼性を考慮し芳香族アミンが好適であ
る。更に好ましくは、3,3’−ジエチル−4、4’−
ジアミノジフェニルメタンであり、これは性状が常温で
液状であり、アンダーフィル材に好ましい流動性を付与
する。
Next, an amine compound is used as a curing agent for the epoxy resin. Examples of the amine compound include aliphatic polyamines, polyamidoamines, aromatic amines, imidazoles, and guanidines. Aromatic amines are preferable in consideration of reliability including adhesiveness. More preferably, 3,3'-diethyl-4,4'-
Diaminodiphenylmethane, which is liquid at room temperature and provides favorable fluidity to the underfill material.

【0010】全エポキシ樹脂に対するアミン化合物の添
加量は、エポキシ基1モル数に対し0.8〜1.2の範
囲であることが好ましい。これらの範囲を外れると、架
橋密度が減少し、特に接着強度が低下するという問題が
起こる。
The amount of the amine compound to be added to all the epoxy resins is preferably in the range of 0.8 to 1.2 with respect to 1 mole of epoxy group. Outside of these ranges, there is a problem that the crosslink density decreases, and in particular, the adhesive strength decreases.

【0011】更に本発明で用いられるアンダーフィル材
には上記の樹脂の他に、硬化促進剤を用いることがで
き、一般的にエポキシ樹脂の硬化促進剤を用いることが
できる。例えば、リン化合物、第三級アミン、カルボン
酸等をあげることができる。
Further, in addition to the above resins, a curing accelerator can be used in the underfill material used in the present invention, and a curing accelerator of an epoxy resin can be generally used. For example, phosphorus compounds, tertiary amines, carboxylic acids and the like can be mentioned.

【0012】更に、アンダーフィル材にはフィラーを用
いることができ、フィラーの例としては、炭酸カルシウ
ム、シリカ、アルミナ、窒化アルミ等がが挙げられる。
用途によりこれらを複数混合してもよいが、信頼性、コ
ストの点でシリカが好ましい。またフィラーのより好ま
しい性状としては、平均粒径が10ミクロン以下、最大
粒径が50ミクロン以下である。平均粒径が10ミクロ
ンを越えるまたは最大粒径が50ミクロンを越えると樹
脂の流動性が悪くなり、半導体素子と回路基板の間隙に
樹脂が流入しなくなる可能性がある。
Further, a filler can be used as the underfill material, and examples of the filler include calcium carbonate, silica, alumina, aluminum nitride and the like.
A plurality of these may be mixed depending on the application, but silica is preferred in terms of reliability and cost. As more preferable properties of the filler, the average particle diameter is 10 microns or less, and the maximum particle diameter is 50 microns or less. If the average particle size exceeds 10 microns or the maximum particle size exceeds 50 microns, the fluidity of the resin deteriorates, and the resin may not flow into the gap between the semiconductor element and the circuit board.

【0013】フィラーの添加量は特に制限がないが、
封止樹脂としての特性(耐湿性、作業性等)を保つため
液状封止樹脂組成物の80重量%以下であることが好ま
しい。80重量%を越えると樹脂粘度が上がりすぎ流動
性に支障をきたす。またフィラーの形状は球状であるこ
とが好ましい。いわゆる破砕型フィラーの場合は樹脂の
流動性を著しく低下させるからである。
The amount of the filler added is not particularly limited,
In order to maintain the properties (moisture resistance, workability, etc.) of the sealing resin, it is preferably 80% by weight or less of the liquid sealing resin composition. If the content exceeds 80% by weight, the viscosity of the resin becomes too high, and the fluidity is hindered. The shape of the filler is preferably spherical. This is because in the case of a so-called crush type filler, the fluidity of the resin is significantly reduced.

【0014】本発明のアンダーフィル材は、前記液状エ
ポキシ樹脂、硬化剤、硬化促進剤、フィラー以外に、必
要に応じて顔料、染料、レベリング剤、消泡剤、カップ
リング材等の添加剤を混合し、真空脱泡することにより
製造することができる。特に反応性が高いアミンの場合
は使用直前にエポキシ樹脂と混合して使用する。
The underfill material of the present invention may contain additives such as a pigment, a dye, a leveling agent, a defoaming agent, and a coupling material, if necessary, in addition to the liquid epoxy resin, the curing agent, the curing accelerator, and the filler. It can be manufactured by mixing and vacuum defoaming. Particularly in the case of highly reactive amines, they are used by mixing with an epoxy resin immediately before use.

【0015】次に本発明で使用されるフラックスは特に
有機カルボン酸系化合物が好ましい。その例としては、
ロジン、リンゴ酸、アスコルビン酸、アジピン酸等が挙
げられる。なお、本発明は、回路基板に直接素子を接合
する場合の封止だけでなく、一旦インタポーザーに接合
してアンダーフィル材で封止し、更にインタポーザーか
ら再配線を行い下部より半田電極を形成して回路基板に
接合する場合の上記インターポーザーと回路基板の間隙
の封止にも用いることが出来る。
The flux used in the present invention is preferably an organic carboxylic acid compound. For example,
Rosin, malic acid, ascorbic acid, adipic acid and the like can be mentioned. In addition, the present invention not only seals when the element is directly joined to the circuit board, but also temporarily joins to the interposer, seals it with an underfill material, further performs rewiring from the interposer, and removes the solder electrode from the lower part. It can also be used to seal the gap between the interposer and the circuit board when formed and joined to a circuit board.

【0016】半導体素子より本発明の方法を用いて製作
された半導体装置は、従来の品質を維持しながら生産性
の高い半導体装置であり、コンピュータを始めあらゆる
電子機器、電気機器に用いることができる。半導体素子
の製造方法、半導体装置のその他の製造工程は従来の公
知の方法を用いることができる。
A semiconductor device manufactured by using the method of the present invention from a semiconductor element is a semiconductor device having high productivity while maintaining the conventional quality, and can be used for all electronic devices and electric devices including computers. . For a method for manufacturing a semiconductor element and other manufacturing steps for a semiconductor device, a conventionally known method can be used.

【0017】[0017]

【実施例】<実施例1>液状エポキシ樹脂として、エポ
キシ等量165のビスフェノールF型エポキシ樹脂10
0重量部、アミン化合物としてキシリレンジアミン35
重量部、カップリング剤として、γ-ク゛リシシ゛ルオキシフ゜ロヒ゜ルト
リメトキシシラン2重量部、フィラーとして最大粒径20ミクロ
ン、平均粒径5ミクロンの球状シリカを150重量部混
錬し、真空脱泡してアンダーフィル材を得た。樹脂特性
として以下の評価を行った。 <実施例2>実施例1において、アミン化合物として
3,3’−ジエチル−4、4’−ジアミノジフェニルメ
タン(カヤハ―ト゛A-A、日本化薬社製)38重量部とした以
外は実施例1と同様にアンダーフィル材を調製し、評価
を行った。
<Example 1> As a liquid epoxy resin, bisphenol F type epoxy resin 10 having an epoxy equivalent of 165 was used.
0 parts by weight, xylylenediamine 35 as an amine compound
Parts by weight, 2 parts by weight of γ-glycidyloxyfluoropropyltrimethoxysilane as a coupling agent, 150 parts by weight of spherical silica having a maximum particle size of 20 μm and an average particle size of 5 μm as a filler, vacuum degassing and under Fill material was obtained. The following evaluations were made as resin characteristics. Example 2 Example 1 was repeated except that the amine compound was 38 parts by weight of 3,3′-diethyl-4,4′-diaminodiphenylmethane (Kayahart AA, manufactured by Nippon Kayaku Co., Ltd.). Similarly, an underfill material was prepared and evaluated.

【0018】<比較例1>実施例1において、アミン化
合物の代わりに酸無水物硬化材としてメチルヘキサヒド
ロフタル酸無水物90部、硬化促進剤としてイミダゾー
ル(商品名2E4MZ、四国化成製)0.5重量部を新たに
加えた以外は実施例1と同様にアンダーフィル材を調製
し、評価を行った。 <比較例2>実施例1において、アミン化合物の代わり
に硬化剤としてビスフェノールF60部、希釈剤として
ブチルセロソルブアセテート5重量部を新たに加えた以
外は実施例1と同様にアンダーフィル材を調製し、評価
を行った。
Comparative Example 1 In Example 1, instead of the amine compound, 90 parts of methylhexahydrophthalic anhydride was used as an acid anhydride curing agent and imidazole (trade name: 2E4MZ, manufactured by Shikoku Chemicals) was used as a curing accelerator. An underfill material was prepared and evaluated in the same manner as in Example 1 except that 5 parts by weight was newly added. <Comparative Example 2> An underfill material was prepared in the same manner as in Example 1 except that 60 parts of bisphenol F was added as a curing agent and 5 parts by weight of butyl cellosolve acetate as a diluent in place of the amine compound. An evaluation was performed.

【0019】(1)接着強度−1及び2:BTレジン製
回路基板の上に、ソルダーレジスト(太陽インキ社製P
SRー4000AUS5/CA−AUS2)を用いて形
成した表面をロジン系フラックスで処理した。更にアン
ダーフィル材を塗布し、その上に2×2mm角のシリコ
ーンチップを載置し、150℃、180分で硬化接着さ
せ、常温における接着力をプッシュプルゲージで測定し
た(接着強度−1)。更に高温高湿処理(85℃、85
%RH、96時間)した後、常温における接着力を測定
した(接着強度−2)。
(1) Adhesive strength -1 and 2: A solder resist (Taiyo Ink Co., Ltd.) is provided on a BT resin circuit board.
The surface formed using SR-4000AUS5 / CA-AUS2) was treated with a rosin-based flux. Further, an underfill material was applied, a 2 × 2 mm silicone chip was placed on the underfill material, and cured and adhered at 150 ° C. for 180 minutes, and the adhesive force at room temperature was measured with a push-pull gauge (adhesive strength-1). . High temperature and high humidity treatment (85 ° C, 85
% RH, 96 hours), the adhesive strength at room temperature was measured (adhesive strength-2).

【0020】(2)耐半田クラック性:BTレジン製回
路基板に10mm角の半田電極(電極高さ:80ミクロ
ン、電極間隔:200ミクロン、電極数:800個)が
具備された半導体素子をロジン系フラックスを用いて接
合し、フラックスを残した状態にする。次にこの試験片
を80℃のホットプレートに載置し、アンダーフィル材
を素子の一辺に塗布し、アンダーフィル材をその間隙に
充填させ、150℃、3時間で硬化させた試験片を用い
てJEDECレベル3(30度、60%RH処理後24
0度リフロー処理)の試験を行った。評価は超音波探診
装置を用いて剥離の状態を調べた(サンプル数N=
6)。
(2) Resistance to solder cracking: A semiconductor element provided with a 10 mm square solder electrode (electrode height: 80 μm, electrode spacing: 200 μm, number of electrodes: 800) on a BT resin circuit board is rosin-coated. Bonding is performed using a system flux to leave the flux. Next, the test piece was placed on a hot plate at 80 ° C., an underfill material was applied to one side of the element, the underfill material was filled in the gap, and a test piece cured at 150 ° C. for 3 hours was used. JEDEC level 3 (30 degrees, 24 hours after 60% RH treatment)
0 degree reflow treatment). For the evaluation, the state of peeling was examined using an ultrasonic probe (the number of samples N =
6).

【0021】(3)耐T/C性試験:(2)で作製した
試験片を用いて熱サイクル試験(−55℃〜125℃)
を行い、100サイクルごとに剥離、クラックの有無を
調べ、1000サイクルまで試験を行った(N=1
0)。評価は初期不良がおきた回数で評価した。
(3) T / C resistance test: Thermal cycle test (-55 ° C. to 125 ° C.) using the test piece prepared in (2)
Was performed, and the presence or absence of peeling and cracking was checked every 100 cycles, and the test was performed up to 1000 cycles (N = 1).
0). The evaluation was based on the number of times the initial failure occurred.

【0022】上記の評価結果を表1に示す。Table 1 shows the above evaluation results.

【表1】 [Table 1]

【0023】[0023]

【発明の効果】本発明の製造方法は、エポキシ樹脂とア
ミン化合物の組み合わせを用いて、フラックス洗浄を行
わなくとも、接着性を維持しつつ、信頼性を維持できる
エリア実装方式の半導体装置を得る方法であり、半導体
装置の製造において工程を簡略化できる為生産性の高い
半導体装置を得ることができる。
According to the manufacturing method of the present invention, an area mounting type semiconductor device which can maintain the adhesiveness and maintain the reliability without performing flux cleaning using a combination of an epoxy resin and an amine compound is obtained. This is a method and can simplify a process in manufacturing a semiconductor device, so that a semiconductor device with high productivity can be obtained.

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 4J002 CD031 CD051 CD061 DE147 DE237 DF017 DJ017 EN036 EN076 ER026 EU116 FA087 FD017 FD146 FD150 4J036 AD01 AD07 AD08 AF01 AJ14 DC02 DC06 DC10 DC41 DC48 JA07 KA01 4M109 AA01 BA04 CA05 EA03 EB02 EB04 EB06 EB07 EB08 EB12 EB16 EC09 EC20  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4J002 CD031 CD051 CD061 DE147 DE237 DF017 DJ017 EN036 EN076 ER026 EU116 FA087 FD017 FD146 FD150 4J036 AD01 AD07 AD08 AF01 AJ14 DC02 DC06 DC10 DC41 DC48 JA07 KA01 4M109 AA03 EB04 EB07 EB07 EB08 EB12 EB16 EC09 EC20

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 回路基板に、回路面に半田電極が具備さ
れた半導体素子を接合するエリア実装法において、接合
前に該半田電極及び該回路基板にフラックス処理を施
し、接合後、フラックス洗浄無しにアンダーフィル材で
該半導体素子と該回路基板の間隙を封止して製造するこ
とを特徴とする半導体装置の製造方法。
In an area mounting method for joining a semiconductor element having a solder electrode on a circuit surface to a circuit board, a flux treatment is applied to the solder electrode and the circuit board before joining, and no flux cleaning is performed after joining. And manufacturing the semiconductor device by sealing a gap between the semiconductor element and the circuit board with an underfill material.
【請求項2】 該アンダーフィル材が、液状エポキシ樹
脂、硬化剤としてアミン化合物からなる請求項1記載の
半導体装置の製造方法。
2. The method according to claim 1, wherein the underfill material comprises a liquid epoxy resin and an amine compound as a curing agent.
【請求項3】 該アンダーフィル材が、平均粒径10ミ
クロン以下、最大粒径50ミクロン以下の球状フィラー
を含む請求項1又は2記載の半導体装置の製造方法。
3. The method for manufacturing a semiconductor device according to claim 1, wherein said underfill material includes a spherical filler having an average particle diameter of 10 μm or less and a maximum particle diameter of 50 μm or less.
【請求項4】 該アミン化合物が液状芳香族アミンであ
る請求項2記載の半導体装置の製造方法。
4. The method according to claim 2, wherein said amine compound is a liquid aromatic amine.
【請求項5】 該液状芳香族アミンが3,3’−ジエチ
ル−4、4’−ジアミノジフェニルメタンである請求項
4記載の半導体装置の製造方法。
5. The method according to claim 4, wherein the liquid aromatic amine is 3,3′-diethyl-4,4′-diaminodiphenylmethane.
【請求項6】 該フラックスが有機カルボン酸である請
求項1記載の半導体装置の製造方法。
6. The method according to claim 1, wherein the flux is an organic carboxylic acid.
【請求項7】 請求項1記載の半導体装置の製造方法に
より製造されたことを特徴とする半導体装置。
7. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1.
JP11192810A 1999-07-07 1999-07-07 Semiconductor device and its production Pending JP2001019745A (en)

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Application Number Priority Date Filing Date Title
JP11192810A JP2001019745A (en) 1999-07-07 1999-07-07 Semiconductor device and its production

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Publication Number Publication Date
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Country Link
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