JP2001007327A - High breakdown voltage semiconductor device - Google Patents
High breakdown voltage semiconductor deviceInfo
- Publication number
- JP2001007327A JP2001007327A JP11175517A JP17551799A JP2001007327A JP 2001007327 A JP2001007327 A JP 2001007327A JP 11175517 A JP11175517 A JP 11175517A JP 17551799 A JP17551799 A JP 17551799A JP 2001007327 A JP2001007327 A JP 2001007327A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- film
- resistive film
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 94
- 230000015556 catabolic process Effects 0.000 title claims abstract description 55
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 92
- 229920005591 polysilicon Polymers 0.000 claims abstract description 92
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 239000002344 surface layer Substances 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims description 20
- 150000004767 nitrides Chemical class 0.000 claims description 19
- 230000007704 transition Effects 0.000 claims description 10
- 239000004020 conductor Substances 0.000 abstract description 30
- 239000011347 resin Substances 0.000 abstract description 20
- 229920005989 resin Polymers 0.000 abstract description 20
- 239000011229 interlayer Substances 0.000 abstract description 17
- 238000002161 passivation Methods 0.000 abstract description 9
- 230000032683 aging Effects 0.000 abstract 1
- 238000000465 moulding Methods 0.000 abstract 1
- 230000005684 electric field Effects 0.000 description 13
- 150000002500 ions Chemical class 0.000 description 9
- 239000010410 layer Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000002040 relaxant effect Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 101100454433 Biomphalaria glabrata BG01 gene Proteins 0.000 description 1
- 108091006146 Channels Proteins 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、スイッチング電源
用、モーター駆動用、あるいは蛍光燈インバータ駆動用
などの高耐圧半導体装置に関し、特に、高耐圧パワーＩ
Ｃを構成する高耐圧横型パワーデバイスに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high withstand voltage semiconductor device for a switching power supply, for driving a motor, or for driving a fluorescent lamp inverter.
The present invention relates to a high withstand voltage lateral power device constituting C.
【０００２】[0002]
【従来の技術】スイッチング電源用、モーター駆動用、
あるいは蛍光燈インバータ駆動用にＰＷＭ制御回路によ
る駆動方式が普及し、この制御回路の高機能化、小型
化、低コスト化、高信頼性化および低消費電力化などに
対する要求が強い。この要求により、高耐圧パワー素子
と制御回路を集積したパワーＩＣの需要が高まってい
る。2. Description of the Related Art Switching power supplies, motor drives,
Alternatively, a driving method using a PWM control circuit has become widespread for driving a fluorescent lamp inverter, and there is a strong demand for higher performance, smaller size, lower cost, higher reliability, and lower power consumption of the control circuit. This demand has increased the demand for a power IC in which a high-voltage power element and a control circuit are integrated.
【０００３】商用１００〜２００Ｖの電源装置を駆動す
る電源用パワーＩＣは、電源装置に搭載されているトラ
ンスを駆動するため、トランスで発生する過電圧を考慮
すると７００Ｖクラスの素子耐圧が必要である。この７
００Ｖクラスの素子は、制御部との集積化を容易とする
ため、図１３に示すような横型構造の高耐圧半導体装置
にして、さらに、高抵抗（低不純物濃度）の基板やドリ
フト領域が必要となる（電気学会研究会資料EDD-93-21,
p21-29,宇野利彦他「ＩＰＤ用高耐圧横型パワーＭＯＳ
ＦＥＴの低オン抵抗化」）。A power IC for a power supply for driving a commercial power supply of 100 to 200 V drives a transformer mounted on the power supply, and therefore requires an element withstand voltage of 700 V class in consideration of an overvoltage generated in the transformer. This 7
In order to facilitate the integration with the control unit, the 00V class element is required to be a high breakdown voltage semiconductor device having a horizontal structure as shown in FIG. 13 and further require a substrate and a drift region having a high resistance (low impurity concentration). (The Institute of Electrical Engineers of Japan, EDD-93-21,
p21-29, Toshihiko Uno et al. "High Voltage Horizontal Power MOS for IPD
Low on-resistance of FET ”).
【０００４】図１３は、従来の高耐圧半導体装置の要部
断面図である。ｐ基板１の表面層に選択的にｎ+ ソース
領域２と、ｐ基板１とのコンタクトをとるめのｐ+ 基板
コンタクト領域３と、ｎ+ ソース領域２と離してｎウエ
ル領域４とを形成し、ｎウエル領域４の表面層に選択的
にｎ+ ドレイン領域５を形成する。ｎ+ ソース領域２と
ｎウエル領域４に挟まれたｐ基板１上にゲート酸化膜６
を介してゲート電極７を形成する。ｎ+ ソース領域２上
とｎ+ ドレイン領域５上にソース電極１２とドレイン電
極１３をそれぞれ形成する。ｎウエル領域４上に熱酸化
膜８を形成し、熱酸化膜８上に層間絶縁膜６０１を形成
し、その層間絶縁膜６０１上に配線用の第１導電膜６０
２と第２導電膜６０３を形成する。さらに、表面をパッ
シベーション膜６０４で被覆して、その上をモールド樹
脂６２０で被覆する。尚、前記の第１導電膜６０２、第
２導電膜６０３、ソース電極１２およびドレイン電極１
３を同一材料で同時に形成してもよい。FIG. 13 is a sectional view of a main part of a conventional high breakdown voltage semiconductor device. An n + source region 2 is selectively formed in a surface layer of p substrate 1, ap + substrate contact region 3 for making contact with p substrate 1, and an n well region 4 separated from n + source region 2. Then, n + drain region 5 is selectively formed on the surface layer of n well region 4. Gate oxide film 6 on p substrate 1 sandwiched between n + source region 2 and n well region 4
The gate electrode 7 is formed through the step. A source electrode 12 and a drain electrode 13 are formed on the n + source region 2 and the n + drain region 5, respectively. A thermal oxide film 8 is formed on the n-well region 4, an interlayer insulating film 601 is formed on the thermal oxide film 8, and a first conductive film 60 for wiring is formed on the interlayer insulating film 601.
2 and a second conductive film 603 are formed. Further, the surface is covered with a passivation film 604, and the surface is covered with a mold resin 620. The first conductive film 602, the second conductive film 603, the source electrode 12, and the drain electrode 1
3 may be simultaneously formed of the same material.
【０００５】前記の構造において、モールド樹脂内部に
は、通常、残留置換体（塩素など）が含まれており、高
耐圧半導体装置の動作中に、この残留置換体は水分や高
電界で容易に可動イオン化する（図中ではマイナスイオ
ンで示す）。このイオンの密度は１０13個／ｃｍ2 程度
と見積もられており、横型高耐圧半導体装置に形成され
る電界を乱し数１００Ｖの耐圧低下を起こすに十分な量
を含んでいる。したがって図１３の構造ではモールド樹
脂界面の可動イオンにより、耐圧低下、耐圧の径時変化
が生じる。In the above structure, the mold resin usually contains a residual substitute (chlorine or the like), and the residual substitute is easily exposed to moisture or a high electric field during the operation of the high breakdown voltage semiconductor device. Mobile ionization (indicated by negative ions in the figure). The density of these ions is estimated to be about 10 13 / cm 2, and includes an amount sufficient to disturb the electric field formed in the lateral high withstand voltage semiconductor device and cause a withstand voltage drop of several hundred volts. Therefore, in the structure of FIG. 13, the withstand voltage is reduced and the withstand voltage changes with time due to the movable ions at the mold resin interface.
【０００６】これを解決するために、つぎの構造が提案
されている。図１４は、従来の高耐圧半導体装置の要部
断面図である。ｐ基板１の表面層に選択的にｎ+ ソース
領域２と、ｐ基板１とのコンタクトをとるめのｐ+ 基板
コンタクト領域３と、ｎ+ ソース領域２と離してｎウエ
ル領域４とを形成し、ｎウエル領域４の表面層に選択的
にｎ+ ドレイン領域５を形成する。ｎ+ ソース領域２と
ｎウエル領域４に挟まれたｐ基板１上にゲート酸化膜６
を介してゲート電極７を形成する。ｎ+ ソース領域２上
とｎ+ ドレイン領域５上にソース電極１２とドレイン電
極１３をそれぞれ形成する。ｎウエル領域４上に熱酸化
膜８を形成し、熱酸化膜８上に高抵抗ポリシリコン抵抗
体７０９を形成する。この高抵抗ポリシリコン抵抗体７
０９の両端部に第１高濃度領域７１０と第２高濃度領域
７１１を形成し、第１高濃度領域７１０上と第２高濃度
領域７１１上に第１接続導体７１４と第２接続導体７１
５をそれぞれ形成する。また、高抵抗ポリシリコン抵抗
体７０９上に層間絶縁膜７１６を形成する。ソース電極
１２と第１接続導体７１０を第１導電膜７１７で接続
し、ドレイン電極１３と第２接続導体７１５を第２導電
膜７１８で接続する。第１導電膜７１７上および第２導
電膜７１８上および層間絶縁膜７１６が露出してる箇所
の上にパッシベーション膜７１９を被覆し、さらに、そ
の上をモールド樹脂７２０で被覆する。In order to solve this, the following structure has been proposed. FIG. 14 is a sectional view of a main part of a conventional high breakdown voltage semiconductor device. An n + source region 2 is selectively formed in a surface layer of p substrate 1, ap + substrate contact region 3 for making contact with p substrate 1, and an n well region 4 separated from n + source region 2. Then, n + drain region 5 is selectively formed on the surface layer of n well region 4. Gate oxide film 6 on p substrate 1 sandwiched between n + source region 2 and n well region 4
The gate electrode 7 is formed through the step. A source electrode 12 and a drain electrode 13 are formed on the n + source region 2 and the n + drain region 5, respectively. A thermal oxide film is formed on the n-well region, and a high-resistance polysilicon resistor is formed on the thermal oxide film. This high resistance polysilicon resistor 7
09, a first high-concentration region 710 and a second high-concentration region 711 are formed at both ends, and a first connection conductor 714 and a second connection conductor 71 are formed on the first high-concentration region 710 and the second high-concentration region 711.
5 are formed. Further, an interlayer insulating film 716 is formed on the high-resistance polysilicon resistor 709. The source electrode 12 and the first connection conductor 710 are connected by a first conductive film 717, and the drain electrode 13 and the second connection conductor 715 are connected by a second conductive film 718. A passivation film 719 is coated on the first conductive film 717 and the second conductive film 718 and on a portion where the interlayer insulating film 716 is exposed.
【０００７】この構造では、ソース電極１２とドレイン
電極１３に接続している高抵抗ポリシリコン抵抗体７０
９に、ソース・ドレイン間の高電圧を印加して、微小な
リーク電流を流して、均一な電位分布を高抵抗ポリシリ
コン抵抗体７０９に形成する。この均一な電位分布が熱
酸化膜８を通して、ｎウエル領域に反映して、ｎウエル
領域４やｐ基板１に形成される電位分布も均一になる。
このようにして前記問題を回避できる。In this structure, the high-resistance polysilicon resistor 70 connected to the source electrode 12 and the drain electrode 13
9, a high voltage is applied between the source and the drain to cause a minute leak current to flow to form a uniform potential distribution on the high-resistance polysilicon resistor 709. This uniform potential distribution is reflected on the n-well region through the thermal oxide film 8, and the potential distribution formed on the n-well region 4 and the p-substrate 1 is also uniform.
In this way, the above problem can be avoided.
【０００８】[0008]
【発明が解決しようとする課題】しかし、実用化に当た
っては、リーク電流の少ない高抵抗ポリシリコン抵抗体
７０９を形成することはむずかしく、特に１２５℃の高
温で、この高抵抗ポリシリコン抵抗体が熱暴走領域に入
ってしまう。また、図１５に示すようにモールド樹脂７
２０の界面に可動イオン（ここではマイナスイオンで示
す）が存在する時、高抵抗ポリシリコン抵抗体７０９の
表面が容易に電荷（ここではプラスイオンで示す）を蓄
積し、部分的に抵抗値が低下し、電位分布の不均一を生
じ、電界緩和効果を失い高耐圧半導体装置の耐圧低下を
招く。本発明の目的は、前記の課題を解決して、耐圧低
下および耐圧の経時変化を防止できる高耐圧半導体装置
を提供することにある。However, in practical use, it is difficult to form a high-resistance polysilicon resistor 709 having a small leakage current. You will enter the runaway area. Also, as shown in FIG.
When mobile ions (indicated by negative ions) are present at the interface of 20, the surface of the high-resistance polysilicon resistor 709 easily accumulates charges (indicated by positive ions in this case), and the resistance value partially increases. As a result, the potential distribution becomes non-uniform, the effect of relaxing the electric field is lost, and the breakdown voltage of the high breakdown voltage semiconductor device is reduced. An object of the present invention is to solve the above problems and to provide a high withstand voltage semiconductor device capable of preventing a decrease in withstand voltage and a change in withstand voltage with time.
【０００９】[0009]
【課題を解決するための手段】前記の目的を達成するた
めに、半導体基板の表面層に低電位側の第１領域と、高
電位側の第２領域を有し、第１領域と第２領域との間で
電位の遷移を行う高耐圧半導体装置において、第１領域
と第２領域に挟まれた半導体基板の主面上に絶縁膜を介
してｎ型抵抗性膜を形成し、第１領域側の該ｎ型抵抗性
膜の端部と第１領域が電気的に接続し、第２領域側の該
ｎ型抵抗性膜の端部と第２領域が電気的に接続し、該ｎ
型抵抗性膜上に絶縁膜を介して形成され、第１領域側の
ｎ型抵抗性膜の端部と電気的に接続する第１導電膜を有
する構成とする。In order to achieve the above object, a semiconductor substrate has a first region on a low potential side and a second region on a high potential side in a surface layer of the semiconductor substrate. In a high-breakdown-voltage semiconductor device which performs potential transition between a first region and a second region, an n-type resistive film is formed on a main surface of a semiconductor substrate sandwiched between a first region and a second region with an insulating film interposed therebetween. The end of the n-type resistive film on the region side is electrically connected to the first region, and the end of the n-type resistive film on the second region is electrically connected to the second region.
A first conductive film formed on the type-resistive film via an insulating film and electrically connected to an end of the n-type resistive film on the first region side;
【００１０】第１領域と第２領域に挟まれた半導体基板
の表面層に絶縁膜を介してｐ型抵抗性膜を形成し、第１
領域側の該ｐ型抵抗性膜の端部と第１領域が電気的に接
続し、第２領域側の該ｐ型抵抗性膜の端部と第２領域が
電気的に接続し、該ｐ型抵抗性膜上に絶縁膜を介して形
成され、第２領域側のｐ型抵抗性膜の端部と電気的に接
続する第２導電膜を有する構成とする。[0010] A p-type resistive film is formed on a surface layer of the semiconductor substrate sandwiched between the first region and the second region via an insulating film.
The end of the p-type resistive film on the region side is electrically connected to the first region, and the end of the p-type resistive film on the second region is electrically connected to the second region. A second conductive film formed on the resistive film via an insulating film and electrically connected to an end of the p-type resistive film on the second region side;
【００１１】第１領域と第２領域に挟まれた半導体基板
の主面上に絶縁膜を介して第１領域側がｎ型抵抗性膜、
第２領域側がｐ型抵抗性膜となるｐｎ接合を有する抵抗
性膜を形成し、ｎ型抵抗性膜の第１領域側の端部と第１
領域が電気的に接続し、ｐ型抵抗性膜の第２領域側の端
部と第４領域が電気的に接続し、前記抵抗性膜上に絶縁
膜を介して形成され、第１領域側のｎ型抵抗性膜の端部
と電気的に接続する第３導電膜と、第２領域側のｐ型抵
抗性膜の端部と電気的に接続する第４導電膜を有する構
成とする。An n-type resistive film on the first region side with an insulating film interposed therebetween on a main surface of the semiconductor substrate sandwiched between the first region and the second region;
Forming a resistive film having a pn junction on the second region side as a p-type resistive film, and forming an end of the n-type resistive film on the first region side with the first region;
The region is electrically connected, the end of the p-type resistive film on the second region side is electrically connected to the fourth region, and is formed on the resistive film via an insulating film, and And a fourth conductive film electrically connected to the end of the p-type resistive film on the second region side.
【００１２】第１領域と第２領域に挟まれた半導体基板
の主面上に絶縁膜を介して両端にｎ型領域を有するｐ型
抵抗性膜を形成し、第１領域側のｎ型領域と第１領域が
電気的に接続し、第２領域側のｎ型領域と第２領域が電
気的に接続し、前記ｐ型抵抗性膜上に絶縁膜を介して形
成され第１領域側のｎ型領域と電気的に接続する第５導
電膜を有する構成とする。A p-type resistive film having n-type regions at both ends is formed on a main surface of a semiconductor substrate sandwiched between a first region and a second region via an insulating film, and an n-type region on the first region side is formed. And the first region are electrically connected to each other, the n-type region and the second region on the second region side are electrically connected to each other, and are formed on the p-type resistive film via an insulating film via the first region side. A structure including a fifth conductive film electrically connected to the n-type region is employed.
【００１３】第１領域と第２領域に挟まれた半導体基板
の主面上に絶縁膜を介して両端にｐ型領域を有するｎ型
抵抗性膜を形成し、第１領域側のｐ型領域と第１領域が
電気的に接続し、第２領域側のｐ型領域と第２領域が電
気的に接続し、前記ｎ型抵抗性膜上に絶縁膜を介して形
成され第２領域側のｐ型領域と電気的に接続する第６導
電膜を有する構成とする。An n-type resistive film having p-type regions at both ends is formed on the main surface of the semiconductor substrate sandwiched between the first region and the second region via an insulating film, and the p-type region on the first region side is formed. And the first region are electrically connected, the p-type region on the second region side and the second region are electrically connected, and formed on the n-type resistive film via an insulating film via the second region side. A structure including a sixth conductive film electrically connected to the p-type region is employed.
【００１４】第１領域と第２領域に挟まれた半導体基板
の主面上に絶縁膜を介して第１領域側がｎ型抵抗性膜、
第２領域側がｐ型抵抗性膜となるｐｎ接合を有する抵抗
性膜を形成し、第１領域側のｐ型抵抗性膜の両端にｎ型
領域を形成し、第２領域側のｎ型抵抗性膜の両端にｐ型
領域を形成し、第１領域側のｎ型領域と第１領域が電気
的に接続し、第２領域側のｐ型領域と第２領域が電気的
に接続し、前記抵抗性膜膜上に絶縁膜を介して形成さ
れ、第１領域側のｎ型領域と電気的に接続する第７導電
膜と、第２領域側のｐ型領域と電気的に接続する第８導
電膜を有する構成とする。An n-type resistive film on the first region side with an insulating film interposed therebetween on a main surface of the semiconductor substrate sandwiched between the first region and the second region;
Forming a resistive film having a pn junction on the second region side as a p-type resistive film; forming n-type regions at both ends of the p-type resistive film on the first region side; Forming a p-type region at both ends of the conductive film, the n-type region on the first region side and the first region are electrically connected, the p-type region on the second region side and the second region are electrically connected, A seventh conductive film formed on the resistive film via an insulating film and electrically connected to the n-type region on the first region side, and a seventh conductive film electrically connected to the p-type region on the second region side It is configured to have eight conductive films.
【００１５】第１領域と第２領域に挟まれた半導体基板
の主面上に絶縁膜を介して両端にｎ型領域を有するｐ型
抵抗性膜を形成し、該ｐ型抵抗性膜の第１領域側のｎ型
領域と接する、ｐ型抵抗性膜より不純物濃度が高い高濃
度ｐ型領域をｐ型抵抗性膜に形成し、第１領域側のｎ型
領域と第１領域が電気的に接続し、第２領域側のｎ型領
域と第２領域が電気的に接続し、前記ｐ型抵抗性膜上に
絶縁膜を介して形成され、第１領域側のｎ型領域と電気
的に接続する第９導電膜を形成することを特徴とする高
耐圧半導体装置。A p-type resistive film having n-type regions at both ends is formed on the main surface of the semiconductor substrate interposed between the first region and the second region with an insulating film interposed therebetween. A high-concentration p-type region having a higher impurity concentration than the p-type resistive film in contact with the n-type region on the first region side is formed in the p-type resistive film, and the n-type region and the first region on the first region side are electrically connected. And the n-type region on the second region side and the second region are electrically connected, formed on the p-type resistive film via an insulating film, and electrically connected to the n-type region on the first region side. Forming a ninth conductive film connected to the semiconductor device.
【００１６】第１領域と第２領域に挟まれた半導体基板
の主面上に絶縁膜を介して両端にｐ型領域を有するｎ型
抵抗性膜を形成し、第２領域側のｐ型領域に接するｎ型
抵抗性膜より不純物濃度が高い高濃度ｎ型領域をｎ型抵
抗性膜に形成し、第１領域側のｐ型領域と第１領域が電
気的に接続し、第２領域側のｐ型領域と第２領域と電気
的に接続し、前記ｎ型抵抗性膜上に絶縁膜を介して形成
され、第２領域と電気的に接続する第１０導電膜を有す
る構成とする。An n-type resistive film having p-type regions at both ends is formed on the main surface of the semiconductor substrate sandwiched between the first region and the second region via an insulating film, and the p-type region on the second region side is formed. Forming a high-concentration n-type region having an impurity concentration higher than that of the n-type resistive film in contact with the n-type resistive film, electrically connecting the p-type region on the first region side to the first region; And a tenth conductive film formed electrically on the n-type resistive film via an insulating film and electrically connected to the second region.
【００１７】第１領域と第２領域に挟まれた半導体基板
の主面上に絶縁膜を介して第１領域側がｐ型抵抗性膜、
第２領域側がｎ型抵抗性膜となるｐｎ接合を有する抵抗
性膜を形成し、第１領域側のｐ型抵抗性膜の両端にｎ型
領域を形成し、該ｎ型領域に接するｐ型抵抗性膜より不
純物濃度が高い高濃度ｐ型領域をｐ型抵抗性膜に形成
し、第２領域側のｎ型抵抗性膜の両端にｐ型領域を形成
し、該ｐ型領域と接するｎ型抵抗性膜より不純物濃度が
高い高濃度ｎ型領域をｐ型抵抗性膜に形成し、第１領域
側のｎ型領域と第１領域が電気的に接続し、第２領域側
のｐ型領域と第２領域が電気的に接続し、前記抵抗性膜
上に絶縁膜を介して形成され、第１領域と電気的に接続
する第１１導電膜と、第２領域と電気的に接続する第１
２導電膜を有する構成とする。前記抵抗性膜がポリシリ
コンからなるとよい。また、前記抵抗性膜がＳｉ+ 窒化
膜であるとよい。The first region side is a p-type resistive film on the main surface of the semiconductor substrate sandwiched between the first region and the second region via an insulating film,
Forming a resistive film having a pn junction on the second region side as an n-type resistive film; forming n-type regions at both ends of the p-type resistive film on the first region side; A high-concentration p-type region having an impurity concentration higher than that of the resistive film is formed in the p-type resistive film, and p-type regions are formed at both ends of the n-type resistive film on the second region side. A high-concentration n-type region having a higher impurity concentration than the p-type resistive film is formed in the p-type resistive film; the n-type region on the first region side is electrically connected to the first region; The region and the second region are electrically connected to each other, and an eleventh conductive film formed on the resistive film via an insulating film and electrically connected to the first region is electrically connected to the second region. First
It has a configuration having two conductive films. Preferably, the resistive film is made of polysilicon. Further, the resistive film is preferably a Si + nitride film.
【００１８】少なくとも、半導体基板の主面側の表面層
に形成されるソース領域およびドレイン領域が第１領域
および第２領域で、半導体基板上に絶縁膜を介して形成
されるゲート電極と、ソース領域上に形成されるソース
電極と、ドレイン領域上に形成されるドレイン電極とを
具備する高耐圧横型ＭＯＳＦＥＴであるとよい。At least a source region and a drain region formed in a surface layer on the main surface side of the semiconductor substrate are a first region and a second region, and a gate electrode formed on the semiconductor substrate via an insulating film; A high breakdown voltage lateral MOSFET having a source electrode formed on the region and a drain electrode formed on the drain region is preferable.
【００１９】前記のように、導電膜をゲートとしたＪＦ
ＥＴあるいはＭＯＳＦＥＴをポリシリコンもしくは窒化
膜で形成し、その素子をピンチオフあるいはサブスレッ
シュホールド動作（ゲート電圧をしきい値電圧以下のし
きい値近傍の電圧で動作させること）させ、その電位分
布でシリコン基板内部の主パワーデバイスの表面電界緩
和を行うことができる。このとき、ゲートとなるメタル
などを素子全面に形成しモールド樹脂界面の可動イオン
の寄生電荷に対し、シールド効果も期待できる。As described above, the JF using the conductive film as a gate
The ET or MOSFET is formed of polysilicon or nitride film, and the device is pinch-off or sub-threshold operation (operating the gate voltage at a voltage close to the threshold voltage below the threshold voltage), and the potential distribution of silicon The surface electric field of the main power device inside the substrate can be reduced. At this time, a metal or the like serving as a gate is formed on the entire surface of the element, and an effect of shielding parasitic charges of mobile ions at the interface of the mold resin can be expected.
【００２０】[0020]
【発明の実施の形態】以下の説明において、従来例と同
一の符号は同一の領域を示す。図１は、本発明の第１実
施例で、高耐圧半導体装置の要部断面図である。ｐ基板
１の表面層に選択的にｎ+ ソース領域２と、ｐ基板１と
のコンタクトをとるめのｐ+ 基板コンタクト領域３と、
ｎ+ ソース領域２と離してｎウエル領域４とを形成し、
ｎウエル領域４の表面層に選択的にｎ+ ドレイン領域５
を形成する。ｎ + ソース領域２とｎウエル領域４に挟ま
れたｐ基板１上にゲート酸化膜６を介してゲート電極７
を形成する。ｎ+ ソース領域２上とｎ+ ドレイン領域５
上にソース電極１２とドレイン電極１３をそれぞれ形成
する。ｎウエル領域４上に熱酸化膜８を形成し、熱酸化
膜８上にｎポリシリコンフィールドプレート９ａを形成
する。このｎポリシリコンフィールドプレート９ａの両
端部に第１ｎ+ 領域１０と第２ｎ+ 領域１１を形成し、
第１ｎ+ 領域１０上と第２ｎ+ 領域１１上に第１接続導
体１４と第２接続導体１５をそれぞれ形成する。また、
ｎポリシリコンフィールドプレート９ａ上に層間絶縁膜
１６を挟んで第１導電膜１７を形成し、この第１導電膜
１７はソース電極１２と第１接続導体１０とにそれぞれ
接続する。この第１導電膜１７とソース電極１２は同一
材質で同時に形成してもよい。また、ドレイン電極１３
と第２接続導体１５は第２導電膜１８で接続する。第１
導電膜１７上および第２導電膜１８上および層間絶縁膜
１６が露出してる箇所の上にパッシベーション膜１９を
被覆し、さらに、その上をモールド樹脂２０で被覆す
る。尚、前記の第１導電膜１７、第２導電膜１８、ソー
ス電極１２およびドレイン電極１３を同一材料で同時に
形成してもよい。DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, the same as the conventional example will be described.
One symbol indicates the same area. FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a cross-sectional view of a main part of a high breakdown voltage semiconductor device in an example. p substrate
1 selectively on the surface layer+Source region 2, p substrate 1
The contact p+A substrate contact region 3;
n+Forming an n-well region 4 apart from the source region 2;
The surface layer of n well region 4 is selectively n+Drain region 5
To form n +Sandwiched between source region 2 and n-well region 4
A gate electrode 7 on a p-type substrate 1 with a gate oxide film 6 interposed therebetween.
To form n+On the source region 2 and n+Drain region 5
A source electrode 12 and a drain electrode 13 are respectively formed thereon.
I do. A thermal oxide film 8 is formed on the n-well region 4,
Forming n polysilicon field plate 9a on film 8
I do. Both sides of this n polysilicon field plate 9a
1n at the end+Region 10 and 2n+Forming an area 11;
1n+On the region 10 and the second n+A first connection conductor on the area 11
The body 14 and the second connection conductor 15 are respectively formed. Also,
Interlayer insulating film on n polysilicon field plate 9a
A first conductive film 17 is formed with the first conductive film 17 interposed therebetween.
Reference numeral 17 denotes the source electrode 12 and the first connection conductor 10, respectively.
Connecting. The first conductive film 17 and the source electrode 12 are the same.
The material may be formed simultaneously. Also, the drain electrode 13
And the second connection conductor 15 are connected by the second conductive film 18. First
On conductive film 17, on second conductive film 18, and interlayer insulating film
A passivation film 19 is formed on the portion where 16 is exposed.
And then overlaid with a mold resin 20.
You. The first conductive film 17, the second conductive film 18, and the saw
Electrode 12 and drain electrode 13 are simultaneously made of the same material.
It may be formed.
【００２１】ここで、各箇所について説明する。ｐ基板
は１５０Ω・ｃｍ程度の高抵抗のｎ型半導体基板、熱酸
化膜の膜厚は約０．６μｍ、ｎポリシリコンフィールド
プレートの厚さは約０．５μｍ、不純物原子はリンなど
で濃度は１×１０14ｃｍ-3〜１×１０16ｃｍ-3程度、ゲ
ート電極はポリシリコンで形成され、厚みは０．５μ
ｍ、不純物濃度はリンなどで濃度は１×１０20ｃｍ-3程
度である。また、第１および第２ｎ+ 領域の不純物濃度
は１×１０20ｃｍ-3程度、層間絶縁膜の膜厚は２μｍ程
度、ｐ+ 基板コンタクト領域の不純物濃度は１×１０19
ｃｍ-3程度である。Here, each part will be described. The p-substrate is an n-type semiconductor substrate having a high resistance of about 150 Ω · cm, the thickness of the thermal oxide film is about 0.6 μm, the thickness of the n-polysilicon field plate is about 0.5 μm, and the concentration of impurity atoms is phosphorus or the like. About 1 × 10 14 cm −3 to 1 × 10 16 cm −3 , the gate electrode is formed of polysilicon, and has a thickness of 0.5 μm.
m, the impurity concentration is about 1 × 10 20 cm −3 in phosphorus or the like. The impurity concentration of the first and second n + regions is about 1 × 10 20 cm −3 , the thickness of the interlayer insulating film is about 2 μm, and the impurity concentration of the p + substrate contact region is 1 × 10 19
cm -3 .
【００２２】図２は、図１の高耐圧半導体装置に電圧を
印加した状態を示す図である。ソース電極１２をグラン
ドとしてドレイン電極１３に高電圧を印加すした状態の
図である。第１導電膜１７と層間絶縁膜１６およびｎポ
リシリコンフィールドプレート９ａでコンデンサを構成
するために、ｎポリシリコンフィールドプレート９ａの
第１導電膜１７に対向する側に、プラス電荷が誘起され
て、ピンチオフ領域５２が形成される。このピンチオフ
領域５２はｎポリシリコンフィールドプレート９ａに形
成された空乏層である。FIG. 2 is a diagram showing a state in which a voltage is applied to the high breakdown voltage semiconductor device of FIG. FIG. 3 is a diagram illustrating a state where a high voltage is applied to a drain electrode 13 with a source electrode 12 serving as a ground. Since a capacitor is constituted by the first conductive film 17, the interlayer insulating film 16 and the n-polysilicon field plate 9a, a positive charge is induced on the side of the n-polysilicon field plate 9a facing the first conductive film 17, A pinch-off region 52 is formed. This pinch-off region 52 is a depletion layer formed in n polysilicon field plate 9a.
【００２３】このように、ピンチオフ領域５２が形成さ
れると、ｎポリシリコンフィールドプレート９ａ内に一
定の微小な電流がｎ+ ドレイン領域５からｎ+ ソース領
域２に流れる。丁度、ｎポリシリコンフィールドプレー
ト９ａがｎ型のＪＦＥＴの高抵抗層に相当する。[0023] Thus, when the pinch-off region 52 is formed, n polysilicon field plate constant minute current in 9a flows from n + drain region 5 to the n + source region 2. Just the n-polysilicon field plate 9a corresponds to the high-resistance layer of the n-type JFET.
【００２４】ｎポリシリコンフィールドプレート９ａの
不純物濃度が低いため、ソース電極１２からドレイン電
極１３側に張り出した第１導電膜１７がＪＦＥＴのゲー
ト電極のような働きして、前記したように、ｎポリシリ
コンフィールドプレート９ａの第１導電膜１７に対向す
る側に、容易にプラス電荷が誘起されて、ピンチオフ領
域５２が形成される。その結果、ドレイン電極１３に７
００Ｖ程度の電圧が印加されると、ｎポリシリコンフィ
ールドプレート９ａに数ｎＡのピンチオフ微少電流が流
れて、図中の点線で示した等電位線５１の間隔がほぼ同
じになり、比較的均一な電位（電位分布が均一であるこ
と）がｎポリシリコンフィールドプレート内部に生ずる
ことになる。この効果は、以下の実施例でも全く同様で
ある。Since the impurity concentration of the n-polysilicon field plate 9a is low, the first conductive film 17 projecting from the source electrode 12 to the drain electrode 13 acts as a gate electrode of the JFET, and as described above, Positive charges are easily induced on the side of the polysilicon field plate 9a facing the first conductive film 17, and the pinch-off region 52 is formed. As a result, 7
When a voltage of about 00 V is applied, a pinch-off minute current of several nA flows through the n-polysilicon field plate 9a, so that the intervals between the equipotential lines 51 indicated by dotted lines in the drawing become substantially the same, and the gap becomes relatively uniform. A potential (uniform potential distribution) will be generated inside the n-polysilicon field plate. This effect is completely the same in the following embodiments.
【００２５】これにより、ｐ基板１に形成された主デバ
イスであるパワーＭＯＳＦＥＴ（高耐圧半導体装置）の
表面の電界緩和がなされ、高耐圧化できる。また、ソー
ス電極１２と一体となっている第１導電膜１７がＪＦＥ
Ｔの働きをするｎポリシリコンフィールドプレート９ａ
上をほぼ全面的に覆うため、モールド樹脂２０との界面
近傍の可動電荷の影響を遮蔽でき、パワーＭＯＳＦＥＴ
の耐圧変動を無くすことができる。As a result, the electric field on the surface of the power MOSFET (high breakdown voltage semiconductor device), which is the main device formed on the p substrate 1, is relaxed, and the breakdown voltage can be increased. Further, the first conductive film 17 integrated with the source electrode 12 is made of JFE.
N polysilicon field plate 9a acting as T
Since the upper surface is almost entirely covered, the influence of movable charges near the interface with the mold resin 20 can be shielded.
Can be eliminated.
【００２６】図３は、本発明の第２実施例で、高耐圧半
導体装置の要部断面図である。第１実施例との違いは、
ｐポリシリコンフィールドプレート９ｂにして、ドレイ
ン電極１３と第２接続導体１５を第２導電膜２８で接続
し、この第２導電膜２８がｐポリシリコンフィールドプ
レート９ｂ上を層間絶縁膜１６を介して被覆している点
である。このｐポリシリコンフィールドプレート９ｂが
ｐ型のＪＦＥＴの高抵抗層に相当している。また、ピン
チオフ動作を効果的に行わせるために（ピンチオフ領域
５２を効果的に形成するために）、ドレイン電極１３と
接続している第２導電膜２８がソース近傍まで張り出し
ている。ｐポリシリコンフィールドプレート９ｂの場合
は、荷電粒子は正孔であり、この正孔の移動度は電子よ
り小さいため、第１実施例よりピンチオフ電流（ピンチ
オフしたときに流れる電流）を低減できる。尚、ｐポリ
シリコンフィールドプレート９ｂの両端部には、コンタ
クトをとるために、第１ｐ+ 領域１０ｂと第２ｐ+ 領域
１１ｂが形成され、また、ソース電極１２と第１ｐ+ 領
域１０ｂを第１導電膜２７で接続する。前記の第１導電
膜２７、第２導電膜２８、ソース電極１２およびドレイ
ン電極１３を同一材料で同時に形成してもよい。FIG. 3 is a sectional view of a main part of a high voltage semiconductor device according to a second embodiment of the present invention. The difference from the first embodiment is
The drain electrode 13 and the second connection conductor 15 are connected by a second conductive film 28 in the p-polysilicon field plate 9b, and the second conductive film 28 is formed on the p-polysilicon field plate 9b via the interlayer insulating film 16. This is the point of coating. The p-polysilicon field plate 9b corresponds to a high-resistance layer of a p-type JFET. In addition, in order to perform the pinch-off operation effectively (to effectively form the pinch-off region 52), the second conductive film 28 connected to the drain electrode 13 extends to the vicinity of the source. In the case of the p-polysilicon field plate 9b, the charged particles are holes, and since the mobility of the holes is smaller than that of the electrons, the pinch-off current (the current flowing when pinching off) can be reduced as compared with the first embodiment. A first p + region 10b and a second p + region 11b are formed at both ends of the p polysilicon field plate 9b for making contact, and the source electrode 12 and the first p + region 10b are connected to the first conductive region. The connection is made with the film 27. The first conductive film 27, the second conductive film 28, the source electrode 12 and the drain electrode 13 may be simultaneously formed of the same material.
【００２７】図４は、本発明の第３実施例で、高耐圧半
導体装置の要部断面図である。ポリシリコンフィールド
プレート９のソース電極１２側にｎポリシリコン領域９
ｃ、ドレイン電極１３側にｐポリシリコン領域９ｄを形
成するため、中央にｐｎ接合３０によるダイオードが存
在する。前記したように、ｎポリシリコン領域９ｃがｎ
型のＪＦＥＴの高抵抗層となり、ｐポリシリコン領域９
ｄがｐ型のＪＦＥＴの高抵抗層となる。ソース電極１２
およびドレイン電極１３から張り出した電極（第１導電
膜３７および第２導電膜３８）により、各ＪＦＥＴの高
抵抗層に相当するｎポリシリコン領域９ｃおよびｐポリ
シリコン領域９ｄはピンチオフになる。そのピンチオフ
した領域がピンチオフ領域５２である。FIG. 4 is a sectional view of a main part of a high breakdown voltage semiconductor device according to a third embodiment of the present invention. An n-polysilicon region 9 is provided on the source electrode 12 side of the polysilicon field plate 9.
(c) Since a p-polysilicon region 9d is formed on the drain electrode 13 side, a diode with a pn junction 30 exists at the center. As described above, the n polysilicon region 9c is
High-resistance layer of the p-type JFET
d becomes the high resistance layer of the p-type JFET. Source electrode 12
The electrodes (the first conductive film 37 and the second conductive film 38) projecting from the drain electrode 13 pinch off the n polysilicon region 9c and the p polysilicon region 9d corresponding to the high resistance layer of each JFET. The pinch-off area is the pinch-off area 52.
【００２８】第１実施例では張り出した第１導電膜１７
とｎポリシリコンフィールドプレート９ａの間には最大
で、主素子（パワーＭＯＳＦＥＴ）の定格電圧である７
００Ｖが印加されるが、本実施例では、ｐｎ接合３０の
箇所で全印加電圧を２分割するため、ｎポリシリコン領
域３７とｐポリシリコン領域３８に印加される電圧は、
約３５０Ｖ程度であり、第１実施例の約半分となる。そ
のため、第１導電膜３７および第２導電膜３８とポリシ
リコンフィールドプレート９に挟まれた層間絶縁膜１６
の電界が緩和されて、層間絶縁膜１６の信頼性が向上す
る。尚、コンタクトをとるために、ｎポリシリコン領域
９ｃのソース電極１２側にｎ+ 領域１０ｃが形成され、
ｐポリシリコン領域９ｄのドレイン電極１３側にｐ+ 領
域１１ｃが形成される。In the first embodiment, the overhanging first conductive film 17
And the maximum voltage between the n polysilicon field plate 9a and the rated voltage of the main element (power MOSFET).
Although 00V is applied, in the present embodiment, since the total applied voltage is divided into two at the pn junction 30, the voltage applied to the n polysilicon region 37 and the p polysilicon region 38 is
It is about 350 V, which is about half of the first embodiment. Therefore, the interlayer insulating film 16 sandwiched between the first conductive film 37 and the second conductive film 38 and the polysilicon field plate 9 is formed.
And the reliability of the interlayer insulating film 16 is improved. In order to make a contact, an n + region 10c is formed on the side of the source electrode 12 in the n polysilicon region 9c.
Ap + region 11c is formed on drain electrode 13 side of p polysilicon region 9d.
【００２９】図５は、本発明の第４実施例で、高耐圧半
導体装置の要部断面図である。ここではｐポリシリコン
フィールドプレート１０９の両側に第１ｎ+ 領域１１０
と第２ｎ+ 領域１１１を形成する。第１ｎ+ 領域１１０
と第２ｎ+ 領域１１１に挟まれたｐポリシリコンフィー
ルドプレート１０９がｐポリシリコン領域１０９ａであ
る。このｐポリシリコン領域１０９ａと第１ｎ+ 領域１
１０と第２ｎ+ 領域１１１および第１導電膜１７で、ｎ
型ＭＯＳＦＥＴを構成し、第１ｎ+ 領域１１０と第２ｎ
+ 領域１１１が、このｎ型ＭＯＳＦＥＴのソース領域お
よびドレイン領域に相当する。尚、この第１ｎ+ 領域１
１０上と第２ｎ+ 領域１１１上に第１接続導体１４と第
２接続導体をそれぞれ形成し、ソース電極１２と第１接
続導体１４を第１導電膜１７で接続し、この第１導電膜
１７でｐポリシリコン領域１０９を層間絶縁膜１６を介
して被覆する。また、第２接続導体１５とドレイン電極
１３を第２導電膜１８で接続する。FIG. 5 is a sectional view of a main part of a high breakdown voltage semiconductor device according to a fourth embodiment of the present invention. Here, the first n + region 110 is formed on both sides of the p polysilicon field plate 109.
And a second n + region 111 are formed. 1n + region 110
The p-polysilicon field plate 109 sandwiched between the first n-type region 111 and the second n + region 111 is a p-polysilicon region 109a. The p polysilicon region 109a and the first n + region 1
10 and the second n + region 111 and the first conductive film 17, n
The first n + region 110 and the second n +
+ Region 111 corresponds to the source region and the drain region of this n-type MOSFET. The first n + region 1
A first connection conductor 14 and a second connection conductor are respectively formed on the first and second n + regions 111, and the source electrode 12 and the first connection conductor 14 are connected by a first conductive film 17. To cover p polysilicon region 109 with interlayer insulating film 16 interposed therebetween. Further, the second connection conductor 15 and the drain electrode 13 are connected by the second conductive film 18.
【００３０】このｎ型ＭＯＳＦＥＴのゲート電極に相当
する第１導電膜１７はソース電極２３から張り出した第
１導電膜１７である。また、ｎ型ＭＯＳＦＥＴのソース
領域である第１ｎ+ 領域１１０とｎ型ＭＯＳＦＥＴのゲ
ート電極に相当する第１導電膜１７が同一電位を有する
バイアス条件となっている。The first conductive film 17 corresponding to the gate electrode of the n-type MOSFET is the first conductive film 17 projecting from the source electrode 23. In addition, the first n + region 110, which is the source region of the n-type MOSFET, and the first conductive film 17, which corresponds to the gate electrode of the n-type MOSFET, have the same bias condition.
【００３１】ｐ型のチャネル領域（第１ｎ+ 領域１１０
と第２ｎ+ 領域１１１に挟まれたｐポリシリ領域１０９
ａ）の不純物濃度を１×１０15ｃｍ-3程度することで、
サブスレッシュホールド電流を流し、ｐポリシリコン領
域１０９ａの内部に比較的均一な電位分布を形成するこ
とで、ｐ基板１に形成された主素子であるパワーＭＯＳ
ＦＥＴの表面電界緩和を行い耐圧を高めている。また、
ソース電極１２と接続する第１導電膜１７がｐポリシリ
コン領域１０９ａ上をほぼ全面的に覆うため、モールド
樹脂２０の界面の可動電荷の影響を遮蔽でき、パワーＭ
ＯＳＦＥＴの耐圧変動を無くすことができる。A p-type channel region (first n + region 110
Polysilicon region 109 sandwiched between the second n + region 111 and
By making the impurity concentration of a) about 1 × 10 15 cm −3 ,
By passing a sub-threshold current and forming a relatively uniform potential distribution inside p polysilicon region 109a, power MOS which is a main element formed on p substrate 1 is formed.
The withstand voltage is increased by relaxing the surface electric field of the FET. Also,
Since the first conductive film 17 connected to the source electrode 12 covers almost the entire surface of the p-polysilicon region 109a, the influence of the movable charge at the interface of the mold resin 20 can be shielded, and the power M
Variations in the breakdown voltage of the OSFET can be eliminated.
【００３２】図６は、本発明の第５実施例で、高耐圧半
導体装置の要部断面図である。ここではｎポリシリコン
フィールドプレート２０９の両側に第１ｐ+ 領域２１０
ｂと第２ｐ+ 領域２１１ｂを形成する。この第１ｐ+ 領
域２１０ｂと第２ｐ+ 領域２１１ｂに挟まれたｎポリシ
リコンフィールドプレートがｎポリシリコン領域２０９
ａである。このｎポリシリコン領域１０９ａと第１ｐ+
領域２１０ｂと第２ｐ + 領域２１１ｂおよび第２導電膜
２８でｐ型ＭＯＳＦＥＴを構成し、第１ｐ+ 領域１１０
ｂと第２ｐ+ 領域１１１ｂが、このｐ型ＭＯＳＦＥＴの
ドレイン領域、ソース領域に相当する。このｐ型ＭＯＳ
ＦＥＴのゲート電極は、ソース領域である第２ｐ+ 領域
２１１ｂから張り出した第２導電膜２８である。またｐ
型ＭＯＳＦＥＴのソース領域である第２ｐ+ 領域２１１
ｂとゲート電極である第２導電膜２８が同一電位を有す
るバイアス条件となっている。FIG. 6 shows a fifth embodiment of the present invention, in which
It is principal part sectional drawing of a conductor apparatus. Here, n polysilicon
First p on both sides of field plate 209+Region 210
b and the second p+The region 211b is formed. This first p+Territory
Area 210b and second p+N policy sandwiched between regions 211b
Recon field plate is n polysilicon region 209
a. The n polysilicon region 109a and the first p+
The region 210b and the second p +Region 211b and second conductive film
28 constitute a p-type MOSFET,+Region 110
b and the second p+The region 111b corresponds to the p-type MOSFET.
They correspond to a drain region and a source region. This p-type MOS
The gate electrode of the FET is the second p+region
The second conductive film 28 overhangs from 211b. Also p
P, which is the source region of the p-type MOSFET+Area 211
b and the second conductive film 28 as the gate electrode have the same potential
Bias condition.
【００３３】ｎ型のチャネル領域（第１ｐ+ 領域２１０
ｂと第２ｐ+ 領域２１１ｂに挟まれたｎポリシリコン領
域２０９ａ）の不純物濃度を１×１０15ｃｍ-3程度する
ことで、サブスレッシュホールド電流を流し、ｎポリシ
リコン領域２０９ａの内部に比較的均一な電位分布が形
成されることで、ｐ基板１に形成されたパワーＭＯＳの
表面電界緩和を行い耐圧を高めている。また、ソース電
極と接続する第２導電膜２８がｎポリシリコン領域２０
９ａをほぼ全面的に覆うため、モールド樹脂２０の界面
の可動電荷の影響を遮蔽でき、パワーＭＯＳＦＥＴの耐
圧変動を無くすことができる。An n-type channel region (first p + region 210
By setting the impurity concentration of n polysilicon region 209a) sandwiched between b and second p + region 211b to about 1 × 10 15 cm −3 , a sub-threshold current is caused to flow into n polysilicon region 209a relatively. By forming a uniform potential distribution, the surface electric field of the power MOS formed on the p-substrate 1 is alleviated to increase the breakdown voltage. Further, the second conductive film 28 connected to the source electrode is formed in the n polysilicon region 20.
9a can be covered almost entirely, so that the influence of the movable charge at the interface of the mold resin 20 can be shielded, and the withstand voltage fluctuation of the power MOSFET can be eliminated.
【００３４】図７は、本発明の第６実施例で、高耐圧半
導体装置の要部断面図である。ポリシリコンフィールド
プレート３０９のソース電極１２側にｐポリシリコン領
域３０９ｃ、ドレイン電極１３側のｎポリシリコン領域
３０９ｄが形成される。ｐポリシリコン領域３０９ｃに
ｎ+ ソース領域となる第１ｎ+ 領域３１０ｃ、ｎ+ ドレ
イン領域となる第２ｎ+ 領域３１０ｄおよびｎポリシリ
コン領域３０９ｄにｐ + ドレイン領域となる第１ｐ+ 領
域３１１ｄ、ｐ+ ソース領域となる第２ｐ+ 領域３１１
ｃが各々形成される。これらの領域と、層間絶縁膜１６
を介してポリシリコンフィールドプレート３０９上に形
成されるゲート電極となる第１導電膜３７と第２導電膜
３８とでｎ型ＭＯＳＦＥＴとｐ型ＭＯＳＦＥＴを構成す
る。FIG. 7 shows a sixth embodiment of the present invention, in which
It is principal part sectional drawing of a conductor apparatus. Polysilicon field
A p-polysilicon region is formed on the source electrode 12 side of the plate 309.
Region 309c, n-polysilicon region on drain electrode 13 side
309d is formed. In the p polysilicon region 309c
n+1n as a source region+Region 310c, n+Dre
2n to be the in region+Region 310d and n polysilicon
P in the con area 309d +First p to be drain region+Territory
Area 311d, p+2nd source region+Area 311
c are each formed. These regions and the interlayer insulating film 16
Through the polysilicon field plate 309
First conductive film 37 and second conductive film to be formed gate electrodes
38 together form an n-type MOSFET and a p-type MOSFET.
You.
【００３５】また、ｎ+ ドレイン領域となる第２ｎ+ 領
域３１０ｄとｐ+ ドレイン領域となる第２ｐ+ 領域３１
１ｄは隣接して配置されている。ゲート電極に相当する
第１導電膜３７と第２導電膜３８は、ポリシリコンフィ
ールドプレート３０９の中央まで張り出されており、ｎ
型ＭＯＳＦＥＴおよびｐ型ＭＯＳＦＥＴのソース電極で
ある第１接続導体１４および第２接続導体１５と、ゲー
ト電極である第１導電膜３７および第２導電膜３８は接
続されており、同一電位を有するバイアス条件となって
いる。Further, the 2p the first 2n + region 310d and the p + drain region made of an n + drain region + region 31
1d are arranged adjacently. The first conductive film 37 and the second conductive film 38 corresponding to the gate electrode extend to the center of the polysilicon field plate 309, and n
The first and second connection conductors 14 and 15 that are the source electrodes of the p-type MOSFET and the p-type MOSFET are connected to the first conductive film 37 and the second conductive film 38 that are the gate electrodes, and have the same potential. It is a condition.
【００３６】また、チャネル領域となるｐポリシリコン
領域３０９ｃおよびｎポリシリコン領域３０９ｄの高抵
抗領域３１０ｅ、３１１ｅの不純物濃度をそれぞれ１×
１０ 15ｃｍ-3程度することで、サブスレッシュホールド
電流を流し、中央の第２ｎ+領域３１０ｄ、第２ｐ+ 領
域３１１ｄの各ドレイン領域で電子と正孔が再結合す
る。ｐポリシリコン領域３０９ｃおよびｎポリシリコン
３０９ｄのそれぞれの内部に比較的均一な電位分布が形
成されることで、ｐ基板に形成された主素子であるパワ
ーＭＯＳＦＥＴの表面電界緩和を行い耐圧を高めてい
る。また、それぞれのソース電極である第１接続導体１
４と第２接続導体１５と接続する第１導電膜３７と第２
導電膜３８がｐポリシリコン領域３０９ｃとｎポリシリ
コン領域３０９ｄの高抵抗領域ををほぼ全面的に覆うた
め、モールド樹脂２０の界面の可動電荷の影響を遮蔽で
き、パワーＭＯＳＦＥＴの耐圧変動を無くすことができ
る。In addition, p-polysilicon serving as a channel region
Region 309c and n polysilicon region 309d
The impurity concentration of each of the anti regions 310e and 311e is set to 1 ×
10 Fifteencm-3Sub-threshold
Pass the current and the second n+Region 310d, second p+Territory
The electrons and holes are recombined in each drain region of the region 311d.
You. p polysilicon region 309c and n polysilicon
A relatively uniform potential distribution is formed inside each of the 309d.
By this, the power, which is the main element formed on the p-substrate, is
ー Reducing the surface electric field of the MOSFET to increase the breakdown voltage
You. In addition, the first connection conductor 1 serving as each source electrode
4 and the first conductive film 37 connected to the second connection conductor 15 and the second conductive film 37.
The conductive film 38 is formed between the p polysilicon region 309c and the n polysilicon region.
The high resistance region of the contact region 309d is almost entirely covered.
The effect of the movable charge at the interface of the mold resin 20 is shielded.
Power voltage fluctuation of the power MOSFET can be eliminated.
You.
【００３７】図８は、本発明の第７実施例で、高耐圧半
導体装置の要部断面図である。第４実施例との違いは、
ｐポリシリコンフィールドプレート１０９のｎ+ ソース
領域である第１ｎ+ 領域１１０に接してｐベース領域１
０９ｂを追加形成し、ｎ型ＤＭＯＳＦＥＴのような構造
とした点である。このｎ型ＤＭＯＳＦＥＴのゲート電極
は、パワーＭＯＳＦＥＴのソース電極１２接続して張り
出した第１導電膜１４を用いておりソース電極である第
１接続導体１４とゲート電極である第１導電膜１７が同
一電位を有するバイアス条件となっている。FIG. 8 is a sectional view of a main part of a high voltage semiconductor device according to a seventh embodiment of the present invention. The difference from the fourth embodiment is that
The p base region 1 is in contact with the first n + region 110 which is the n + source region of the p polysilicon field plate 109.
09b is additionally formed to have a structure like an n-type DMOSFET. The gate electrode of this n-type DMOSFET uses a first conductive film 14 which is connected to and protrudes from the source electrode 12 of the power MOSFET, and the first connection conductor 14 as the source electrode and the first conductive film 17 as the gate electrode are the same. The bias condition has a potential.
【００３８】ｐポリシリコン領域１０９ａの不純物濃度
を１×１０15ｃｍ-3程度、ｐベース領域１０９ｂの表面
濃度を１×１０16ｍ-3程度とすることで、サブスレッシ
ュ電流を流すとともにｐベースでパンチスルーブレイク
ダウンを防止している。ｐポリシリコン領域１０９ａの
内部に比較的均一な電位分布が形成されることで、ｐ基
板１に形成された主素子であるパワーＭＯＳＦＥＴの表
面電界緩和を行い耐圧を高めている。また、ソース電極
と接続する第１導電膜がｐポリシリコン領域１０９ａを
ほぼ全面的に覆うため、モールド樹脂２０の界面の可動
電荷の影響を遮蔽でき、パワーＭＯＳＦＥＴの耐圧変動
を無くすことができる。By setting the impurity concentration of p polysilicon region 109a to about 1 × 10 15 cm -3 and the surface concentration of p base region 109b to about 1 × 10 16 m -3 , a sub-threshold current is applied and p base Prevents punch-through breakdown. By forming a relatively uniform potential distribution inside p polysilicon region 109a, the surface electric field of the power MOSFET, which is the main element formed on p substrate 1, is relaxed to increase the breakdown voltage. In addition, since the first conductive film connected to the source electrode covers almost the entire surface of the p-polysilicon region 109a, it is possible to shield the influence of the movable charge at the interface of the mold resin 20 and to eliminate the fluctuation in the breakdown voltage of the power MOSFET.
【００３９】図９は、本発明の第８実施例で、高耐圧半
導体装置の要部断面図である。第５実施例との違いは、
ｎポリシリコンフィールドプレート２０９のｐ+ ソース
領域である第２ｐ+ 領域２１１ｂに接するｎベース領域
２０９ｂを追加形成し、ｐ型ＤＭＯＳＦＥＴの構造のよ
うにした点である。このｐ型ＤＭＯＳＦＥＴのゲート電
極はパワーＭＯＳＦＥＴのドレイン電極１３と接続し、
張り出した第２導電膜２８であり、ｐ型ＤＭＯＳＦＥＴ
のソース電極である第２接続導体１５とゲート電極であ
る第２導電膜２８が接続し、ｐ型ＤＭＯＳＦＥＴのソー
ス電極である第２接続導体１５とゲート電極である第２
導電膜２８が同一電位を有するバイアス条件となってい
る。FIG. 9 is a sectional view of an essential part of a high breakdown voltage semiconductor device according to an eighth embodiment of the present invention. The difference from the fifth embodiment is that
The point is that an n base region 209b in contact with the second p + region 211b, which is the p + source region of the n polysilicon field plate 209, is additionally formed to have a p-type DMOSFET structure. The gate electrode of this p-type DMOSFET is connected to the drain electrode 13 of the power MOSFET,
The overhanging second conductive film 28 is a p-type DMOSFET
The second connection conductor 15 which is the source electrode of the P-type DMOSFET is connected to the second conductive film 28 which is the gate electrode, and the second connection conductor 15 which is the source electrode of the p-type DMOSFET and the second conductive film 28 which is the gate electrode.
The conductive film 28 has a bias condition of having the same potential.
【００４０】ｎポリシリコン領域２０９ａの不純物濃度
を１×１０15ｃｍ-3程度、ｎベース領域２０９ａの表面
濃度を１×１０16ｍ-3程度とすることで、サブスレッシ
ュホールド電流を流すとともに、ｎベース領域２０９ａ
でパンチスルによるブレイクダウンを防止している。ｎ
ポリシリコン領域２０９ａの内部に比較的均一な電位分
布が形成されることで、ｐ基板１に形成された主素子で
あるパワーＭＯＳＦＥＴの表面電界緩和を行い耐圧を高
めている。また、ソース電極１３と接続する第２導電膜
２８がｎポリシリコン領域２０９ａをほぼ全面的に覆う
ため、モールド樹脂界面の可動電荷の影響を遮蔽でき、
パワーＭＯＳＦＥＴの耐圧変動を無くすことができる。By setting the impurity concentration of n polysilicon region 209a to about 1 × 10 15 cm −3 and the surface concentration of n base region 209a to about 1 × 10 16 m −3 , a sub-threshold current flows, n base region 209a
Prevents punch-through breakdown. n
By forming a relatively uniform potential distribution inside the polysilicon region 209a, the surface electric field of the power MOSFET, which is the main element formed on the p substrate 1, is relaxed to increase the breakdown voltage. Further, since the second conductive film 28 connected to the source electrode 13 covers almost the entire surface of the n-polysilicon region 209a, it is possible to shield the influence of the movable charge at the mold resin interface,
Variations in the breakdown voltage of the power MOSFET can be eliminated.
【００４１】図１０は、本発明の第９実施例で、高耐圧
半導体装置の要部断面図である。第６実施例との違い
は、ｐポリシリコン領域３０９ｃのｎ+ ソース領域３１
０ｃに接するｐベース領域３１０ｆを形成し、ｎ型ＤＭ
ＯＳＦＥＴの構造のようにして、ｎポリシリコン領域３
０９ｄのｐ+ ソース領域３１１ｃに接してｎベース領域
３１１ｆを形成し、ｐ型ＤＭＯＳＦＥＴの構造のように
した点である。ｎ型ＤＭＯＳＦＥＴのゲート電極はソー
ス電極である第１接続導体１４に接続して張り出した第
１導電膜３７であり、ｐ型ＤＭＯＳＦＥＴのゲート電極
はパワーＭＯＳＦＥＴのソース電極である第２接続導体
１５と接続して張り出した第２導電膜３８であり、ｎ型
ＭＯＳＦＥＴのソース電極である第１接続導体１４とゲ
ート電極である第１導電膜３７、ｐ型ＭＯＳＦＥＴのソ
ース電極である第２接続導体１５とゲート電極である第
２導電膜３８が同一電位を有するバイアス条件となって
いる。FIG. 10 is a sectional view of a main part of a high-voltage semiconductor device according to a ninth embodiment of the present invention. The difference from the sixth embodiment is that the n + source region 31 of the p polysilicon region 309c
0c is formed to form a p base region 310f, and an n-type DM
As in the structure of the OSFET, the n polysilicon region 3
The difference is that an n base region 311f is formed in contact with the p + source region 311c of the transistor 09d to have a p-type DMOSFET structure. The gate electrode of the n-type DMOSFET is a first conductive film 37 connected to and protruding from the first connection conductor 14 as the source electrode, and the gate electrode of the p-type DMOSFET is connected to the second connection conductor 15 as the source electrode of the power MOSFET. A second conductive film 38 connected and protruding, the first connecting conductor 14 being the source electrode of the n-type MOSFET, the first conductive film 37 being the gate electrode, and the second connecting conductor 15 being the source electrode of the p-type MOSFET. And the second conductive film 38 as a gate electrode has a bias condition of having the same potential.
【００４２】ｐポリシリコン領域３０９ｃおよびｎポリ
シリコン領域３０９ｄの高抵抗領域３１０ｅ、３１１ｅ
の不純物濃度を１×１０15ｃｍ-3程度、ｐベース領域３
１０ｆおよびｎベース領域３１１ｆの表面濃度を１×１
０16ｃｍ-3程度とすることで、サブスレッシュホールド
電流を流し、中央の第２ｎ+ 領域３１０ｄ、第２ｐ+領
域３１１ｄのドレイン領域で電子と正孔が再結合する。
ｐポリシリコン領域３０９ｃおよびｎポリシリコン領域
３０９ｄの内部に比較的均一な電位分布が形成されるこ
とで、ｐ基板１に形成された主素子であるパワーＭＯＳ
ＦＥＴの表面電界緩和を行い耐圧を高めている。ｐベー
ス領域３１０ｆおよびｎベース領域３１１ｆによりｎ型
ＤＭＯＳＦＥＴおよびｐ型ＤＭＯＳＦＥＴのソース・ド
レイン間のパンチスルーを防止している。また、ソース
電極である第１および第２導電膜がｐポリシリコン領域
３０９ｃ上およびｎポリシリコン領域３０９ｄ上をほぼ
全面的に覆うため、モールド樹脂２０の界面の可動電荷
の影響を遮蔽でき、パワーＭＯＳＦＥＴの耐圧変動を無
くすことができる。The high resistance regions 310e and 311e of the p polysilicon region 309c and the n polysilicon region 309d
Impurity concentration of about 1 × 10 15 cm −3 and the p base region 3
The surface concentration of 10f and n base region 311f is 1 × 1
By setting it to about 0 16 cm −3 , a sub-threshold current flows, and electrons and holes are recombined in the central drain region of the second n + region 310d and the second p + region 311d.
Since a relatively uniform potential distribution is formed inside p polysilicon region 309c and n polysilicon region 309d, power MOS which is a main element formed on p substrate 1 is formed.
The withstand voltage is increased by relaxing the surface electric field of the FET. The p-base region 310f and the n-base region 311f prevent punch-through between the source and drain of the n-type DMOSFET and the p-type DMOSFET. In addition, since the first and second conductive films serving as source electrodes cover substantially the entire surface of the p polysilicon region 309c and the n polysilicon region 309d, the influence of the movable charge at the interface of the mold resin 20 can be shielded. Variations in the breakdown voltage of the MOSFET can be eliminated.
【００４３】図１１は、本発明の第１０実施例で、高耐
圧半導体装置の要部断面図である。これは図１３の従来
例に対し、第１メタルである第１導電膜４１７を形成し
た後に、シリコンの組成比を高めに設定した窒化膜４２
０（ｎ型の導電性をもつｎ型のＳｉ+ 窒化膜）を形成
し、さらに通常の窒化膜（絶縁窒化膜）であるパッシベ
ーション膜４１９などを形成し、さらにコンタクトホー
ルを、ソース電極１２上に形成した第１導電膜４１７に
形成し、パッシベーション膜４１９上に第２のメタルで
ある第３導電膜４２１を被覆する。絶縁窒化膜であるパ
ッシベーション膜４１９を介してソース電極１２に接続
する第１導電膜４１７に接続した第３導電膜４２１が、
ｎ型のＳｉ+ 窒化膜４２０上に存在するため、第２のメ
タルである第３導電膜４２１によりｎ型のＳｉ+ 窒化膜
４２０は、空乏化しリーク電流を低く押さえることがで
き、そのため高温でのパワーＭＯＳＦＥＴの熱暴走を防
ぐことができる。前記の実施例同様、第３導電膜４２１
がｎ型のＳｉ+ 窒化膜４２０上を覆っているため、モー
ルド樹脂２０の界面の可動電荷の影響を遮蔽でき、パワ
ーＭＯＳＦＥＴの耐圧変動を無くすことができる。FIG. 11 is a sectional view of a principal part of a high breakdown voltage semiconductor device according to a tenth embodiment of the present invention. This is different from the conventional example of FIG. 13 in that after forming the first conductive film 417 as the first metal, the nitride film 42 having a higher silicon composition ratio is used.
0 (n-type Si + nitride film having n-type conductivity), a passivation film 419, which is a normal nitride film (insulating nitride film), and the like, and a contact hole is formed on the source electrode 12. Is formed on the first conductive film 417, and the third conductive film 421 as the second metal is coated on the passivation film 419. The third conductive film 421 connected to the first conductive film 417 connected to the source electrode 12 via the passivation film 419, which is an insulating nitride film,
Since the n-type Si + nitride film 420 is present on the n-type Si + nitride film 420, the n-type Si + nitride film 420 is depleted by the third conductive film 421, which is the second metal, and the leak current can be suppressed low. Thermal runaway of the power MOSFET can be prevented. The third conductive film 421 as in the above embodiment.
Covers the n-type Si + nitride film 420, the influence of the movable charge at the interface of the mold resin 20 can be shielded, and the withstand voltage fluctuation of the power MOSFET can be eliminated.
【００４４】図１２は、本発明の第１１実施例で、高耐
圧半導体装置の要部断面図である。これは図１１との違
いは、ｎ型のＳｉ+ 窒化膜４２０がｐ型の導電性を持つ
ｐ型のＳｉ+ 窒化膜５２０となっている点である。ドレ
イン電極１３上に形成した第２導電膜４１０に接続し
て、張り出した第２のメタルである第４導電膜５２１に
よりｐ型のＳｉ+ 窒化膜５２０は空乏化しリーク電流を
低く押さえることができ、このため高温でのパワーＭＯ
ＳＦＥＴの熱暴走を防ぐことができる。前記の実施例同
様、第４導電膜５２１がｐ型のＳｉ+ 窒化膜５２０上を
覆っているため、モールド樹脂２０の界面の可動電荷の
影響を遮蔽でき、パワーＭＯＳＦＥＴの耐圧変動を無く
すことができる。FIG. 12 is a sectional view of a principal part of a high voltage semiconductor device according to an eleventh embodiment of the present invention. This is different from FIG. 11 in that the n-type Si + nitride film 420 is a p-type Si + nitride film 520 having p-type conductivity. The p-type Si + nitride film 520 is connected to the second conductive film 410 formed on the drain electrode 13 and is overhanged by the overhanging fourth metal conductive film 521, so that the leak current can be suppressed low. Power MO at high temperature
Thermal runaway of the SFET can be prevented. As in the above embodiment, since the fourth conductive film 521 covers the p-type Si + nitride film 520, the influence of the movable charge at the interface of the mold resin 20 can be shielded, and the withstand voltage fluctuation of the power MOSFET can be eliminated. it can.
【００４５】前記したように、層間絶縁膜の内部、ある
いはモールド樹脂２０との界面に電界緩和用の前記のよ
うな構造を設けることで、高耐圧半導体装置の耐圧を向
上するとともに、モールド樹脂界面の可動イオンの影響
を遮蔽することもでき、さらに、温度特性の面でも熱暴
走を生じない素子構造とすることができる。As described above, by providing the above-described structure for alleviating the electric field inside the interlayer insulating film or at the interface with the mold resin 20, the withstand voltage of the high withstand voltage semiconductor device can be improved, and the mold resin interface can be improved. Can be shielded from the influence of mobile ions, and an element structure that does not cause thermal runaway in terms of temperature characteristics can also be obtained.
【００４６】[0046]
【発明の効果】この発明によれば、モールド樹脂界面の
可動電荷の影響を遮蔽でき、主素子の耐圧変動を無くす
ことができる。また、層間絶縁膜下あるいはパッシべー
ション膜下にＪＦＥＴ構造あるいはＭＯＳＦＥＴ構造の
ポリシリコンフィールドプレートやＳｉ+ 窒化膜を形成
し、このＪＦＥＴあるいはＭＯＳＦＥＴをピンチオフあ
るいはサブスレッシュホールド領域で動作させること
で、これらの電界緩和ＪＦＥＴあるいはＭＯＳＦＥＴの
電流を低減し、オフ状態の電力損失を低減するととも
に、高温動作での熱暴走を回避する効果を有する。According to the present invention, the influence of the movable charge at the mold resin interface can be shielded, and the withstand voltage fluctuation of the main element can be eliminated. In addition, a polysilicon field plate or a Si + nitride film having a JFET structure or a MOSFET structure is formed under an interlayer insulating film or a passivation film, and the JFET or MOSFET is operated in a pinch-off or sub-threshold region. This has the effect of reducing the current of the electric field relaxation JFET or MOSFET, reducing the power loss in the off state, and avoiding thermal runaway at high temperature operation.
【図１】本発明の第１実施例で、高耐圧半導体装置の要
部断面図FIG. 1 is a cross-sectional view of a main part of a high breakdown voltage semiconductor device according to a first embodiment of the present invention.
【図２】図１の高耐圧半導体装置に電圧を印加した状態
を示す図FIG. 2 is a diagram showing a state where a voltage is applied to the high breakdown voltage semiconductor device of FIG. 1;
【図３】本発明の第２実施例で、高耐圧半導体装置の要
部断面図FIG. 3 is a sectional view of a main part of a high breakdown voltage semiconductor device according to a second embodiment of the present invention;
【図４】本発明の第３実施例で、高耐圧半導体装置の要
部断面図FIG. 4 is a sectional view of a main part of a high breakdown voltage semiconductor device according to a third embodiment of the present invention;
【図５】本発明の第４実施例で、高耐圧半導体装置の要
部断面図FIG. 5 is a sectional view of a main part of a high breakdown voltage semiconductor device according to a fourth embodiment of the present invention;
【図６】本発明の第５実施例で、高耐圧半導体装置の要
部断面図FIG. 6 is a sectional view of a main part of a high breakdown voltage semiconductor device according to a fifth embodiment of the present invention.
【図７】本発明の第６実施例で、高耐圧半導体装置の要
部断面図FIG. 7 is a sectional view of a main part of a high breakdown voltage semiconductor device according to a sixth embodiment of the present invention;
【図８】本発明の第７実施例で、高耐圧半導体装置の要
部断面図FIG. 8 is a sectional view of a main part of a high breakdown voltage semiconductor device according to a seventh embodiment of the present invention.
【図９】本発明の第８実施例で、高耐圧半導体装置の要
部断面図FIG. 9 is a sectional view of a main part of a high breakdown voltage semiconductor device according to an eighth embodiment of the present invention;
【図１０】本発明の第９実施例で、高耐圧半導体装置の
要部断面図FIG. 10 is a sectional view of a main part of a high breakdown voltage semiconductor device according to a ninth embodiment of the present invention;
【図１１】本発明の第１０実施例で、高耐圧半導体装置
の要部断面図FIG. 11 is a sectional view of a main part of a high breakdown voltage semiconductor device according to a tenth embodiment of the present invention;
【図１２】本発明の第１１実施例で、高耐圧半導体装置
の要部断面図FIG. 12 is a sectional view of a main part of a high breakdown voltage semiconductor device according to an eleventh embodiment of the present invention.
【図１３】従来の高耐圧半導体装置の要部断面図FIG. 13 is a sectional view of a main part of a conventional high breakdown voltage semiconductor device.
【図１４】従来の高耐圧半導体装置の要部断面図FIG. 14 is a sectional view of a main part of a conventional high breakdown voltage semiconductor device.
【図１５】モールド樹脂７２０の界面に可動イオンが存
在する場合の図FIG. 15 is a diagram when mobile ions are present at an interface of a mold resin 720.
１ ｐ基板 ２ ｎ+ ソース領域 ３ ｐ+ 基板コンタクト領域 ４ ｎウエル領域 ５ ｎ+ ドレイン領域 ６ ゲート酸化膜 ７ ゲート電極 ８ 熱酸化膜 ９、３０９ ポリシリコンフィールドプレート ９ａ、２０９、３０９ ｎポリシリコンフィールドプレ
ート ９ｂ、１０９ ｐポリシリコンフィールドプレート ９ｃ、２０９ａ、３０９ｄ ｎポリシリコン領域 ９ｄ、１０９ａ、３０９ｃ ｐポリシリコン領域 １０、１１０、２１０ｂ、３１０ｃ 第１ｎ+ 領域 １０ｂ、３１１ｃ 第１ｐ+ 領域 １０ｃ ｎ+ 領域 １１、１１１、２１１ｂ、３１０ｄ 第２ｎ+ 領域 １１ｂ、３１１ｄ 第２ｐ+ 領域 １１ｃ ｐ+ 領域 １２ ソース電極 １３ ドレイン電極 １４ 第１接続導体 １５ 第２接続導体 １６、４１６ 層間絶縁膜 １７、２７、３７、４１７ 第１導電膜 １８、２８、３８、４１８ 第２導電膜 １９、４１９ パッシベーション膜 ２０ モールド樹脂 ３０ ｐｎ接合 １０９ｂ、３１０ｆ ｐベース領域 ２０９ｂ ｎベース領域 ３１０ｅ、３１１ｅ 高抵抗領域 ３１１ｆ ｎベース領域 ４２０ ｎ型のＳｉ+ 窒化膜 ４２１ 第３導電膜 ５２０ ｐ型のＳｉ+ 窒化膜 ５２１ 第４導電膜Reference Signs List 1 p substrate 2 n + source region 3 p + substrate contact region 4 n well region 5 n + drain region 6 gate oxide film 7 gate electrode 8 thermal oxide film 9, 309 polysilicon field plate 9 a, 209, 309 n polysilicon field Plate 9b, 109p polysilicon field plate 9c, 209a, 309dn n polysilicon region 9d, 109a, 309c p polysilicon region 10, 110, 210b, 310c first n + region 10b, 311c first p + region 10cn + region 11 , 111, 211b, 310d Second n + region 11b, 311d Second p + region 11cp + region 12 Source electrode 13 Drain electrode 14 First connection conductor 15 Second connection conductor 16, 416 Interlayer insulating film 17, 27, 37, 417 First conductive films 18, 28, 8,418 second conductive 19,419 passivation film 20 mold resin 30 pn junction 109b, 310f p base region 209 b n base region 310e, 311 e high resistance region 311f n base region 420 n-type Si + nitride film 421 third conductive Film 520 p-type Si + nitride film 521 fourth conductive film
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 4M104 BB01 CC05 FF10 GG14 HH18 5F040 DA00 DA02 DB03 DB05 DB06 DB08 DB10 EA00 EB12 EC07 EC19 EF18 EL06 EM01 EM06 5F048 AA05 AC04 AC10 BA01 BA20 BB01 BB06 BC16 BE08 BG01 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 BB01 CC05 FF10 GG14 HH18 5F040 DA00 DA02 DB03 DB05 DB06 DB08 DB10 EA00 EB12 EC07 EC19 EF18 EL06 EM01 EM06 5F048 AA05 AC04 AC10 BA01 BA20 BB01 BB06 BC16 BE08 BG01
Claims (12)
と、高電位側の第２領域を有し、第１領域と第２領域と
の間で電位の遷移を行う高耐圧半導体装置において、第
１領域と第２領域に挟まれた半導体基板の主面上に絶縁
膜を介してｎ型抵抗性膜を形成し、第１領域側の該ｎ型
抵抗性膜の端部と第１領域が電気的に接続し、第２領域
側の該ｎ型抵抗性膜の端部と第２領域が電気的に接続
し、該ｎ型抵抗性膜上に絶縁膜を介して形成され、第１
領域側のｎ型抵抗性膜の端部と電気的に接続する第１導
電膜を有することを特徴とする高耐圧半導体装置。A high breakdown voltage semiconductor having a first region on a low potential side and a second region on a high potential side in a surface layer of a semiconductor substrate, and performing a potential transition between the first region and the second region. In the device, an n-type resistive film is formed on a main surface of a semiconductor substrate sandwiched between a first region and a second region via an insulating film, and an end of the n-type resistive film on a first region side is formed. The first region is electrically connected, the end of the n-type resistive film on the second region side is electrically connected to the second region, and is formed on the n-type resistive film via an insulating film. , First
A high breakdown voltage semiconductor device comprising a first conductive film electrically connected to an end of an n-type resistive film on a region side.
と、高電位側の第２領域を有し、第１領域と第２領域と
の間で電位の遷移を行う高耐圧半導体装置において、第
１領域と第２領域に挟まれた半導体基板の表面層に絶縁
膜を介してｐ型抵抗性膜を形成し、第１領域側の該ｐ型
抵抗性膜の端部と第１領域が電気的に接続し、第２領域
側の該ｐ型抵抗性膜の端部と第２領域が電気的に接続
し、該ｐ型抵抗性膜上に絶縁膜を介して形成され、第２
領域側のｐ型抵抗性膜の端部と電気的に接続する第２導
電膜を有することを特徴とする高耐圧半導体装置。2. A high withstand voltage semiconductor having a first region on a low potential side and a second region on a high potential side in a surface layer of a semiconductor substrate, and performing a potential transition between the first region and the second region. In the device, a p-type resistive film is formed on a surface layer of a semiconductor substrate sandwiched between a first region and a second region via an insulating film, and an end of the p-type resistive film on the first region side and a first resistive film are formed. One region is electrically connected, an end of the p-type resistive film on the second region side is electrically connected to the second region, and is formed on the p-type resistive film via an insulating film; Second
A high breakdown voltage semiconductor device comprising a second conductive film that is electrically connected to an end of a p-type resistive film on a region side.
と、高電位側の第２領域を有し、第１領域と第２領域と
の間で電位の遷移を行う高耐圧半導体装置において、第
１領域と第２領域に挟まれた半導体基板の主面上に絶縁
膜を介して第１領域側がｎ型抵抗性膜、第２領域側がｐ
型抵抗性膜となるｐｎ接合を有する抵抗性膜を形成し、
ｎ型抵抗性膜の第１領域側の端部と第１領域が電気的に
接続し、ｐ型抵抗性膜の第２領域側の端部と第４領域が
電気的に接続し、前記抵抗性膜上に絶縁膜を介して形成
され、第１領域側のｎ型抵抗性膜の端部と電気的に接続
する第３導電膜と、第２領域側のｐ型抵抗性膜の端部と
電気的に接続する第４導電膜を有することを特徴とする
高耐圧半導体装置。3. A high breakdown voltage semiconductor having a first region on a low potential side and a second region on a high potential side in a surface layer of a semiconductor substrate, and performing a potential transition between the first region and the second region. In the device, the first region side is an n-type resistive film, and the second region side is a p-type film on the main surface of the semiconductor substrate sandwiched between the first region and the second region via an insulating film.
Forming a resistive film having a pn junction to be a type resistive film,
The end of the n-type resistive film on the first region side and the first region are electrically connected, the end of the p-type resistive film on the second region side and the fourth region are electrically connected, and A third conductive film formed on the conductive film via an insulating film and electrically connected to an end of the n-type resistive film on the first region side, and an end of the p-type resistive film on the second region side A high breakdown voltage semiconductor device comprising a fourth conductive film electrically connected to the semiconductor device.
と、高電位側の第２領域を有し、第１領域と第２領域と
の間で電位の遷移を行う高耐圧半導体装置において、第
１領域と第２領域に挟まれた半導体基板の主面上に絶縁
膜を介して両端にｎ型領域を有するｐ型抵抗性膜を形成
し、第１領域側のｎ型領域と第１領域が電気的に接続
し、第２領域側のｎ型領域と第２領域が電気的に接続
し、前記ｐ型抵抗性膜上に絶縁膜を介して形成され第１
領域側のｎ型領域と電気的に接続する第５導電膜を有す
ることを特徴とする高耐圧半導体装置。4. A high withstand voltage semiconductor having a first region on a low potential side and a second region on a high potential side in a surface layer of a semiconductor substrate, and performing a potential transition between the first region and the second region. In the device, a p-type resistive film having n-type regions at both ends is formed on a main surface of a semiconductor substrate sandwiched between a first region and a second region via an insulating film, and an n-type region on the first region side is formed. And the first region are electrically connected, the n-type region on the second region side and the second region are electrically connected, and the first region is formed on the p-type resistive film via an insulating film.
A high breakdown voltage semiconductor device comprising a fifth conductive film electrically connected to an n-type region on the region side.
と、高電位側の第２領域を有し、第１領域と第２領域と
の間で電位の遷移を行う高耐圧半導体装置において、第
１領域と第２領域に挟まれた半導体基板の主面上に絶縁
膜を介して両端にｐ型領域を有するｎ型抵抗性膜を形成
し、第１領域側のｐ型領域と第１領域が電気的に接続
し、第２領域側のｐ型領域と第２領域が電気的に接続
し、前記ｎ型抵抗性膜上に絶縁膜を介して形成され第２
領域側のｐ型領域と電気的に接続する第６導電膜を有す
ることを特徴とする高耐圧半導体装置。5. A high breakdown voltage semiconductor having a first region on a low potential side and a second region on a high potential side in a surface layer of a semiconductor substrate, and performing a potential transition between the first region and the second region. In the device, an n-type resistive film having p-type regions at both ends is formed on a main surface of a semiconductor substrate sandwiched between a first region and a second region via an insulating film, and a p-type region on the first region side is formed. And the first region are electrically connected, the p-type region on the second region side and the second region are electrically connected, and the second region is formed on the n-type resistive film via an insulating film.
A high breakdown voltage semiconductor device comprising a sixth conductive film electrically connected to a p-type region on the region side.
と、高電位側の第２領域を有し、第１領域と第２領域と
の間で電位の遷移を行う高耐圧半導体装置において、第
１領域と第２領域に挟まれた半導体基板の主面上に絶縁
膜を介して第１領域側がｎ型抵抗性膜、第２領域側がｐ
型抵抗性膜となるｐｎ接合を有する抵抗性膜を形成し、
第１領域側のｐ型抵抗性膜の両端にｎ型領域を形成し、
第２領域側のｎ型抵抗性膜の両端にｐ型領域を形成し、
第１領域側のｎ型領域と第１領域が電気的に接続し、第
２領域側のｐ型領域と第２領域が電気的に接続し、前記
抵抗性膜膜上に絶縁膜を介して形成され、第１領域側の
ｎ型領域と電気的に接続する第７導電膜と、第２領域側
のｐ型領域と電気的に接続する第８導電膜を有すること
を特徴とする高耐圧半導体装置。6. A high breakdown voltage semiconductor having a first region on a low potential side and a second region on a high potential side in a surface layer of a semiconductor substrate, and performing a potential transition between the first region and the second region. In the device, the first region side is an n-type resistive film, and the second region side is a p-type film on the main surface of the semiconductor substrate sandwiched between the first region and the second region via an insulating film.
Forming a resistive film having a pn junction to be a type resistive film,
Forming n-type regions at both ends of the p-type resistive film on the first region side;
Forming p-type regions at both ends of the n-type resistive film on the second region side;
The n-type region on the first region side is electrically connected to the first region, the p-type region on the second region side is electrically connected to the second region, and an insulating film is formed on the resistive film via an insulating film. A high withstand voltage characterized by having a seventh conductive film formed and electrically connected to the n-type region on the first region side and an eighth conductive film electrically connected to the p-type region on the second region side. Semiconductor device.
と、高電位側の第２領域を有し、第１領域と第２領域と
の間で電位の遷移を行う高耐圧半導体装置において、第
１領域と第２領域に挟まれた半導体基板の主面上に絶縁
膜を介して両端にｎ型領域を有するｐ型抵抗性膜を形成
し、該ｐ型抵抗性膜の第１領域側のｎ型領域と接する、
ｐ型抵抗性膜より不純物濃度が高い高濃度ｐ型領域をｐ
型抵抗性膜に形成し、第１領域側のｎ型領域と第１領域
が電気的に接続し、第２領域側のｎ型領域と第２領域が
電気的に接続し、前記ｐ型抵抗性膜上に絶縁膜を介して
形成され、第１領域側のｎ型領域と電気的に接続する第
９導電膜を形成することを特徴とする高耐圧半導体装
置。7. A high-breakdown-voltage semiconductor having a first region on a low potential side and a second region on a high potential side in a surface layer of a semiconductor substrate, and performing a potential transition between the first region and the second region. In the apparatus, a p-type resistive film having n-type regions at both ends is formed on a main surface of a semiconductor substrate sandwiched between a first region and a second region via an insulating film, and a p-type resistive film of the p-type resistive film is formed. In contact with the n-type region on one side,
A high-concentration p-type region having a higher impurity concentration than the p-type resistive film
The n-type region on the first region side is electrically connected to the first region, and the n-type region on the second region side is electrically connected to the second region; A high-voltage semiconductor device comprising: a ninth conductive film formed on the conductive film via an insulating film and electrically connected to the n-type region on the first region side.
と、高電位側の第２領域を有し、第１領域と第２領域と
の間で電位の遷移を行う高耐圧半導体装置において、第
１領域と第２領域に挟まれた半導体基板の主面上に絶縁
膜を介して両端にｐ型領域を有するｎ型抵抗性膜を形成
し、第２領域側のｐ型領域に接するｎ型抵抗性膜より、
不純物濃度が高い高濃度ｎ型領域をｎ型抵抗性膜に形成
し、第１領域側のｐ型領域と第１領域が電気的に接続
し、第２領域側のｐ型領域と第２領域と電気的に接続
し、前記ｎ型抵抗性膜上に絶縁膜を介して形成され、第
２領域と電気的に接続する第１０導電膜を有することを
特徴とする高耐圧半導体装置。8. A high-breakdown-voltage semiconductor having a first region on a low potential side and a second region on a high potential side in a surface layer of a semiconductor substrate, and performing a potential transition between the first region and the second region. In an apparatus, an n-type resistive film having p-type regions at both ends is formed on a main surface of a semiconductor substrate sandwiched between a first region and a second region via an insulating film, and a p-type region on a second region side is formed. From the n-type resistive film in contact with
A high-concentration n-type region having a high impurity concentration is formed in the n-type resistive film, the p-type region on the first region side is electrically connected to the first region, and the p-type region on the second region side is connected to the second region. And a tenth conductive film formed on the n-type resistive film via an insulating film and electrically connected to the second region.
と、高電位側の第２領域を有し、第１領域と第２領域と
の間で電位の遷移を行う高耐圧半導体装置において、第
１領域と第２領域に挟まれた半導体基板の主面上に絶縁
膜を介して第１領域側がｐ型抵抗性膜、第２領域側がｎ
型抵抗性膜となるｐｎ接合を有する抵抗性膜を形成し、
第１領域側のｐ型抵抗性膜の両端にｎ型領域を形成し、
該ｎ型領域に接するｐ型抵抗性膜より不純物濃度が高い
高濃度ｐ型領域をｐ型抵抗性膜に形成し、第２領域側の
ｎ型抵抗性膜の両端にｐ型領域を形成し、該ｐ型領域と
接するｎ型抵抗性膜より不純物濃度が高い高濃度ｎ型領
域をｐ型抵抗性膜に形成し、第１領域側のｎ型領域と第
１領域が電気的に接続し、第２領域側のｐ型領域と第２
領域が電気的に接続し、前記抵抗性膜上に絶縁膜を介し
て形成され、第１領域と電気的に接続する第１１導電膜
と、第２領域と電気的に接続する第１２導電膜を有する
ことを特徴とする高耐圧半導体装置。9. A high withstand voltage semiconductor having a first region on a low potential side and a second region on a high potential side in a surface layer of a semiconductor substrate, and performing a potential transition between the first region and the second region. In the device, the first region side is a p-type resistive film, and the second region side is an n-type on the main surface of the semiconductor substrate sandwiched between the first region and the second region via an insulating film.
Forming a resistive film having a pn junction to be a type resistive film,
Forming n-type regions at both ends of the p-type resistive film on the first region side;
A high-concentration p-type region having a higher impurity concentration than the p-type resistive film in contact with the n-type region is formed in the p-type resistive film, and p-type regions are formed at both ends of the n-type resistive film on the second region side. Forming a high-concentration n-type region having a higher impurity concentration than the n-type resistive film in contact with the p-type region in the p-type resistive film, and electrically connecting the n-type region on the first region side to the first region; , The p-type region on the second region side and the second
A region electrically connected to the region, an eleventh conductive film formed on the resistive film via an insulating film, and electrically connected to the first region; and a twelfth conductive film electrically connected to the second region. A high voltage semiconductor device characterized by having:
特徴とする請求項１ないし９のうちいずれか一つに記載
の高耐圧半導体装置。10. The high breakdown voltage semiconductor device according to claim 1, wherein the resistive film is made of polysilicon.
徴とする請求項１ないし９のうちいずれか一つに記載の
高耐圧半導体装置。11. The high breakdown voltage semiconductor device according to claim 1, wherein the resistive film is a Si + nitride film.
層に形成されるソース領域およびドレイン領域が第１領
域および第２領域で、半導体基板上に絶縁膜を介して形
成されるゲート電極と、ソース領域上に形成されるソー
ス電極と、ドレイン領域上に形成されるドレイン電極と
を具備する高耐圧横型ＭＯＳＦＥＴであることを特徴と
する請求項１ないし１１のうちいずれか一つに記載の高
耐圧半導体装置。12. A semiconductor device comprising: a first region and a second region having at least a source region and a drain region formed in a surface layer on a main surface side of a semiconductor substrate, and a gate electrode formed on the semiconductor substrate via an insulating film; 12. A high-withstand-voltage lateral MOSFET having a source electrode formed on a source region and a drain electrode formed on a drain region. High breakdown voltage semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11175517A JP2001007327A (en) | 1999-06-22 | 1999-06-22 | High breakdown voltage semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11175517A JP2001007327A (en) | 1999-06-22 | 1999-06-22 | High breakdown voltage semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001007327A true JP2001007327A (en) | 2001-01-12 |
Family
ID=15997448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11175517A Pending JP2001007327A (en) | 1999-06-22 | 1999-06-22 | High breakdown voltage semiconductor device |
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| Country | Link |
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| JP (1) | JP2001007327A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006222210A (en) * | 2005-02-09 | 2006-08-24 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
| WO2009078274A1 (en) * | 2007-12-14 | 2009-06-25 | Fuji Electric Device Technology Co., Ltd. | Integrated circuit, and semiconductor device |
| US8609500B2 (en) | 2011-06-15 | 2013-12-17 | Fujitsu Semiconductor Limited | Semiconductor device production method |
-
1999
- 1999-06-22 JP JP11175517A patent/JP2001007327A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006222210A (en) * | 2005-02-09 | 2006-08-24 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
| WO2009078274A1 (en) * | 2007-12-14 | 2009-06-25 | Fuji Electric Device Technology Co., Ltd. | Integrated circuit, and semiconductor device |
| US8638160B2 (en) | 2007-12-14 | 2014-01-28 | Fuji Electric Co., Ltd. | Integrated circuit and semiconductor device |
| US9411346B2 (en) | 2007-12-14 | 2016-08-09 | Fuji Electric Co., Ltd. | Integrated circuit and semiconductor device |
| US8609500B2 (en) | 2011-06-15 | 2013-12-17 | Fujitsu Semiconductor Limited | Semiconductor device production method |
| US8729610B2 (en) | 2011-06-15 | 2014-05-20 | Fujitsu Semiconductor Limited | Semiconductor device |
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