JP2000353761A - Manufacture of wiring board - Google Patents
Manufacture of wiring boardInfo
- Publication number
- JP2000353761A JP2000353761A JP16489599A JP16489599A JP2000353761A JP 2000353761 A JP2000353761 A JP 2000353761A JP 16489599 A JP16489599 A JP 16489599A JP 16489599 A JP16489599 A JP 16489599A JP 2000353761 A JP2000353761 A JP 2000353761A
- Authority
- JP
- Japan
- Prior art keywords
- conductive material
- intaglio
- reduced pressure
- grooves
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、各種電子機器に用
いる電子部品の製造方法に関し、特に凹版印刷によって
製造される配線基板の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing electronic components used for various electronic devices, and more particularly to a method for manufacturing a wiring board manufactured by intaglio printing.
【０００２】[0002]
【従来の技術】近年、情報通信機器関連の発達と、高速
信号処理、高周波化に対応して、半導体装置には、低コ
ストで小型・軽量・薄型化の要求が高まってきている。
そして、半導体ＩＣ（ベアチップ）と同等レベルまで小
型化された商品が、いろいろな形態で提案されている。
以下、これらを半導体装置と総称して呼ぶ。2. Description of the Related Art In recent years, in response to the development of information communication equipment, high-speed signal processing, and high frequency, demands for low cost, small, light, and thin semiconductor devices have been increasing.
Products that have been miniaturized to the same level as semiconductor ICs (bare chips) have been proposed in various forms.
Hereinafter, these are collectively referred to as semiconductor devices.
【０００３】次に、配線基板とその配線基板を用いた半
導体装置の製造方法を図６、図７によって説明する。Next, a method of manufacturing a wiring board and a semiconductor device using the wiring board will be described with reference to FIGS.
【０００４】図６において、凹版１０５は、厚さ１２５
μｍの可とう性樹脂基材であるポリイミドフィルム１０
２に対し、予め所望の配線パターン１１１及び電極パッ
ド１１２に対応した形状となるようエキシマレーザ装置
（図示せず）を用いて紫外線領域の波長２４８ｎｍのレ
ーザビームを照射して作成される。レーザビームで照射
された部分は、光化学反応で分解されて配線パターン１
１１及び電極パッド１１２に相当する溝１０３及び１０
４が加工される。加工された溝の配線パターン部分１０
３の幅は２５μｍ、電極パッド部分１０４は１００μｍ
×１００μｍで深さは３０μｍである。In FIG. 6, an intaglio 105 has a thickness 125
Polyimide film 10 which is a flexible resin substrate of μm
2 is formed by previously irradiating a laser beam having a wavelength of 248 nm in the ultraviolet region using an excimer laser device (not shown) so as to have a shape corresponding to the desired wiring pattern 111 and electrode pad 112. The part irradiated with the laser beam is decomposed by a photochemical reaction to form a wiring pattern 1.
11 and grooves 103 and 10 corresponding to electrode pads 112
4 is processed. Wiring pattern portion 10 of processed groove
3 has a width of 25 μm, and the electrode pad portion 104 has a width of 100 μm.
× 100 μm and depth is 30 μm.
【０００５】また、凹版１０５の材料として使用してい
るポリイミドフィルム１０２は溝１０３，１０４の中に
充填されて転写される導電性材料１０６とポリイミドフ
ィルム１０２との剥離性が十分でない。そのため、転写
工程において溝１０３，１０４の内部に導電性材料１０
６が残存しやすい。そこで、予め凹版１０５の表面、特
に溝１０３，１０４の内壁に剥離層（図示せず）を形成
しておく。剥離層はフッ化炭素系単分子膜を使用してい
る。Further, the polyimide film 102 used as the material of the intaglio 105 has insufficient peeling properties between the conductive material 106 filled in the grooves 103 and 104 and transferred, and the polyimide film 102. Therefore, the conductive material 10 is formed inside the grooves 103 and 104 in the transfer process.
6 easily remains. Therefore, a release layer (not shown) is formed in advance on the surface of the intaglio 105, particularly on the inner walls of the grooves 103 and 104. The release layer uses a fluorocarbon-based monomolecular film.
【０００６】次に、剥離層が形成された凹版１０５の表
面に導電性材料１０６としてＡｇ／Ｐｄペーストを塗布
する。そして、塗布後の凹版１０５の表面をスキージ１
１３で掻くことによって凹版表面の余分な導電性材料１
０６を十分に除去する。充填された導電性材料１０６は
凹版１０５とともに乾燥器を用いて乾燥させて、導電性
材料１０６中の有機溶剤を蒸発させる。そのため、有機
溶剤の蒸発分に相当する分の溝１０３，１０４の内部に
充填されている導電性材料１０６の体積が減少する。そ
こで、体積減少分を補うために再び導電性材料１０６の
充填を行う。そして、再び充填した導電性材料１０６に
ついても同様に乾燥を行い、導電性材料１０６中の有機
溶剤を蒸発させる。この導電性材料１０６の充填・乾燥
工程を所定の回数繰り返すことによって、充填される導
電性材料１０６の乾燥後の厚さを溝１０３，１０４の深
さとほぼ同等にすることができる。本例では４回の充填
・乾燥工程を繰り返している。Next, an Ag / Pd paste is applied as a conductive material 106 to the surface of the intaglio 105 on which the release layer has been formed. Then, the surface of the intaglio 105 after coating is squeegee 1
13 to remove excess conductive material 1 on the intaglio surface
06 is sufficiently removed. The filled conductive material 106 is dried together with the intaglio 105 using a dryer to evaporate the organic solvent in the conductive material 106. Therefore, the volume of the conductive material 106 filled in the grooves 103 and 104 corresponding to the amount of evaporation of the organic solvent is reduced. Therefore, the conductive material 106 is filled again to compensate for the reduced volume. Then, the refilled conductive material 106 is dried in the same manner to evaporate the organic solvent in the conductive material 106. By repeating the step of filling and drying the conductive material 106 a predetermined number of times, the thickness of the filled conductive material 106 after drying can be made substantially equal to the depth of the grooves 103 and 104. In this example, the filling and drying steps are repeated four times.
【０００７】続いて、スルーホール１０８加工済みのセ
ラミック基板１０７上に導電性材料１０６が転写される
ように、熱可塑性樹脂よりなる接着層１０９を形成す
る。その後、導電性材料１０６が充填された凹版１０５
の溝１０３，１０４を有する側の面と接着層１０９とを
所定の位置に対向させ、凹版１０５とセラミック基板１
０７とを加熱・加圧して貼り合わせる。Subsequently, an adhesive layer 109 made of a thermoplastic resin is formed so that the conductive material 106 is transferred onto the ceramic substrate 107 on which the through holes 108 have been processed. After that, the intaglio 105 filled with the conductive material 106
The surface on the side having the grooves 103 and 104 and the adhesive layer 109 face each other at a predetermined position.
07 is bonded by heating and pressing.
【０００８】次に、貼り合わせられた凹版１０５とセラ
ミック基板１０７の温度を室温まで下げ、凹版１０５を
セラミック基板１０７から剥離し、セラミック基板１０
７上に導電性材料１０６の転写を行うことで、配線パタ
ーン１１１及び電極パッド１１２が形成される。その
後、このセラミック基板１０７をピーク温度８５０℃の
温度プロファイルの下で焼成する。その後、通常のスク
リーン印刷法により各導体パターン、絶縁層等を形成し
配線基板１０１を完成させる。Next, the temperature of the bonded intaglio 105 and the ceramic substrate 107 is lowered to room temperature, the intaglio 105 is separated from the ceramic substrate 107, and the ceramic substrate 10
By transferring the conductive material 106 onto the wiring 7, a wiring pattern 111 and an electrode pad 112 are formed. Thereafter, the ceramic substrate 107 is fired under a temperature profile with a peak temperature of 850 ° C. Thereafter, each conductor pattern, an insulating layer, and the like are formed by a normal screen printing method, and the wiring substrate 101 is completed.
【０００９】以上の工程により、セラミック基板１０７
上に配線パターン１１１及び電極パッド１１２が形成さ
れ、最小ライン幅２０μｍ、最小ライン間隔４０μｍ、
電極パッド８０μｍ×８０μｍ、そして焼成後の導体膜
厚２０μｍとなる。溝１０３，１０４の寸法よりも小さ
くなったのは、導電性材料が焼成によって収縮したから
である。By the above steps, the ceramic substrate 107
A wiring pattern 111 and an electrode pad 112 are formed thereon, and a minimum line width of 20 μm, a minimum line interval of 40 μm,
The electrode pad has a size of 80 μm × 80 μm, and the conductor thickness after firing is 20 μm. The reason why the size is smaller than the dimensions of the grooves 103 and 104 is that the conductive material shrinks by firing.
【００１０】次に、上述した配線基板１０１を用いた半
導体装置１２４を図７に示す。Next, a semiconductor device 124 using the above-described wiring board 101 is shown in FIG.
【００１１】実装される半導体ＩＣ１２１の電極部１２
２にフリップチップ実装を行うためのＡｕバンプ１２６
を形成する。Ａｕバンプ１２６は、バンプ形成装置（図
示せず）を用いて１つ１つ個別に形成している。次に、
Ａｕバンプ１２６形成後半導体ＩＣ１２１を反転させ、
導電性接着剤１２５をＡｕバンプ１２６上に塗布する。
導電性接着剤１２５には熱硬化タイプのものを用いてい
る。その後、半導体ＩＣ１２１を配線基板１０１上にフ
ェースダウンで実装し、所定の温度で導電性接着剤１２
５を硬化させる。導電性接着剤１２５の硬化終了後、半
導体ＩＣ１２１と配線基板１０１の隙間部分にアンダー
フィル１２３を充填し、所定の温度でアンダーフィル１
２３を硬化させる。以上の工程により半導体装置１２４
を形成することができる。The electrode section 12 of the semiconductor IC 121 to be mounted
Au bump 126 for performing flip chip mounting on 2
To form The Au bumps 126 are individually formed one by one using a bump forming apparatus (not shown). next,
After the formation of the Au bump 126, the semiconductor IC 121 is inverted,
A conductive adhesive 125 is applied on the Au bump 126.
As the conductive adhesive 125, a thermosetting type is used. After that, the semiconductor IC 121 is mounted face down on the wiring board 101, and the conductive adhesive 12 is
5 is cured. After the curing of the conductive adhesive 125 is completed, the gap between the semiconductor IC 121 and the wiring board 101 is filled with the underfill 123, and the underfill 1 is filled at a predetermined temperature.
23 is cured. Through the above steps, the semiconductor device 124
Can be formed.
【００１２】[0012]
【発明が解決しようとする課題】しかしながら上記のよ
うな半導体装置１２４の構成では、Ａｕバンプ１２６を
各電極部１２２上に１つ１つ個別形成しているため、半
導体ＩＣ１２１の高集積化に伴い電極部１２２の数が増
加すれば、必然的にＡｕバンプ１２６の形成時間が長く
なり、生産の高タクト化を招いてしまうこととなる。ま
た、半導体ＩＣ１２１の電極部１２２と基板１０１の電
極パッド１１２との導通を確実に行うためには、各電極
部１２２上に設けられたＡｕバンプ１２６の形状、特に
高さ形状を常に一定に揃える必要があり、そのため従来
のような個々に各電極部１２２上にＡｕバンプ１２６を
形成する方法では、常に安定した形状のＡｕバンプ１２
６を形成することが非常に困難であった。However, in the configuration of the semiconductor device 124 as described above, the Au bumps 126 are individually formed on the respective electrode portions 122, one by one. If the number of the electrode portions 122 increases, the formation time of the Au bump 126 is inevitably increased, which leads to an increase in production tact. In addition, in order to ensure conduction between the electrode section 122 of the semiconductor IC 121 and the electrode pad 112 of the substrate 101, the shape, particularly the height, of the Au bump 126 provided on each electrode section 122 is always uniform. For this reason, the conventional method of individually forming the Au bumps 126 on each of the electrode portions 122 requires the Au bumps 12 having a stable shape.
6 was very difficult to form.
【００１３】本発明は上記課題を解決するためのもので
あり、半導体装置の製造時間を短縮するとともに、半導
体ＩＣの実装に必要となる常に安定した形状のバンプを
有する配線基板の製造方法を実現することを目的とす
る。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and realizes a method of manufacturing a wiring board having bumps of always stable shapes required for mounting a semiconductor IC while shortening the manufacturing time of a semiconductor device. The purpose is to do.
【００１４】[0014]
【課題を解決するための手段】上記目的を達成するため
に本発明は、従来半導体ＩＣ側に形成していたバンプ
を、基板側に配線パターンと同一の材料で一体化して形
成するための凹版転写印刷において、安定したバンプ形
状を実現する方法として、凹版に形成しているバンプに
対応した溝内に導電性材料を充填する際に、導電性材料
の乾燥方法を、減圧による溶剤成分の蒸発を利用して行
うとしたものである。また、更に効率よく充填するため
に、凹版を回転させて遠心力を利用しながら減圧を行っ
て導電性材料を乾燥する方法を用いても良い。SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides an intaglio plate for integrally forming a bump formed on a semiconductor IC side on a substrate side with the same material as a wiring pattern. In transfer printing, as a method of realizing a stable bump shape, when filling the conductive material into the groove corresponding to the bump formed in the intaglio, the method of drying the conductive material is determined by evaporating the solvent component by decompression. This is done using Further, for more efficient filling, a method of rotating the intaglio plate and reducing the pressure while utilizing centrifugal force to dry the conductive material may be used.
【００１５】この方法により、凹版への導電性材料の充
填時に気泡を混入することなく、凹版内を導電性材料で
充満させることができるので、凹版転写印刷により形成
されるバンプの転写歩留りを向上させることができると
ともに、高さばらつきのないバンプが配線パターン上に
一体形成されるため、実装される半導体ＩＣの電極部と
バンプの導通も確実に行うことができる。According to this method, since the intaglio can be filled with the conductive material without introducing bubbles when the intaglio is filled with the conductive material, the transfer yield of bumps formed by intaglio transfer printing can be improved. In addition, since bumps having no variation in height are integrally formed on the wiring pattern, conduction between the bumps and the electrodes of the semiconductor IC to be mounted can be reliably performed.
【００１６】[0016]
【発明の実施の形態】本発明の請求項１に記載の発明
は、実装される電子部品に設けられた電極部と電気的に
接続される突起部が、基板上に配線パターンと一体かつ
同時に形成される配線基板の製造方法であって、フィル
ムに所望の前記配線パターンに対応する第１の溝と前記
配線パターン上の所望の位置にある前記突起部に対応す
る第２の溝を形成する工程と、前記第１及び第２の溝に
導電性材料を充填する工程と、前記フィルムに充填され
た導電性材料を接着層を介して基板に転写し焼成する工
程において、前記第１及び第２の溝に充填された導電性
材料を減圧により溶剤成分を蒸発させて乾燥することを
特徴とする配線基板の製造方法としたものであり、導電
性材料を減圧による溶剤成分の蒸発を用いて乾燥するた
め、凹版内壁と導電性材料間に隙間を作ることなく、凹
版内に導電性材料を充満させることができる。そのた
め、配線パターン上に安定した形状の突起部を形成する
ことができる。また、配線パターンと同一の導電性材料
で突起部を形成することができるため、突起部と配線パ
ターンとの電気的な接続を確実に行うことができ、実装
される電子部品の電極部と突起部との電気的な接続も確
実に行うことができるという作用を有する。DESCRIPTION OF THE PREFERRED EMBODIMENTS According to a first aspect of the present invention, a projection electrically connected to an electrode provided on an electronic component to be mounted is integrated with a wiring pattern on a substrate at the same time. A method of manufacturing a wiring board to be formed, wherein a first groove corresponding to a desired wiring pattern and a second groove corresponding to the protrusion at a desired position on the wiring pattern are formed in a film. A step of filling the first and second grooves with a conductive material, and a step of transferring the conductive material filled in the film to a substrate via an adhesive layer and baking the first and second grooves. A method for manufacturing a wiring board, characterized in that a solvent component is evaporated under reduced pressure to dry a conductive material filled in the groove of No. 2, and the conductive material is evaporated using a solvent component under reduced pressure. Conducts conductivity with intaglio inner wall to dry Without forming a gap between the materials, it is possible to fill a conductive material in the intaglio. Therefore, a projection having a stable shape can be formed on the wiring pattern. In addition, since the projection can be formed of the same conductive material as the wiring pattern, electrical connection between the projection and the wiring pattern can be reliably performed, and the electrode and the projection of the electronic component to be mounted can be formed. This has the effect that electrical connection with the section can be reliably performed.
【００１７】本発明の請求項２に記載の発明は、前記第
１及び第２の溝に充填された導電性材料を遠心回転を用
いた遠心力により前記第１及び第２の溝の深部に押し込
みながら乾燥することを特徴とする請求項１記載の配線
基板の製造方法としたものであり、導電性材料を減圧に
よる溶剤成分の蒸発を使って、さらに遠心力により導電
性材料を凹版内へ押し込みながら乾燥するため、凹版内
に導電性材料を気泡なく充満させることができる。その
ため、配線パターン上に安定した形状の突起部を形成す
ることができる。また、配線パターンと同一の導電性材
料で突起部を形成することができるため、突起部と配線
パターンとの電気的な接続を確実に行うことができ、実
装される電子部品の電極部と突起部との電気的な接続も
確実に行うことができるという作用を有する。According to a second aspect of the present invention, the conductive material filled in the first and second grooves is placed in a deep portion of the first and second grooves by centrifugal force using centrifugal rotation. 2. The method for manufacturing a wiring board according to claim 1, wherein the conductive material is dried while being pushed in, and the conductive material is evaporated into the intaglio by centrifugal force by using evaporation of a solvent component due to reduced pressure. Since it is dried while being pressed, the intaglio can be filled with the conductive material without bubbles. Therefore, a projection having a stable shape can be formed on the wiring pattern. In addition, since the projection can be formed of the same conductive material as the wiring pattern, electrical connection between the projection and the wiring pattern can be reliably performed, and the electrode and the projection of the electronic component to be mounted can be formed. This has the effect that electrical connection with the section can be reliably performed.
【００１８】本発明の請求項３に記載の発明は、加熱し
ながら減圧または減圧下で遠心回転を用いて乾燥するこ
とを特徴とする請求項１または請求項２記載の配線基板
の製造方法としたものであり、導電性材料を減圧による
溶剤成分の蒸発を使って、或いは減圧と遠心力により導
電性材料を凹版内へ押し込みながら乾燥する際に短時間
で乾燥が完了し、凹版内に導電性材料を気泡なく充満さ
せることができる。そのため、配線パターン上に安定し
た形状の突起部を形成することができる。また、配線パ
ターンと同一の導電性材料で突起部を形成することがで
きるため、突起部と配線パターンとの電気的な接続を確
実に行うことができ、実装される電子部品の電極部と突
起部との電気的な接続も確実に行うことができるという
作用を有する。According to a third aspect of the present invention, there is provided a method of manufacturing a wiring board according to the first or second aspect, wherein drying is performed by using a centrifugal rotation under reduced pressure or reduced pressure while heating. Drying is completed in a short time when the conductive material is dried by using the evaporation of the solvent component by depressurization or by pushing the conductive material into the intaglio by depressurization and centrifugal force, and the conductive material is transferred into the intaglio. The conductive material can be filled without bubbles. Therefore, a projection having a stable shape can be formed on the wiring pattern. In addition, since the projection can be formed of the same conductive material as the wiring pattern, electrical connection between the projection and the wiring pattern can be reliably performed, and the electrode and the projection of the electronic component to be mounted can be formed. This has the effect that electrical connection with the section can be reliably performed.
【００１９】本発明の請求項４に記載の発明は、加熱温
度は１５０℃以下であることを特徴とする請求項３記載
の配線基板の製造方法としたものであり、１５０℃以下
とすることで導電性材料に含まれる樹脂成分の変成を伴
わずに、溶剤成分の蒸発のみを効率よく行うことができ
るという作用を有する。According to a fourth aspect of the present invention, there is provided the method for manufacturing a wiring board according to the third aspect, wherein the heating temperature is 150 ° C. or less. Thus, it has the effect that only the evaporation of the solvent component can be performed efficiently without the denaturation of the resin component contained in the conductive material.
【００２０】本発明の請求項５に記載の発明は、減圧ま
たは減圧下で遠心回転を用いて乾燥した後、２００℃以
下の乾燥器中で再び乾燥することを特徴とする請求項１
〜４のいずれかに記載の配線基板の製造方法としたもの
であり、乾燥器で乾燥することで更に良好な乾燥状態に
することができる。また２００℃以下とすることで、導
電性材料に含まれる樹脂成分の変成を伴わずに、溶剤成
分の蒸発のみを効率よく行うことができるという作用を
有する。The invention according to claim 5 of the present invention is characterized in that after drying using reduced pressure or centrifugal rotation under reduced pressure, drying is performed again in a dryer at 200 ° C. or lower.
4. The method according to any one of Items 1 to 4, wherein the wiring board is dried by a drier to obtain a more favorable drying state. By setting the temperature to 200 ° C. or lower, there is an effect that only the evaporation of the solvent component can be efficiently performed without the denaturation of the resin component contained in the conductive material.
【００２１】以下、本発明の一実施の形態について、図
１から図５を用いて説明する。An embodiment of the present invention will be described below with reference to FIGS.
【００２２】図１は本実施の形態の製造方法を示してお
り、まず厚さ１２５μｍの可とう性樹脂基材であるポリ
イミドフィルム２にエキシマレーザ装置（図示せず）を
用いて紫外線領域の波長２４８ｎｍのレーザビームを照
射して所望の配線パターン１１に対応する第１の溝３を
形成する。配線パターン１１に対応する部分の第１の溝
３の幅を２５μｍ、深さを３０μｍとした。FIG. 1 shows a manufacturing method according to the present embodiment. First, a polyimide film 2 as a flexible resin base material having a thickness of 125 μm is applied to a wavelength in the ultraviolet region by using an excimer laser device (not shown). The first groove 3 corresponding to the desired wiring pattern 11 is formed by irradiating a 248 nm laser beam. The width of the first groove 3 corresponding to the wiring pattern 11 was 25 μm, and the depth was 30 μm.
【００２３】次に、第１の溝３の加工と同様の方法で、
突起部１２に対応する第２の溝４を形成する。本実施の
形態では突起部１２に対応する第２の溝４の最深部の径
を１２０μｍ、深さを１００μｍとした。可とう性樹脂
基材としては、エキシマレーザによる加工の場合は、光
化学反応で分解される材料であれば何でも可能である
が、他にポリエチレンテレフタレート（ＰＥＴ）やポリ
エーテルイミド（ＰＥＩ）なども使用できる。Next, in the same manner as the processing of the first groove 3,
The second groove 4 corresponding to the protrusion 12 is formed. In the present embodiment, the diameter of the deepest portion of the second groove 4 corresponding to the projection 12 is 120 μm, and the depth is 100 μm. In the case of processing with an excimer laser, any material that can be decomposed by a photochemical reaction can be used as the flexible resin substrate, but other materials such as polyethylene terephthalate (PET) and polyetherimide (PEI) are also used. it can.
【００２４】ここで、凹版５の材料として使用している
ポリイミドフィルム２では第１の溝３及び第２の溝４の
中に充填されて転写される導電性材料６とポリイミドフ
ィルム２との剥離性が十分でない。そのため、転写工程
において第１の溝３及び第２の溝４の内部に導電性材料
６が残存しやすい。そこで、凹版５の表面、特に第１の
溝３及び第２の溝４の内壁に剥離層（図示せず）を形成
する。剥離層はフッ化炭素系単分子膜を使用した。Here, in the polyimide film 2 used as the material of the intaglio 5, the conductive material 6 filled in the first groove 3 and the second groove 4 and transferred is separated from the polyimide film 2. Sex is not enough. Therefore, the conductive material 6 easily remains inside the first groove 3 and the second groove 4 in the transfer step. Therefore, a release layer (not shown) is formed on the surface of the intaglio 5, particularly on the inner walls of the first groove 3 and the second groove 4. The release layer used was a fluorocarbon monomolecular film.
【００２５】次に、剥離層が形成された凹版５の表面に
導電性材料６としてＡｇ／Ｐｄペーストを塗布する。そ
して、塗布後の凹版５の表面をスキージ１３で掻くこと
によって凹版５の表面の余分な導電性材料６を除去する
とともに、第１の溝３及び第２の溝４の中に導電性材料
６を十分に充填する。その後、図２に示すように、充填
された導電性材料６を凹版５とともに減圧装置１４の中
で乾燥させる。減圧下での乾燥は、例えば常圧で１００
℃以上沸点を持つ溶剤であっても、減圧環境下ではその
沸点が下がり、室温においても容易に蒸発させることが
できる。更に、図３に示すように、凹版５を減圧しなが
ら、遠心回転機１５に第１の溝３及び第２の溝４が加工
されている面を内側にしてセットし、遠心回転させて乾
燥を行っても良い。Next, an Ag / Pd paste as a conductive material 6 is applied to the surface of the intaglio 5 on which the release layer has been formed. Then, by scraping the surface of the intaglio 5 after application with a squeegee 13, excess conductive material 6 on the surface of the intaglio 5 is removed, and the conductive material 6 is placed in the first groove 3 and the second groove 4. Fill well. Thereafter, as shown in FIG. 2, the filled conductive material 6 is dried together with the intaglio 5 in the pressure reducing device 14. Drying under reduced pressure is carried out, for example, at 100 at normal pressure.
Even if the solvent has a boiling point of not less than ° C., its boiling point is lowered under a reduced pressure environment, and it can be easily evaporated even at room temperature. Further, as shown in FIG. 3, while the intaglio plate 5 is depressurized, the surface where the first groove 3 and the second groove 4 are processed is set in the centrifugal rotating machine 15 inside, and the centrifugal rotation is performed to dry. May be performed.
【００２６】この方法では、遠心力により導電性材料６
を第１の溝３及び第２の溝４の深部にまで押し込むこと
ができる。通常、導電性材料６を常圧下で乾燥器により
乾燥した場合、導電性材料６中に存在する溶剤成分の蒸
発により、導電性材料６の体積が減少するが、その際、
導電性材料６と第１の溝３及び第２の溝４の内壁との間
に空間ができる。この空間には、空気であったり、導電
性材料６から蒸発した溶剤成分が存在している。そこ
で、この減圧乾燥を用いれば、この空間にある気体につ
いても除去することができる。更に、減圧環境下で遠心
回転することで、第１の溝３及び第２の溝４の最深部に
まで導電性材料６を充填することができる。また、減圧
或いは減圧及び遠心回転による乾燥を室温以上１５０℃
以下の温度に加熱しながら行うことで、導電性材料６の
乾燥にかかる時間を短縮することができる。In this method, the conductive material 6 is formed by centrifugal force.
Can be pushed deep into the first groove 3 and the second groove 4. Usually, when the conductive material 6 is dried by a dryer under normal pressure, the volume of the conductive material 6 is reduced by evaporation of a solvent component present in the conductive material 6.
A space is created between the conductive material 6 and the inner walls of the first groove 3 and the second groove 4. This space contains air or a solvent component evaporated from the conductive material 6. Therefore, if this vacuum drying is used, the gas in this space can also be removed. Further, by performing centrifugal rotation in a reduced pressure environment, the conductive material 6 can be filled up to the deepest portions of the first groove 3 and the second groove 4. Drying under reduced pressure or reduced pressure and centrifugal rotation is performed at room temperature or higher and 150 ° C.
By performing while heating to the following temperature, the time required for drying the conductive material 6 can be reduced.
【００２７】ここで、通常、導電性材料６に使われてい
る溶剤は３００℃以下の沸点を持つものが使われている
ので、減圧環境下では１５０℃以下の温度で十分溶剤を
蒸発させることができる。また、第１の溝３及び第２の
溝４内の導電性材料６の乾燥を完全に行うため、減圧に
よる乾燥の後、乾燥器で再乾燥しても良い。その後、導
電性材料６は乾燥により体積が減少しているので、この
体積減少分を補うために導電性材料６の充填・乾燥工程
を再度繰り返す。乾燥工程は、上記に説明した減圧によ
る乾燥方法を使用することが望ましい。この繰り返しに
よって充填されている導電性材料６の乾燥後の厚さを第
１の溝３及び第２の溝４の深さとほぼ同等にすることが
できる。本例では４回の充填・乾燥を繰り返した。Here, since the solvent used for the conductive material 6 usually has a boiling point of 300 ° C. or less, it is necessary to sufficiently evaporate the solvent at a temperature of 150 ° C. or less under a reduced pressure environment. Can be. Further, in order to completely dry the conductive material 6 in the first groove 3 and the second groove 4, after drying under reduced pressure, drying may be performed again in a dryer. Thereafter, since the volume of the conductive material 6 has been reduced by drying, the filling and drying process of the conductive material 6 is repeated again to compensate for the reduced volume. In the drying step, it is desirable to use the above-described drying method under reduced pressure. By repeating this, the thickness of the filled conductive material 6 after drying can be made substantially equal to the depth of the first groove 3 and the second groove 4. In this example, filling and drying were repeated four times.
【００２８】一方、スルーホール８を形成したセラミッ
ク基板７上に導電性材料６が転写されるように、熱可塑
性樹脂よりなる接着層９を形成する。そして、導電性材
料６が充填された凹版５の表面と接着層９とを対向さ
せ、凹版５とセラミック基板７とを加熱・加圧して貼り
合わせる。ここで、接着層９の厚さが厚くなると、焼成
時に接着層９自身の焼成と収縮力によって導電性材料６
がうまく形成されないという問題点が発生する。この問
題点に対して接着層９の厚さは２０μｍ以下が適当であ
ることが確認されている。貼り合わせ工程の温度は１３
０℃とした。On the other hand, an adhesive layer 9 made of a thermoplastic resin is formed so that the conductive material 6 is transferred onto the ceramic substrate 7 on which the through holes 8 are formed. Then, the surface of the intaglio 5 filled with the conductive material 6 and the adhesive layer 9 are opposed to each other, and the intaglio 5 and the ceramic substrate 7 are bonded by heating and pressing. Here, when the thickness of the adhesive layer 9 is increased, the conductive material 6 is fired and shrunk by the adhesive layer 9 itself during firing.
Is not formed well. It has been confirmed that an appropriate thickness of the adhesive layer 9 is 20 μm or less for this problem. The temperature of the bonding process is 13
0 ° C.
【００２９】これは使用する熱可塑性樹脂のガラス転移
点よりも約３０℃程度高い温度を選び、転写性の良いこ
とを確認した。熱可塑性樹脂は、ポリビニールブチラー
ル樹脂（以下、ＰＶＢと略記）を溶解したブチルカルビ
トールアセテートの溶液をセラミック基板７の表面にデ
ィップ法によって塗布して乾燥する。これによって、セ
ラミック基板７の表面全体に厚さ５μｍのＰＶＢ層を接
着層９として形成する。なお、ＰＶＢ層はディップ法の
他にスピンナー法或いはロールコータ法、スクリーン印
刷法を用いて塗布することもできる。The temperature was selected to be about 30 ° C. higher than the glass transition point of the thermoplastic resin used, and it was confirmed that the transferability was good. As the thermoplastic resin, a solution of butyl carbitol acetate in which polyvinyl butyral resin (hereinafter abbreviated as PVB) is dissolved is applied to the surface of the ceramic substrate 7 by a dip method and dried. Thus, a PVB layer having a thickness of 5 μm is formed as an adhesive layer 9 on the entire surface of the ceramic substrate 7. The PVB layer can be applied by a spinner method, a roll coater method, or a screen printing method in addition to the dipping method.
【００３０】ところで、通常、セラミック基板７の表面
には少なくとも約３０μｍ程度のうねりが存在する。こ
こで凹版５として柔軟性を持っていないような、例えば
ガラス製凹版等の場合には硬く剛性が大きすぎるため
に、貼り合わせ時に凹版が基板のうねり形状に十分に追
従できないが、本発明のようにフレキシブル性に富んだ
樹脂製の凹版５を使用する構成によれば、セラミック基
板７のうねり形状に十分に追従でき、転写性の優れた製
造方法となる。By the way, usually, the surface of the ceramic substrate 7 has undulation of at least about 30 μm. Here, in the case where the intaglio 5 does not have flexibility, for example, in the case of a glass intaglio or the like, the intaglio cannot sufficiently follow the undulating shape of the substrate at the time of bonding, because the intaglio is too hard and rigid. According to the configuration using the intaglio 5 made of resin having high flexibility as described above, it is possible to sufficiently follow the undulating shape of the ceramic substrate 7 and to obtain a manufacturing method excellent in transferability.
【００３１】次に、転写工程として、貼り合わせられた
凹版５とセラミック基板７との温度を室温まで下げてか
ら凹版５をセラミック基板７から剥離させ、配線パター
ン１１及び突起部１２となる導電性材料６の転写を行
う。Next, as a transfer step, the temperature of the bonded intaglio 5 and the ceramic substrate 7 is lowered to room temperature, and then the intaglio 5 is peeled from the ceramic substrate 7, and the conductive pattern for forming the wiring pattern 11 and the projection 12 is formed. The material 6 is transferred.
【００３２】その後、導電性材料６が転写されたセラミ
ック基板２をピーク温度８５０℃の温度プロファイルの
下で焼成する。焼成の対象になるセラミック基板７は接
着層９を介して導電性材料６が形成されている構造にな
るので、焼成条件の設定によっては接着層９から燃焼ガ
スが勢い良く発生して配線パターン１１及び突起部１２
の不良の原因になる剥離や変形が生じることがある。そ
のような不具合の発生を防ぐためには、接着層９の燃焼
が開始されてから終了するまでの温度に相当する２００
〜５００℃の間の昇温時の温度勾配を２００℃／Ｈ以下
にすることが望ましい。Thereafter, the ceramic substrate 2 to which the conductive material 6 has been transferred is fired under a temperature profile with a peak temperature of 850 ° C. Since the ceramic substrate 7 to be fired has a structure in which the conductive material 6 is formed via the adhesive layer 9, depending on the setting of the firing conditions, a combustion gas is generated from the adhesive layer 9 vigorously and the wiring pattern 11 is formed. And projection 12
In some cases, peeling or deformation may occur, which may cause a defect. In order to prevent the occurrence of such a problem, the temperature corresponding to the temperature from the start of combustion of the adhesive layer 9 to the end thereof is set to 200.
It is desirable that the temperature gradient at the time of temperature rise between -500 ° C be 200 ° C / H or less.
【００３３】これらの温度条件と接着層９の膜厚の関係
に検討を加えた結果、上記温度条件の下では接着層９が
２０μｍ以下であれば、導電性材料６の変形もなく、焼
成時の導電性材料６の剥がれも無いことが確認できた。
以上の工程により、配線パターン１１及び突起部１２を
同時に一体化させて形成した配線基板１を製造すること
ができる。この配線基板１の最小ライン幅は２０μｍ、
突起部高さは６０μｍとなる。溝３，４の寸法より小さ
くなったのは、導電性材料６が焼成によって収縮したか
らである。As a result of examining the relationship between these temperature conditions and the film thickness of the adhesive layer 9, if the adhesive layer 9 is 20 μm or less under the above temperature conditions, the conductive material 6 is not deformed and It was confirmed that the conductive material 6 did not peel off.
Through the above steps, it is possible to manufacture the wiring board 1 in which the wiring pattern 11 and the projection 12 are simultaneously integrated. The minimum line width of this wiring board 1 is 20 μm,
The protrusion height is 60 μm. The reason why the size was smaller than the dimensions of the grooves 3 and 4 is that the conductive material 6 contracted by firing.
【００３４】また、配線パターン１１及び突起部１２の
電気抵抗は、最大線長部分で０．４Ω、導体の面積抵抗
値は２．１ｍΩと非常に小さい配線抵抗にすることがで
きる。その後、通常のスクリーン印刷法により各導体パ
ターン、絶縁層等を形成し、配線基板１を完成させる。Further, the electric resistance of the wiring pattern 11 and the protruding portion 12 can be made as extremely small as 0.4 Ω at the maximum line length and the area resistance of the conductor as 2.1 mΩ. Thereafter, the respective conductor patterns, insulating layers and the like are formed by a normal screen printing method, and the wiring board 1 is completed.
【００３５】次に、この配線基板１を用いた半導体装置
２４の製造方法を図４を用いて説明する。Next, a method of manufacturing the semiconductor device 24 using the wiring board 1 will be described with reference to FIG.
【００３６】図４、図５において、２１は半導体ＩＣ
（ベアチップ）であり、その下面の周囲（ペリフェラ
ル）に複数個の電極部２２が形成されている。一般にこ
の電極部２２はＡｌで形成された電極にＡｕメッキ処理
が施されている。また、電極部２２は半導体ＩＣ２１の
下面の周囲だけでなく内側に形成されたものである。こ
の半導体ＩＣ２１を配線基板１に実装する際、配線基板
１上の突起部１２と電極部２２とが図５に示すようにＡ
ｇ／Ｐｄ或いはＡｇ等の導電ペーストやはんだで構成さ
れる導電性材料２５を介して電気的に接続されるように
形成されている。4 and 5, reference numeral 21 denotes a semiconductor IC.
(Bare chip), and a plurality of electrode portions 22 are formed around the lower surface (peripheral). Generally, the electrode portion 22 is formed by applying an Au plating process to an electrode formed of Al. The electrode section 22 is formed not only around the lower surface of the semiconductor IC 21 but also inside. When the semiconductor IC 21 is mounted on the wiring board 1, the protrusions 12 and the electrode portions 22 on the wiring board 1 are connected to each other as shown in FIG.
It is formed so as to be electrically connected via a conductive material 25 made of a conductive paste such as g / Pd or Ag or a solder.
【００３７】また、実装される部品は半導体ＩＣ２１に
限らず、他のチップコンデンサやチップ抵抗器等のよう
なチップ部品を用いても良く、半導体装置２４に用いる
配線基板に限らず、回路基板としても利用することがで
きる。また、２３は突起部１２と電極部２２の接続部を
覆うように半導体ＩＣ２１と配線基板１との間に封入さ
れたエポキシ樹脂等からなるアンダーフィルであり、こ
れにより突起部１２と電極部２２との接続部を保護する
ことができ、長期信頼性を確保することができる。The components to be mounted are not limited to the semiconductor IC 21 but may be chip components such as other chip capacitors and chip resistors, and are not limited to the wiring board used for the semiconductor device 24 but may be used as a circuit board. Can also be used. Reference numeral 23 denotes an underfill made of epoxy resin or the like which is sealed between the semiconductor IC 21 and the wiring board 1 so as to cover the connection between the projection 12 and the electrode 22. Connection can be protected, and long-term reliability can be ensured.
【００３８】本実施の形態においては、以下に示す効果
を有する。The present embodiment has the following effects.
【００３９】可とう性樹脂基材の表面に微細な第１の溝
３及び第２の溝４を形成して凹版５とし、第１の溝３及
び第２の溝４に導電性材料６を充填・乾燥し、乾燥によ
る体積減少分を補うために追加の導電性材料６を再充填
・再乾燥する工程を所定の回数繰り返すことで第１の溝
３及び第２の溝４に導電性材料６を充満し、その凹版５
とセラミック基板７とを貼り合わせ、第１の溝３及び第
２の溝４に充填された導電性材料６をセラミック基板７
上に転写し、焼成して微細な配線パターン１１と突起部
１２を形成する工程において、導電性材料６を減圧或い
は減圧下で遠心力を用いながら成分の蒸発を利用して乾
燥することで、導電性材料６と第１の溝３及び第２の溝
４の内壁との間に発生する気体を除去できるので、完全
に第１の溝３及び第２の溝４の内部に導電性材料６を充
満させることができる。そのため、突起部１２の形状を
安定化させることができ、転写歩留りを向上するととも
に、高さばらつきのない突起部１２を形成することがで
きる。A fine first groove 3 and a second groove 4 are formed on the surface of a flexible resin base material to form an intaglio 5, and a conductive material 6 is filled in the first groove 3 and the second groove 4. The steps of filling and drying and refilling and re-drying the additional conductive material 6 in order to compensate for the decrease in volume due to drying are repeated a predetermined number of times, so that the conductive material is added to the first groove 3 and the second groove 4. 6 and the intaglio 5
And the ceramic substrate 7 are bonded together, and the conductive material 6 filled in the first groove 3 and the second groove 4 is filled with the ceramic substrate 7.
In the step of transferring and baking to form the fine wiring pattern 11 and the projections 12, the conductive material 6 is dried by using the evaporation of the components while reducing pressure or using centrifugal force under reduced pressure. Since gas generated between the conductive material 6 and the inner walls of the first groove 3 and the second groove 4 can be removed, the conductive material 6 is completely contained in the first groove 3 and the second groove 4. Can be charged. Therefore, the shape of the protrusion 12 can be stabilized, the transfer yield can be improved, and the protrusion 12 having no height variation can be formed.
【００４０】[0040]
【発明の効果】以上のように本発明によれば、凹版内に
気泡を混入することなく、導電性材料を充満させること
ができるので、配線パターンと同一の導電性材料で安定
した形状の突起部を形成することができるため、突起部
と配線パターンとの電気的な接続を確実に行うことがで
き、実装される半導体ＩＣの電極部と突起部との電気的
な接続も確実に行うことができる。As described above, according to the present invention, since the conductive material can be filled without mixing bubbles in the intaglio, the protrusion having a stable shape with the same conductive material as the wiring pattern can be obtained. Since the portions can be formed, the electrical connection between the projections and the wiring pattern can be reliably performed, and the electrical connection between the electrode portions of the semiconductor IC to be mounted and the projections can also be reliably performed. Can be.
【００４１】また、基板に配線パターンを形成する際
に、同時にしかも一括して突起部を形成することができ
るため、生産性を大幅に向上させることができるととも
に、突起部の形状を揃えることができ、半導体ＩＣの電
極部との電気的な接続を確実に行うことができる。Further, when the wiring pattern is formed on the substrate, the projections can be formed simultaneously and collectively, so that the productivity can be greatly improved and the shapes of the projections can be made uniform. Thus, electrical connection with the electrode portion of the semiconductor IC can be reliably performed.
【図１】本発明の一実施の形態による配線基板の製造工
程図FIG. 1 is a manufacturing process diagram of a wiring board according to an embodiment of the present invention.
【図２】同実施の形態による導電性材料の充填工程の製
造工程図FIG. 2 is a manufacturing process diagram of a conductive material filling process according to the embodiment.
【図３】同実施の形態による減圧遠心回転機の構造を示
す図FIG. 3 is a diagram showing a structure of a reduced-pressure centrifugal rotary machine according to the embodiment.
【図４】同実施の形態による半導体装置の製造工程図FIG. 4 is a view showing a manufacturing process of the semiconductor device according to the embodiment;
【図５】同実施の形態による半導体装置の構成を示す断
面図FIG. 5 is a sectional view showing the configuration of the semiconductor device according to the same embodiment;
【図６】従来の配線基板の製造工程図FIG. 6 is a manufacturing process diagram of a conventional wiring board.
【図７】従来の半導体装置の製造工程図FIG. 7 is a manufacturing process diagram of a conventional semiconductor device.
１ 配線基板 ２ ポリイミドフィルム ３ 第１の溝 ４ 第２の溝 ５ 凹版 ６ 導電性材料 ７ セラミック基板 ８ スルーホール ９ 接着層 １０ ランド・グリッド・アレイ １１ 配線パターン １２ 突起部 １３ スキージ １４ 減圧乾燥器 １５ 遠心回転機 ２１ 半導体ＩＣ ２２ 電極部 ２３ アンダーフィル ２４ 半導体装置 ２５ 導電性材料 １０１ 配線基板 １０２ ポリイミドフィルム １０３ 溝 １０４ 溝 １０５ 凹版 １０６ 導電性材料 １０７ セラミック基板 １０８ スルーホール １０９ 接着層 １１０ ランド・グリッド・アレイ １１１ 配線パターン １１２ 電極パッド １１３ スキージ １２１ 半導体ＩＣ １２２ 電極部 １２３ アンダーフィル １２４ 半導体装置 １２５ 導電性接着剤 １２６ Ａｕバンプ DESCRIPTION OF SYMBOLS 1 Wiring board 2 Polyimide film 3 First groove 4 Second groove 5 Intaglio 6 Conductive material 7 Ceramic substrate 8 Through hole 9 Adhesive layer 10 Land grid array 11 Wiring pattern 12 Projecting part 13 Squeegee 14 Decompression dryer 15 Centrifugal rotator 21 Semiconductor IC 22 Electrode part 23 Underfill 24 Semiconductor device 25 Conductive material 101 Wiring board 102 Polyimide film 103 Groove 104 Groove 105 Intaglio 106 Conductive material 107 Ceramic substrate 108 Through hole 109 Adhesive layer 110 Land grid array Reference Signs List 111 Wiring pattern 112 Electrode pad 113 Squeegee 121 Semiconductor IC 122 Electrode part 123 Underfill 124 Semiconductor device 125 Conductive adhesive 126 Au bump
フロントページの続き (72)発明者 三浦 和裕 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 ▲高▼瀬 喜久 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Ｆターム(参考） 5E343 DD56 ER33 ER36 ER39 5F044 KK04 KK17 KK19 QQ06 Continuing on the front page (72) Inventor Kazuhiro Miura 1006 Kazuma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. Term (reference) 5E343 DD56 ER33 ER36 ER39 5F044 KK04 KK17 KK19 QQ06
Claims (5)
と電気的に接続される突起部が、基板上に配線パターン
と一体かつ同時に形成される配線基板の製造方法であっ
て、フィルムに所望の前記配線パターンに対応する第１
の溝と前記配線パターン上の所望の位置にある前記突起
部に対応する第２の溝を形成する工程と、前記第１及び
第２の溝に導電性材料を充填する工程と、前記フィルム
に充填された導電性材料を接着層を介して基板に転写し
焼成する工程において、前記第１及び第２の溝に充填さ
れた導電性材料を減圧により溶剤成分を蒸発させて乾燥
することを特徴とする配線基板の製造方法。1. A method of manufacturing a wiring board, wherein a projection electrically connected to an electrode provided on an electronic component to be mounted is formed integrally and simultaneously with a wiring pattern on the board. A first corresponding to the desired wiring pattern
Forming a second groove corresponding to the groove and the protrusion at a desired position on the wiring pattern; filling the first and second grooves with a conductive material; In the step of transferring the filled conductive material to the substrate via the adhesive layer and baking, the conductive material filled in the first and second grooves is dried by evaporating a solvent component under reduced pressure. Method for manufacturing a wiring board.
性材料を遠心回転を用いた遠心力により前記第１及び第
２の溝の深部に押し込みながら乾燥することを特徴とす
る請求項１記載の配線基板の製造方法。2. The method according to claim 1, wherein the conductive material filled in the first and second grooves is dried while being pushed into the deep portions of the first and second grooves by centrifugal force using centrifugal rotation. Item 2. The method for manufacturing a wiring board according to Item 1.
転を用いて乾燥することを特徴とする請求項１または請
求項２記載の配線基板の製造方法。3. The method for producing a wiring board according to claim 1, wherein drying is performed by using a centrifugal rotation under reduced pressure or reduced pressure while heating.
徴とする請求項３記載の配線基板の製造方法。4. The method according to claim 3, wherein the heating temperature is 150 ° C. or lower.
燥した後、２００℃以下の乾燥器中で再び乾燥すること
を特徴とする請求項１〜４のいずれかに記載の配線基板
の製造方法。5. The method of manufacturing a wiring board according to claim 1, wherein the substrate is dried under reduced pressure or centrifugal rotation under reduced pressure, and then dried again in a dryer at 200 ° C. or lower. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16489599A JP2000353761A (en) | 1999-06-11 | 1999-06-11 | Manufacture of wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16489599A JP2000353761A (en) | 1999-06-11 | 1999-06-11 | Manufacture of wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000353761A true JP2000353761A (en) | 2000-12-19 |
Family
ID=15801917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16489599A Withdrawn JP2000353761A (en) | 1999-06-11 | 1999-06-11 | Manufacture of wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000353761A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6861744B2 (en) * | 1997-10-14 | 2005-03-01 | Matsushita Electric Industrial Co., Ltd. | Multilayer ceramic substrate utilizing an intaglio plate with a plurality of grooves having different depths |
-
1999
- 1999-06-11 JP JP16489599A patent/JP2000353761A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6861744B2 (en) * | 1997-10-14 | 2005-03-01 | Matsushita Electric Industrial Co., Ltd. | Multilayer ceramic substrate utilizing an intaglio plate with a plurality of grooves having different depths |
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