JP2000277728A - Insulated-gate semiconductor device and its manufacture - Google Patents
Insulated-gate semiconductor device and its manufactureInfo
- Publication number
- JP2000277728A JP2000277728A JP11080975A JP8097599A JP2000277728A JP 2000277728 A JP2000277728 A JP 2000277728A JP 11080975 A JP11080975 A JP 11080975A JP 8097599 A JP8097599 A JP 8097599A JP 2000277728 A JP2000277728 A JP 2000277728A
- Authority
- JP
- Japan
- Prior art keywords
- outer peripheral
- eqr
- electrode
- region
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 63
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 86
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 86
- 230000002093 peripheral effect Effects 0.000 claims abstract description 79
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 68
- 229920005591 polysilicon Polymers 0.000 claims abstract description 68
- 239000012535 impurity Substances 0.000 claims abstract description 58
- 239000010410 layer Substances 0.000 claims description 41
- 239000011229 interlayer Substances 0.000 claims description 35
- 239000002344 surface layer Substances 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 7
- 238000004904 shortening Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 127
- 210000004027 cell Anatomy 0.000 description 22
- 150000004767 nitrides Chemical class 0.000 description 9
- 238000000206 photolithography Methods 0.000 description 6
- 239000013078 crystal Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ゲート電極を溝の
内部に設けた縦型のＭＯＳＦＥＴやＩＧＢＴ（Ｉｎｓｕ
ｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉ
ｓｔｏｒ）等の絶縁ゲート型半導体装置およびその製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical MOSFET or an IGBT (Insu) having a gate electrode provided inside a groove.
lated Gate Bipolar Transi
and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】この種の絶縁ゲート型半導体装置の代表
例としての電力用のＭＯＳＦＥＴでは、チップ内部のセ
ル部にトランジスタ機能を有する多数の並列接続された
ユニットセルを設け、チップ外周部にＥＱＲ（Equi Ｐo
tential Ring）によるチャネルストッパ構造を設けてい
るのが一般的である。このＭＯＳＦＥＴはチャネルが半
導体本体の溝方向に形成されており、チャネルが半導体
本体の面方向に形成されるゲートプレーナ型のＭＯＳＦ
ＥＴに比較してユニットセルの高集積化が可能であり、
単位面積あたりのチャネル幅を大きくとれ、素子の低オ
ン抵抗化に非常に有効であることが知られている。以
下、従来のＮチャネル型ＭＯＳＦＥＴの構成について、
図６乃至図７を参照して説明する。2. Description of the Related Art In a power MOSFET as a typical example of this type of insulated gate semiconductor device, a plurality of parallel-connected unit cells having a transistor function are provided in a cell portion inside a chip, and an EQR is provided on an outer peripheral portion of the chip. (Equi Po
It is common to provide a channel stopper structure by a tential ring). In this MOSFET, a channel is formed in a groove direction of the semiconductor body, and a channel is formed in a plane direction of the semiconductor body.
Higher integration of unit cells is possible compared to ET,
It is known that a large channel width per unit area can be obtained, which is very effective in reducing the on-resistance of the device. Hereinafter, regarding the configuration of the conventional N-channel MOSFET,
This will be described with reference to FIGS.
【０００３】図６において、１は半導体本体で、高濃度
Ｎ型であるＮ+ 型半導体基板２と、この半導体基板２上
に設け、セル部Ａ表面にＵ字型溝３が格子状に形成され
るとともにチップ外周部Ｂ表面に外周端から所定距離離
間して外周溝４がリング状に形成されたエピタキシャル
層５とを有している。まず、セル部Ａについて説明す
る。エピタキシャル層５表面に形成されたＵ字型溝３の
内部にゲート酸化膜６を介してポリシリコンからなるゲ
ート電極７が形成されている。エピタキシャル層５はエ
ピタキシャル層５の初期層であり低濃度Ｎ型であるＮ-
型ドレイン領域８と、このドレイン領域８表面層のＵ字
型溝３により分離された領域にＵ字型溝３より浅く設け
たＰ型ベース領域９と、ベース領域９の表面層にベース
領域９を一部残して設けたＮ+ 型ソース領域１０とを含
んでいる。エピタキシャル層５上にはゲート電極７を被
覆するように層間絶縁膜１１を設け、更にその上にソー
ス領域１０およびベース領域９表面とオーミック接触に
より電気的接続するアルミニウムを主金属とするソース
電極１２を設けている。ソース電極１２はその一部を外
部への電気的接続のためのソースパッドとしている。In FIG. 6, reference numeral 1 denotes a semiconductor body, which is an N + type semiconductor substrate 2 which is a high concentration N type, and a U-shaped groove 3 is formed on the surface of the cell portion A in a lattice shape. And an epitaxial layer 5 in which a peripheral groove 4 is formed in a ring shape at a predetermined distance from the peripheral end on the surface of the chip peripheral portion B. First, the cell section A will be described. A gate electrode 7 made of polysilicon is formed via a gate oxide film 6 inside a U-shaped groove 3 formed on the surface of the epitaxial layer 5. The epitaxial layer 5 is an initial layer of the epitaxial layer 5 and has a low concentration of N-type N-.
Drain region 8, a P-type base region 9 provided shallower than the U-shaped groove 3 in a region separated by the U-shaped groove 3 in the surface layer of the drain region 8, and a base region 9 in the surface layer of the base region 9. And an N + type source region 10 provided partially. An interlayer insulating film 11 is provided on the epitaxial layer 5 so as to cover the gate electrode 7, and a source electrode 12 made of aluminum as a main metal and electrically connected to the surfaces of the source region 10 and the base region 9 by ohmic contact. Is provided. Part of the source electrode 12 is used as a source pad for electrical connection to the outside.
【０００４】次に、チップ外周部Ｂについて説明する。
エピタキシャル層５はセル部Ａと共通のドレイン領域８
と、このドレイン領域８表面層のチップ外周端と外周溝
４に挟まれた領域に設けベース領域９と同時に形成され
たＰ型不純物領域１４と、このＰ型不純物領域１４表面
層に設けソース領域１０と同時に設けたＮ+ 型不純物領
域１５とを含んでいる。外周溝４内面にはフィールド酸
化膜１６を設け、このフィールド酸化膜１６上にはフィ
ールド酸化膜１６を被覆するようにセル部Ａと共通の層
間絶縁膜１１を設けている。更にＮ+ 型不純物領域１５
上のスクライブ領域Ｄを除く位置から層間絶縁膜１１上
のチップ外周端から所定距離離間した位置までに跨って
アルミニウムを主金属とするＥＱＲアルミニウム電極１
７を図７に示すようにリング状にソース電極１２と同時
に設けている。尚、図６に示すＥＱＲアルミニウム電極
１７は図７のＢ−Ｂ断面を示したものである。図示しな
いが、ゲート電極７は外部への電気的接続のためのゲー
トパッドに接続されている。Next, the outer peripheral portion B of the chip will be described.
The epitaxial layer 5 has a common drain region 8 with the cell portion A.
A P-type impurity region 14 formed in the surface layer of the drain region 8 between the chip outer peripheral end and the outer peripheral groove 4 and formed simultaneously with the base region 9; and a source region provided in the surface layer of the P-type impurity region 14. 10 and an N @ + -type impurity region 15 provided at the same time. A field oxide film 16 is provided on the inner surface of the outer peripheral groove 4, and an interlayer insulating film 11 common to the cell portion A is provided on the field oxide film 16 so as to cover the field oxide film 16. Further, the N + type impurity region 15
An EQR aluminum electrode 1 made of aluminum as the main metal, extending from a position excluding the upper scribe region D to a position separated by a predetermined distance from a peripheral edge of the chip on the interlayer insulating film 11.
7 is provided simultaneously with the source electrode 12 in a ring shape as shown in FIG. It should be noted that the EQR aluminum electrode 17 shown in FIG. 6 shows the BB section of FIG. Although not shown, the gate electrode 7 is connected to a gate pad for external electrical connection.
【０００５】[0005]
【発明が解決しようとする課題】ところで上記構成のＭ
ＯＳＦＥＴではＥＱＲアルミニウム電極１７をフィール
ド酸化膜１６と層間絶縁膜１１を介して設けているため
ＥＱＲ効果が低く、チャネルストッパとして十分機能さ
せるためＥＱＲアルミニウム電極１７を長くする必要が
あり、その結果チップ外周部面積が大きくなり、チップ
面積も大きくなるという問題がある。ＥＱＲ効果を高く
するためＥＱＲアルミニウム電極を層間絶縁膜を介さず
にフィールド酸化膜のみを介して設けることも考えられ
るが、フィールド酸化膜上を層間絶縁膜で被覆した後に
ＥＱＲアルミニウム電極をＮ+ 型不純物領域に電気的接
続するためにＮ+ 型不純物領域上を露出する製造方法を
使用する場合には、フィールド酸化膜上の層間絶縁膜を
精度良くエッチングすることが難しい。また、ＥＱＲア
ルミニウム電極１７はアルミニウムを主金属としてチッ
プ外周部にリング状に設けており、製品での温度サイク
ル試験で、チップと樹脂間の膨張係数の違いでチップ表
面にストレスが掛かり、材質的に柔らかいアルミが押し
伸ばされたような状態になるアルミスライドと呼ばれる
現象が発生することがある。特にチップのコーナー部に
位置するリング状のＥＱＲアルミニウム電極１７のコー
ナー部はチップ中心部からの距離が４辺の中央部より大
きいためアルミスライドが大きく起こり、隣接するソー
ス電極と接触しソース−ドレイン間ショートが発生する
ことがある。本発明は上記問題点を解決するためにＥＱ
Ｒポリシリコン電極をフィールド酸化膜と層間絶縁膜と
の間に設け、このＥＱＲポリシリコン電極と半導体本体
との電気的接続をＥＱＲアルミニウム電極でとるように
して、ＥＱＲ効果を大きくするとともに、アルミスライ
ド現象によるソース電極とＥＱＲアルミニウム電極との
間のショートを防止した絶縁ゲート型半導体装置および
その製造方法を提供することを目的とする。By the way, M having the above structure
In the OSFET, since the EQR aluminum electrode 17 is provided via the field oxide film 16 and the interlayer insulating film 11, the EQR effect is low, and it is necessary to lengthen the EQR aluminum electrode 17 in order to sufficiently function as a channel stopper. There is a problem that the area of the part increases and the chip area also increases. It is conceivable to provide an EQR aluminum electrode only via a field oxide film without an interlayer insulating film in order to enhance the EQR effect. However, after covering the field oxide film with an interlayer insulating film, the EQR aluminum electrode is replaced with an N + type. When using a manufacturing method that exposes the N + type impurity region to electrically connect to the impurity region, it is difficult to accurately etch the interlayer insulating film on the field oxide film. In addition, the EQR aluminum electrode 17 is provided in a ring shape around the chip with aluminum as a main metal, and in a temperature cycle test on a product, stress is applied to the chip surface due to a difference in expansion coefficient between the chip and the resin. A phenomenon called an aluminum slide, in which soft aluminum is stretched out, may occur. In particular, the corner of the ring-shaped EQR aluminum electrode 17 located at the corner of the chip has a large aluminum slide because the distance from the center of the chip is larger than the center of the four sides, and the source-drain contacts the adjacent source electrode. A short circuit may occur during operation. The present invention provides EQ to solve the above problem.
An R polysilicon electrode is provided between the field oxide film and the interlayer insulating film, and an electrical connection between the EQR polysilicon electrode and the semiconductor body is made by an EQR aluminum electrode, so that the EQR effect is enhanced and an aluminum slide is provided. An object of the present invention is to provide an insulated gate semiconductor device in which a short circuit between a source electrode and an EQR aluminum electrode due to a phenomenon is prevented, and a method of manufacturing the same.
【０００６】[0006]
【課題を解決するための手段】（１）本発明に係る絶縁
ゲート型半導体装置は、セル部にＵ字型溝およびチップ
外周部の外周端から所定距離離間した位置に外周溝が形
成されセル部およびチップ外周部に共通の低濃度一導電
型ドレイン領域を含む半導体本体を具備し、セル部にお
いて、前記半導体本体に含まれ前記ドレイン領域の表面
層で前記Ｕ字型溝に分離された領域に設けた他導電型ベ
ース領域と、このベース領域の表面層に設けた高濃度一
導電型ソース領域と、前記Ｕ字型溝の内面に設けたゲー
ト酸化膜と、前記Ｕ字型溝にゲート酸化膜を介して設け
たポリシリコンからなるゲート電極と、このゲート電極
と層間絶縁膜で絶縁し前記ベース領域およびソース領域
に電気的接続したアルミニウムを主金属とするソース電
極とを具備し、チップ外周部において、前記半導体本体
に含まれ前記ドレイン領域の表面層でチップ外周端と前
記外周溝間に挟まれた領域に設けた他導電型不純物領域
と、この他導電型不純物領域の表面層に設けた高濃度一
導電型不純物領域と、前記外周溝内に設けたフィールド
酸化膜と、このフィールド酸化膜上と前記層間絶縁膜下
間に所定長で前記高濃度一導電型不純物領域上に跨って
リング状に設けたポリシリコンからなるＥＱＲポリシリ
コン電極と、このＥＱＲポリシリコン電極のチップ外周
端側の端部および前記高濃度一導電型不純物領域に電気
的接続したアルミニウムを主金属とするＥＱＲアルミニ
ウム電極とを具備している。上記手段によれば、ＥＱＲ
ポリシリコン電極を外周溝内に設けたフィールド酸化膜
と層間絶縁膜下との間に設け、ＥＱＲポリシリコン電極
と高濃度一導電型型不純物領域との電気的接続をＥＱＲ
アルミニウム電極によりとっているので、従来のＥＱＲ
アルミニウム電極だけの場合のようにフィールド酸化膜
＋層間絶縁膜上にＥＱＲアルミニウム電極を設けた場合
よりＥＱＲ効果を高くできるとともに、従来のＥＱＲア
ルミニウム電極だけの場合よりＥＱＲアルミニウム電極
とソース電極との離間距離を大きくとれ、更にソース電
極とＥＱＲポリシリコン電極間は段差があり、かつ、層
間絶縁膜により分離されているため、温度サイクル試験
で発生するアルミスライドによるソース電極とＥＱＲア
ルミニウム電極とのショートを防止できる。 （２）本発明に係る絶縁ゲート型半導体装置は（１）に
おいて、前記ＥＱＲアルミニウム電極が方形チップのコ
ーナー部を除いて設けられている。上記手段によれば、
特に、ＥＱＲアルミニウム電極をリング状にするのでは
なく、チップのコーナー部に設けないようにしたので、
アルミスライドが大きく起こりやすいコーナー部でのソ
ース電極とＥＱＲアルミニウム電極とのショートを完全
に防止できる。 （３）本発明に係る絶縁ゲート型半導体装置は（２）に
おいて、前記ＥＱＲアルミニウム電極が方形チップの４
辺の各中央部４個所に設けられている。上記手段によれ
ば、前記ＥＱＲアルミニウム電極は方形チップの４辺の
各中央部４個所に設けることによりＥＱＲポリシリコン
電極と高濃度一導電型型不純物領域との電気的接続をと
ることができる。 （４）本発明に係る絶縁ゲート型半導体装置は（１）に
おいて、前記ＥＱＲアルミニウム電極がリング状に設け
られている。上記手段によれば、（２）よりはチップの
コーナー部でのアルミスライドに対して少し不利になる
が従来のＥＱＲアルミニウム電極だけの場合よりはソー
ス電極とＥＱＲアルミニウム電極とのショートをより防
止できる。 （５）本発明に係る絶縁ゲート型半導体装置は（１）に
おいて、前記ＥＱＲポリシリコン電極が前記ゲート電極
と同時に設けられている。 （６）本発明に係る絶縁ゲート型半導体装置は（１）に
おいて、前記半導体本体が半導体基板上に形成されたエ
ピタキシャル層である。 （７）本発明に係る絶縁ゲート型半導体装置は（６）に
おいて、前記半導体基板が高濃度一導電型である。 （８）本発明に係る絶縁ゲート型半導体装置は（６）に
おいて、前記半導体基板が高濃度他導電型である。 （９）本発明に係る絶縁ゲート型半導体装置の製造方法
は、ドレイン領域となる低濃度一導電型半導体層を表面
側に含む半導体本体上にシリコン酸化膜とシリコン窒化
膜を順次形成した後、エッチングにより半導体本体表面
のセル部に初期溝とチップ外周部の外周端から所定距離
離間した位置に外周初期溝とを形成する第１工程と、第
１工程完了後、前記シリコン窒化膜をマスクに前記初期
溝および外周初期溝の内面にＬＯＣＯＳ酸化膜を形成す
ることより初期溝がＵ字型溝および外周初期溝が外周溝
に形状変形され、このＬＯＣＯＳ酸化膜をマスクに、セ
ル部において、前記半導体層の表面層の前記Ｕ字型溝に
分離された領域に他導電型ベース領域を形成するととも
にこのベース領域の表面層に高濃度一導電型ソース領域
を形成し、チップ外周部において、前記半導体層の表面
層のチップ外周端と前記外周溝に挟まれた領域に他導電
型不純物領域を形成するとともにこの他導電型不純物領
域の表面層に高濃度一導電型不純物領域を形成する第２
工程と、第２工程完了後、前記Ｕ字型溝のＬＯＣＯＳ酸
化膜を除去するとともに前記外周溝のＬＯＣＯＳ酸化膜
をフィールド酸化膜として残す第３工程と、第３工程完
了後、Ｕ字型溝内面を含む露出した半導体本体表面にゲ
ート酸化膜を形成した後、その上からポリシリコン膜を
被覆する第４工程と、第４工程完了後、ポリシリコン膜
をエッチングして、セル部において、前記ソース領域表
面の一部およびＵ字型溝のポリシリコン膜を残してゲー
ト電極を形成し、チップ外周部において、前記フィール
ド酸化膜上に所定長で前記高濃度一導電型不純物領域上
の一部に跨ってリング状にポリシリコン膜を残してＥＱ
Ｒポリシリコン電極を形成し、その上から層間絶縁膜を
被覆する第５工程と、第５工程完了後、前記層間絶縁膜
およびゲート酸化膜をエッチングして、セル部におい
て、前記ソース領域表面の一部およびベース領域表面を
露出し、チップ外周部において、前記高濃度一導電型不
純物領域表面を露出するとともに、前記ＥＱＲポリシリ
コン電極表面のチップ外周端側の端部を露出して後、そ
の上からアルミニウム膜を被覆し、このアルミニウム膜
をエッチングして、セル部において前記ベース領域およ
びソース領域と電気的に接続するソース電極を形成し、
チップ外周部において、前記ＥＱＲポリシリコン電極の
チップ外周端側の端部および前記高濃度一導電型不純物
領域に電気的接続したアルミニウムを主金属とするＥＱ
Ｒアルミニウム電極を形成する第６工程とを有する。上
記手段によれば、ＥＱＲポリシリコン電極をゲート電極
と同時に形成することにより、従来のＥＱＲアルミニウ
ム電極だけの場合と同じ工程数で製造できる。(1) In an insulated gate semiconductor device according to the present invention, a cell portion has a U-shaped groove and an outer peripheral groove formed at a predetermined distance from an outer peripheral end of an outer peripheral portion of a chip. A semiconductor body including a low-concentration one-conductivity-type drain region common to a portion and an outer peripheral portion of the chip, and a region included in the semiconductor body and separated by the U-shaped groove in a surface layer of the drain region in the cell portion. And a high-concentration one-conductivity-type source region provided in a surface layer of the base region, a gate oxide film provided on an inner surface of the U-shaped groove, and a gate formed in the U-shaped groove. A gate electrode made of polysilicon provided through an oxide film, and a source electrode mainly composed of aluminum insulated from the gate electrode by an interlayer insulating film and electrically connected to the base region and the source region. A second conductive type impurity region provided in a region between the outer circumferential end of the chip and the outer circumferential groove in a surface layer of the drain region, which is included in the semiconductor body, and a surface layer of the other conductive type impurity region, A high-concentration one-conductivity-type impurity region, a field oxide film provided in the outer peripheral groove, and a predetermined length on the high-concentration one-conductivity-type impurity region between the field oxide film and the interlayer insulating film. The main metal is an EQR polysilicon electrode made of polysilicon which is provided in a ring shape over the straddle, and aluminum which is electrically connected to the end of the EQR polysilicon electrode on the chip outer peripheral end side and the high concentration one conductivity type impurity region. And an EQR aluminum electrode. According to the above means, the EQR
A polysilicon electrode is provided between the field oxide film provided in the outer peripheral groove and under the interlayer insulating film, and an electrical connection between the EQR polysilicon electrode and the high-concentration one-conductivity-type impurity region is provided by EQR.
Conventional EQR because it uses aluminum electrodes
The EQR effect can be enhanced as compared with the case where the EQR aluminum electrode is provided on the field oxide film + interlayer insulating film as in the case of only the aluminum electrode, and the distance between the EQR aluminum electrode and the source electrode can be increased as compared with the case where only the conventional EQR aluminum electrode is used alone. The distance between the source electrode and the EQR polysilicon electrode is large, and there is a step between them. Also, the source electrode and the EQR polysilicon electrode are separated by an interlayer insulating film. Can be prevented. (2) In the insulated gate semiconductor device according to the present invention, in (1), the EQR aluminum electrode is provided except for a corner of a rectangular chip. According to the above means,
In particular, since the EQR aluminum electrode was not provided in the corner of the chip instead of being formed in a ring shape,
It is possible to completely prevent a short circuit between the source electrode and the EQR aluminum electrode at a corner where an aluminum slide easily occurs. (3) In the insulated gate semiconductor device according to the present invention, in (2), the EQR aluminum electrode is a square chip 4
It is provided at each of the four central portions of the side. According to the above means, the EQR aluminum electrode is provided at each of the four central portions of the four sides of the rectangular chip so that the EQR polysilicon electrode can be electrically connected to the high-concentration one-conductivity-type impurity region. (4) In the insulated gate semiconductor device according to the present invention, in (1), the EQR aluminum electrode is provided in a ring shape. According to the above-mentioned means, although it is slightly disadvantageous to the aluminum slide at the corner of the chip than in (2), a short circuit between the source electrode and the EQR aluminum electrode can be prevented more than in the case of using only the conventional EQR aluminum electrode. . (5) In the insulated gate semiconductor device according to the present invention, in (1), the EQR polysilicon electrode is provided simultaneously with the gate electrode. (6) In the insulated gate semiconductor device according to the present invention, in (1), the semiconductor body is an epitaxial layer formed on a semiconductor substrate. (7) In the insulated gate semiconductor device according to the present invention, in (6), the semiconductor substrate is a high concentration one conductivity type. (8) In the insulated gate semiconductor device according to the present invention, in (6), the semiconductor substrate is of a high concentration other conductivity type. (9) In the method of manufacturing an insulated gate semiconductor device according to the present invention, after a silicon oxide film and a silicon nitride film are sequentially formed on a semiconductor body including a low-concentration one-conductivity-type semiconductor layer serving as a drain region on a surface side, A first step of forming an initial groove in the cell portion on the surface of the semiconductor body by etching and an outer peripheral initial groove at a position separated by a predetermined distance from the outer peripheral end of the chip outer peripheral portion; and after the first step is completed, using the silicon nitride film as a mask. By forming a LOCOS oxide film on the inner surface of the initial groove and the outer peripheral initial groove, the initial groove is deformed into a U-shaped groove and the outer peripheral initial groove into an outer peripheral groove. Using the LOCOS oxide film as a mask, Forming a base region of another conductivity type in a region separated by the U-shaped groove in a surface layer of the semiconductor layer, and forming a high-concentration one conductivity type source region in a surface layer of the base region; In the peripheral portion, an impurity region of another conductivity type is formed in a region between the chip outer peripheral end of the surface layer of the semiconductor layer and the outer circumferential groove, and a high-concentration one conductivity type impurity region is formed in a surface layer of the impurity region of the other conductivity type. Forming a second
After the completion of the second step, the third step of removing the LOCOS oxide film of the U-shaped groove and leaving the LOCOS oxide film of the outer peripheral groove as a field oxide film, and after the completion of the third step, the U-shaped groove Forming a gate oxide film on the exposed surface of the semiconductor body including the inner surface, covering the polysilicon film from above, and etching the polysilicon film after completion of the fourth step; A gate electrode is formed while leaving a part of the source region surface and the polysilicon film of the U-shaped groove, and a part of the high-concentration one-conductivity-type impurity region having a predetermined length on the field oxide film at a chip outer peripheral portion. Leave the polysilicon film in a ring shape across the EQ
A fifth step of forming an R-polysilicon electrode and covering the interlayer insulating film from above, and after the completion of the fifth step, etching the interlayer insulating film and the gate oxide film to form a cell surface portion of the source region surface; After exposing the surface of the part and the base region, and exposing the surface of the high-concentration one-conductivity-type impurity region at the chip outer periphery, and exposing the end of the EQR polysilicon electrode surface on the chip outer peripheral end side, An aluminum film is coated from above, and the aluminum film is etched to form a source electrode electrically connected to the base region and the source region in a cell portion,
In a chip outer peripheral portion, an EQ mainly composed of aluminum electrically connected to an end portion of the EQR polysilicon electrode on the chip outer peripheral end side and the high-concentration one-conductivity-type impurity region.
A sixth step of forming an R aluminum electrode. According to the above means, by forming the EQR polysilicon electrode at the same time as the gate electrode, it can be manufactured in the same number of steps as in the case of the conventional EQR aluminum electrode alone.
【０００７】[0007]
【発明の実施の形態】以下に、本発明に基づき１実施例
のＮチャネル型ＭＯＳＦＥＴおよびその製造方法を図１
乃至図４を参照して説明する。まず、構成を説明する
と、図１において、２１は半導体本体で、基板表面の結
晶面が（１００）面の高濃度一導電型であるＮ+ 型半導
体基板２２と、この半導体基板２２上に設け、セル部Ａ
表面にＵ字型溝２３が格子状に形成されるとともにチッ
プ外周部Ｂ表面に外周端から所定距離離間して外周溝２
４がリング状に形成されたエピタキシャル層２５とを有
している。まず、セル部Ａについて説明する。エピタキ
シャル層２５表面に形成されたＵ字型溝２３の内部にゲ
ート酸化膜２６を介してポリシリコンからなるゲート電
極２７が形成されている。エピタキシャル層２５はエピ
タキシャル層２５の初期層であり低濃度Ｎ型であるＮ-
型ドレイン領域２８と、このドレイン領域２８表面層の
Ｕ字型溝２３により分離された領域にＵ字型溝２３より
浅く設けた他導電型であるＰ型ベース領域２９と、ベー
ス領域２９の表面層にベース領域２９を一部残して設け
たＮ+ 型ソース領域３０とを含んでいる。エピタキシャ
ル層２５表面のＵ字型溝２３により分離された各領域の
平面的な構造は図２に示すように、ソース領域３０は全
体が略正方形であり、且つ、所定の一定幅で離隔した非
環状の略４等分に分割された略３角形の４分割ソース領
域３０ａであり、ベース領域２９は４分割ソース領域３
０ａ間の幅狭なソース分割ベース領域２９ａである。エ
ピタキシャル層２５上にはゲート電極２７を被覆するよ
うに層間絶縁膜３１を設け、更にその上にソース領域３
０およびベース領域２９表面とオーミック接触により電
気的接続するアルミニウムを主金属とするソース電極３
２を設けている。ソース電極３２はその一部を外部への
電気的接続のためのソースパッドとしている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An N-channel MOSFET according to one embodiment of the present invention and a method of manufacturing the same will now be described with reference to FIG.
This will be described with reference to FIGS. First, the structure will be described. In FIG. 1, reference numeral 21 denotes a semiconductor body, which is an N + -type semiconductor substrate 22 of a high-concentration one conductivity type having a (100) crystal plane on a substrate surface, and provided on the semiconductor substrate 22. , Cell part A
A U-shaped groove 23 is formed in a lattice shape on the surface, and the outer peripheral groove 2 is spaced from the outer peripheral end by a predetermined distance on the surface of the chip outer peripheral portion B.
4 has an epitaxial layer 25 formed in a ring shape. First, the cell section A will be described. A gate electrode 27 made of polysilicon is formed inside a U-shaped groove 23 formed on the surface of the epitaxial layer 25 via a gate oxide film 26. The epitaxial layer 25 is an initial layer of the epitaxial layer 25 and has a low concentration of N-type N-.
Drain region 28, a P-type base region 29 of another conductivity type provided shallower than U-shaped groove 23 in a region separated by U-shaped groove 23 in the surface layer of drain region 28, and a surface of base region 29. And an N + type source region 30 provided with a part of the base region 29 left in the layer. As shown in FIG. 2, the planar structure of each region separated by the U-shaped groove 23 on the surface of the epitaxial layer 25 is such that the source region 30 is substantially square in its entirety and is separated by a predetermined constant width. The base region 29 is a quadrilateral source region 30a, which is a substantially triangular quadrilateral source region 30a which is divided into four substantially equal parts.
This is a narrow source division base region 29a between 0a. An interlayer insulating film 31 is provided on the epitaxial layer 25 so as to cover the gate electrode 27, and the source region 3 is further formed thereon.
Source electrode 3 made of aluminum as a main metal electrically connected to the surface of O and base region 29 by ohmic contact
2 are provided. Part of the source electrode 32 is used as a source pad for external electrical connection.
【０００８】次に、チップ外周部Ｂについて説明する。
エピタキシャル層２５はセル部Ａと共通のドレイン領域
２８と、このドレイン領域２８表面層のチップ外周端と
外周溝２４に挟まれた領域に設けベース領域２９と同時
に形成されたＰ型不純物領域３４と、このＰ型不純物領
域３４表面層に設けソース領域３０と同時に設けたＮ+
型不純物領域３５とを含んでいる。外周溝２４内面には
フィールド酸化膜３６を設け、このフィールド酸化膜３
６上のチップ外周端から所定距離離間した位置からＮ+
型不純物領域３５上のゲート酸化膜２６を介した一部に
跨ってポリシリコンからなるＥＱＲポリシリコン電極３
７を図３に示すようにリング状にゲート電極７と同時に
設けている。更にＮ+ 型不純物領域３５上のスクライブ
領域Ｄを除く位置、ＥＱＲポリシリコン電極３７上およ
びフィールド酸化膜３６上に、ＥＱＲポリシリコン電極
３７のチップ外周端側の端部およびＮ+ 型不純物領域３
５の一部を除いて、セル部Ａと共通の層間絶縁膜３１を
設け、このＥＱＲポリシリコン電極３７上のチップ外周
端側の端部およびＮ+ 型不純物領域３５の一部上と層間
絶縁膜３１上のＥＱＲポリシリコン電極３７のチップ内
側端よりチップ外周端側の位置にアルミニウムを主金属
とするＥＱＲアルミニウム電極３８を図３に示すように
チップのコーナー部には設けず、チップ４辺の各中央部
４個所に分散してソース電極１２と同時に設けている。
尚、図１に示すＥＱＲポリシリコン電極３７およびＥＱ
Ｒアルミニウム電極３８は図３のＡ−Ａ断面を示したも
のである。図示しないが、ゲート電極２７は外部への電
気的接続のためのゲートパッドに接続されている。Next, the outer peripheral portion B of the chip will be described.
The epitaxial layer 25 has a drain region 28 common to the cell portion A, and a P-type impurity region 34 formed at the same time as the base region 29 provided in a region between the chip outer peripheral end and the outer peripheral groove 24 on the surface layer of the drain region 28. N + provided on the surface layer of P-type impurity region 34 and provided simultaneously with source region 30.
And a type impurity region 35. A field oxide film 36 is provided on the inner surface of the outer peripheral groove 24.
N + from a position separated by a predetermined distance from the outer edge of the chip on
Polysilicon electrode 3 made of polysilicon over a part of gate impurity film 35 over gate oxide film 26
7, is provided simultaneously with the gate electrode 7 in a ring shape as shown in FIG. Further, on the N + -type impurity region 35 except for the scribe region D, on the EQR polysilicon electrode 37 and the field oxide film 36, the end of the EQR polysilicon electrode 37 on the chip outer peripheral side and the N + -type impurity region 3
5 is provided with an interlayer insulating film 31 common to the cell portion A, and an interlayer insulating film 31 on the end of the EQR polysilicon electrode 37 on the chip outer peripheral side and a portion of the N @ + -type impurity region 35. As shown in FIG. 3, an EQR aluminum electrode 38 made of aluminum as a main metal is not provided at the corner of the chip at a position on the outer peripheral end side of the chip than the inner end of the chip of the EQR polysilicon electrode 37 on the film 31, and the four sides of the chip are provided. Are distributed and provided at the same time as the source electrode 12 at four central portions.
The EQR polysilicon electrode 37 and the EQR shown in FIG.
The R aluminum electrode 38 shows the AA cross section of FIG. Although not shown, the gate electrode 27 is connected to a gate pad for external electrical connection.
【０００９】上記構成によれば、ＥＱＲポリシリコン電
極３７をフィールド酸化膜３６と層間絶縁膜３１との間
に設け、ＥＱＲポリシリコン電極３７とＮ+ 型不純物領
域３５との電気的接続をチップ４辺の各中央部４個所に
分散して設けたＥＱＲアルミニウム電極３８によりとっ
ているので、従来のＥＱＲアルミニウム電極だけの場合
のようにフィールド酸化膜＋層間絶縁膜上にＥＱＲアル
ミニウム電極を設けた場合よりＥＱＲ効果を高くできる
のでＥＱＲポリシリコン電極３７を短くでき、チップ面
積を縮小することができるとともに、従来のＥＱＲアル
ミニウム電極だけの場合よりＥＱＲアルミニウム電極３
８とソース電極３２との離間距離を大きくとれ、更にＥ
ＱＲポリシリコン電極３７は外周溝２４内に形成したフ
ィールド酸化膜３６上で、かつ、層間絶縁膜３１の下に
設けられており、ソース電極３２とＥＱＲポリシリコン
電極間は段差があり、かつ、層間絶縁膜により分離され
ているため、温度サイクル試験で発生するアルミスライ
ドによるソース電極とＥＱＲアルミニウム電極とのショ
ートを防止でき、信頼性を高くすることができる。特
に、ＥＱＲアルミニウム電極３８をリング状にするので
はなく、チップのコーナー部に設けないようにしたの
で、アルミスライドが大きく起こりやすいコーナー部で
のソース電極とＥＱＲアルミニウム電極とのショートを
防止でき、信頼性を高くすることができる。According to the above structure, the EQR polysilicon electrode 37 is provided between the field oxide film 36 and the interlayer insulating film 31, and the electrical connection between the EQR polysilicon electrode 37 and the N + -type impurity region 35 is formed by the chip 4. Since it is taken by the EQR aluminum electrodes 38 dispersedly provided at four places at the center of each side, when the EQR aluminum electrode is provided on the field oxide film + interlayer insulating film as in the case of only the conventional EQR aluminum electrode. Since the EQR effect can be further enhanced, the EQR polysilicon electrode 37 can be shortened, the chip area can be reduced, and the EQR aluminum electrode 3 can be reduced as compared with the conventional case using only the EQR aluminum electrode.
8 and the source electrode 32 can be made large, and E
The QR polysilicon electrode 37 is provided on the field oxide film 36 formed in the outer peripheral groove 24 and below the interlayer insulating film 31. There is a step between the source electrode 32 and the EQR polysilicon electrode, and Since they are separated by the interlayer insulating film, a short circuit between the source electrode and the EQR aluminum electrode due to the aluminum slide generated in the temperature cycle test can be prevented, and the reliability can be increased. In particular, since the EQR aluminum electrode 38 is not provided in a corner portion of the chip, instead of being formed in a ring shape, it is possible to prevent a short circuit between the source electrode and the EQR aluminum electrode at the corner portion where aluminum sliding is likely to occur, Reliability can be increased.
【００１０】次に製造方法を図５（ａ）〜（ｅ）と図１
を参照して説明する。先ず、第１工程はこの工程の完了
後を図５（ａ）に示すように、基板表面の結晶面が（１
００）面でオリエーテーションフラットの結晶面が｛１
００｝面のＮ+ 型半導体基板２２上にＮ- 型のエピタキ
シャル初期層を形成した後、この初期層の表面に熱酸化
法によりシリコン酸化膜５３を膜厚５００Å程度に形成
し、更にその上にシリコン窒化膜５４をＣＶＤ法により
膜厚９００Å程度に成長させた後、フォトリソグラフィ
法およびドライエッチ法により選択的に窒化膜５４、酸
化膜５３およびエピタキシャル層をエッチングしてセル
部Ａに初期溝５５が格子状に形成されるとともに、チッ
プ外周部Ｂのチップ外周端から所定距離離間した位置よ
り内側に外周初期溝５６がリング状に形成されたエピタ
キシャル層２５ａを形成する。初期溝５５は側壁面の結
晶面が｛１００｝面に対し０〜３０度の範囲内になるよ
うにエッチングし、深さを例えば、１．３μｍねらいで
エッチングして形成される。尚、初期溝５５の深さは
１．３μｍねらい以外でもよい。酸化膜５３は後工程で
のＬＯＣＯＳ酸化時の窒化膜５４による応力の緩衝膜と
して形成され、膜厚が厚いほうが応力が緩和されると同
時に溝肩部の曲率半径も大きくなるので、曲率半径が適
正値となるような膜厚としている。また、窒化膜５４は
後工程でのＬＯＣＯＳ酸化時のマスクとして形成され、
膜厚が薄いほうが窒化膜５４自身による応力を低減する
と同時に溝肩部の曲率半径も大きくなるが、逆に膜厚が
薄いことによる窒化膜５４の損傷や窒化膜５４を酸素が
通り抜ける等の工程上の不具合が発生するので、工程上
の不具合が発生せず曲率半径が適正値となるような膜厚
としている。Next, the manufacturing method will be described with reference to FIGS.
This will be described with reference to FIG. First, in the first step, after the completion of this step, as shown in FIG.
The crystal plane of the orientation flat on the (00) plane is $ 1
After an N- type epitaxial initial layer is formed on the N + type semiconductor substrate 22 on the 00 ° plane, a silicon oxide film 53 is formed on the surface of the initial layer by thermal oxidation to a thickness of about 500 °, and further thereon. After growing a silicon nitride film 54 to a thickness of about 900 ° by the CVD method, the nitride film 54, the oxide film 53 and the epitaxial layer are selectively etched by the photolithography method and the dry etching method to form an initial groove in the cell portion A. 55 is formed in a lattice shape, and an epitaxial layer 25a is formed in which a peripheral initial groove 56 is formed in a ring shape inside a position at a predetermined distance from the chip outer peripheral end of the chip outer peripheral portion B. The initial groove 55 is formed by etching such that the crystal plane of the side wall surface is in the range of 0 to 30 degrees with respect to the {100} plane, and is etched at a depth of, for example, 1.3 μm. Note that the depth of the initial groove 55 may be other than 1.3 μm. The oxide film 53 is formed as a buffer film for the stress caused by the nitride film 54 at the time of LOCOS oxidation in a later process. The larger the film thickness is, the more the stress is relieved and the larger the radius of curvature of the groove shoulder becomes. The film thickness is set to an appropriate value. Further, the nitride film 54 is formed as a mask at the time of LOCOS oxidation in a later process,
A thinner film reduces the stress caused by the nitride film 54 itself, and at the same time, increases the radius of curvature of the groove shoulder. On the other hand, a process such as damage to the nitride film 54 due to the thin film thickness and oxygen passing through the nitride film 54 are performed. Since the above problems occur, the film thickness is set such that the process radius does not occur and the radius of curvature becomes an appropriate value.
【００１１】次に、第２工程はこの工程の完了後を図５
（ｂ）に示すように、第１工程完了後、窒化膜５４をマ
スクとして初期溝５５、５６の内面を酸化温度１１４０
℃程度で熱酸化して膜厚７０００Å程度のＬＯＣＯＳ酸
化膜５７を形成すると、初期溝５５がＵ字型溝２３、外
周初期溝５６が外周溝２４に形状変形される。ＬＯＣＯ
Ｓ酸化膜５７の形成温度は酸化膜５７の粘性を高くして
応力を低減するように設定している。溝肩部の曲率半径
は適正値０．２〜０．７μｍとなる。Ｕ字型溝２３の側
壁面は結晶面が｛１００｝面に対して０〜３０度の範囲
内で形成される。その後、窒化膜５４および酸化膜５３
をウェットエッチ法により全面除去し、熱酸化法により
イオン注入のためのシリコン酸化膜５８を膜厚１００Å
程度に形成して後、ＬＯＣＯＳ酸化膜５７をマスクにし
てシリコン酸化膜５８を介してホウ素をイオン注入およ
び熱拡散してＵ字型溝２３の深さより浅く、Ｕ字型溝２
３により分離された領域にＰ型ベース領域２９を形成す
るとともにチップ外周端と外周溝２４に挟まれた領域に
Ｐ型不純物領域３４を形成する。尚、この後、図示しな
いがフォトリソグラフィ法でのレジストパターンでマス
クしてホウ素または弗化ホウ素をイオン注入しフォトレ
ジスト膜除去後に熱拡散してベース領域２９表面層に含
まれるＰ+ 型コンタクトベース領域を形成する。さら
に、ＬＯＣＯＳ酸化膜５７をマスクにするとともにベー
ス領域２９上をフォトリソグラフィ法でのレジストパタ
ーンでマスクして砒素またはリンをイオン注入しフォト
レジスト膜除去後に熱拡散してベース領域２９表面層に
Ｎ+ 型ソース領域３０を形成するとともにＰ型不純物領
域３４表面層全面にＮ+ 型不純物領域３５を形成する。
この結果、図５（ａ）のエピタキシャル層２５ａは、表
面に溝２３，２４が形成されエピタキシャル層の初期層
であるＮ- 型ドレイン領域２８と、ベース領域２９と、
ソース領域３０と、Ｐ型不純物領域３４と、Ｎ+ 型不純
物領域３５とを含むエピタキシャル層２５となる。Next, in a second step, FIG.
As shown in (b), after completion of the first step, the inner surfaces of the initial grooves 55 and 56 are exposed to an oxidation temperature 1140 using the nitride film 54 as a mask.
When the LOCOS oxide film 57 having a thickness of about 7000 ° is formed by thermal oxidation at about ℃, the initial groove 55 is deformed into the U-shaped groove 23 and the outer peripheral initial groove 56 is deformed into the outer peripheral groove 24. LOCO
The formation temperature of the S oxide film 57 is set so as to increase the viscosity of the oxide film 57 and reduce the stress. The radius of curvature of the groove shoulder is an appropriate value of 0.2 to 0.7 μm. The side wall surface of U-shaped groove 23 has a crystal plane formed within a range of 0 to 30 degrees with respect to the {100} plane. Thereafter, the nitride film 54 and the oxide film 53
Is entirely removed by wet etching, and a silicon oxide film 58 for ion implantation is formed to a thickness of 100 .ANG. By thermal oxidation.
Then, boron is ion-implanted and thermally diffused through the silicon oxide film 58 using the LOCOS oxide film 57 as a mask, so that the depth is smaller than the depth of the U-shaped groove 23.
The P-type base region 29 is formed in the region separated by 3 and the P-type impurity region 34 is formed in the region between the outer peripheral edge of the chip and the outer peripheral groove 24. After that, although not shown, boron or boron fluoride is ion-implanted by masking with a resist pattern by a photolithography method, the photoresist film is removed, and then heat diffusion is performed to remove the P + type contact base contained in the surface layer of the base region 29. Form an area. Further, arsenic or phosphorus is ion-implanted by using the LOCOS oxide film 57 as a mask and the base region 29 is masked with a resist pattern by a photolithography method, and the photoresist film is removed. A source region 30 is formed, and an impurity region 35 is formed over the entire surface layer of the p-type impurity region 34.
As a result, the epitaxial layer 25a of FIG. 5A has grooves 23 and 24 formed on the surface thereof, an N − -type drain region 28 which is an initial layer of the epitaxial layer, a base region 29, and
The epitaxial layer 25 includes the source region 30, the P-type impurity region 34, and the N + -type impurity region 35.
【００１２】次に、第３工程はこの工程の完了後を図５
（ｃ）に示すように、第２工程完了後、溝２４内のＬＯ
ＣＯＳ酸化膜５７をフォトリソグラフィ法でのレジスト
パターン５９でマスクしウェットエッチ法により溝２３
内のＬＯＣＯＳ酸化膜５７とベース領域２９、ソース領
域３０およびＮ+ 型不純物領域３５上の酸化膜５８を除
去することによりベース領域２９、ソース領域３０およ
びＮ+ 型不純物領域３５の表面と溝２３の内面を露出さ
せ、外周溝２４に形成されたＬＯＣＯＳ酸化膜５７をフ
ィールド酸化膜３６として残す。Next, a third step is a step after completion of this step in FIG.
After completion of the second step, as shown in FIG.
The COS oxide film 57 is masked with a resist pattern 59 by photolithography, and the groove 23 is wet-etched.
By removing the LOCOS oxide film 57 and the oxide film 58 on the base region 29, the source region 30 and the N + type impurity region 35 therein, the surface of the base region 29, the source region 30 and the N + type impurity region 35 and the groove 23 are removed. Is exposed, leaving the LOCOS oxide film 57 formed in the outer peripheral groove 24 as the field oxide film 36.
【００１３】次に、第４工程はこの工程の完了後を図５
（ｄ）に示すように、第３工程完了後、ベース領域２
９、ソース領域３０およびＮ+ 型不純物領域３５の表面
と溝２３の内面に熱酸化法によりゲート酸化膜２６を形
成する。ゲート酸化膜２６の膜厚は、例えば、溝２３の
内面のベース領域２９上で５００Å程度に形成される。
以上の工程を経たエピタキシャル層２５の表面をＣＶＤ
法によりポリシリコン膜６０で被覆する。Next, in a fourth step, FIG.
After completion of the third step, as shown in FIG.
9. A gate oxide film 26 is formed on the surface of the source region 30 and the N @ + -type impurity region 35 and on the inner surface of the groove 23 by a thermal oxidation method. The gate oxide film 26 is formed to a thickness of, for example, about 500 ° on the base region 29 on the inner surface of the groove 23.
The surface of the epitaxial layer 25 having undergone the above steps is
It is covered with a polysilicon film 60 by a method.
【００１４】次に、第５工程はこの工程の完了後を図５
（ｅ）に示すように、第４工程完了後、フォトリソグラ
フィ法およびドライエッチ法により、セル部Ａにおいて
ソース領域３０表面の一部および溝２３のポリシリコン
膜６０を残してゲート電極２７を形成するとともに、チ
ップ外周部Ｂにおいてフィールド酸化膜３６上に所定長
でＮ+ 型不純物領域３５上のゲート酸化膜２６を介した
一部に跨ってリング状にポリシリコン膜６０を残してＥ
ＱＲポリシリコン電極３７を形成した後、以上の工程を
経たエピタキシャル層２５の表面をＣＶＤ法により層間
絶縁膜３１で被覆する。Next, in a fifth step, the completion of this step is shown in FIG.
As shown in (e), after completion of the fourth step, a gate electrode 27 is formed by photolithography and dry etching, leaving a part of the surface of the source region 30 and the polysilicon film 60 in the groove 23 in the cell part A. At the same time, the polysilicon film 60 is left in a ring shape over the field oxide film 36 over the part of the N + type impurity region 35 via the gate oxide film 26 on the field oxide film 36 at the chip outer peripheral portion B.
After the formation of the QR polysilicon electrode 37, the surface of the epitaxial layer 25 that has undergone the above steps is covered with the interlayer insulating film 31 by the CVD method.
【００１５】次に、第６工程はこの工程の完了後を図１
に示すように、第５工程完了後、セル部Ａにおいてソー
ス領域３０表面の一部およびベース領域２９表面が露出
するように層間絶縁膜３１およびゲート酸化膜２６にコ
ンタクト窓を形成するとともに、チップ外周部Ｂにおい
てＮ+ 型不純物領域３５のスクライブ領域Ｄの層間絶縁
膜３１およびゲート酸化膜２６を除去するとともに、Ｅ
ＱＲポリシリコン電極３７表面のチップ外周端側の端部
およびＮ+ 型不純物領域３５上がチップ４辺の各中央部
４個所で部分的に露出するように層間絶縁膜３１および
ゲート酸化膜２６を除去する。以上の工程を経たエピタ
キシャル層２５の表面をスパッタ法によりアルミニウム
膜で被覆し、このアルミニウム膜をフォトリソグラフィ
法およびドライエッチ法により選択的に除去して、セル
部Ａにおいてベース領域２９およびソース領域３０とオ
ーミック接触により電気的に接続するソース電極３２
と、チップ外周部ＢにおいてＥＱＲポリシリコン電極３
７上のチップ外周端側の端部およびＮ+ 型不純物領域３
５の上記部分的に露出した表面から層間絶縁膜３１上の
ＥＱＲポリシリコン電極３７のチップ内側端よりチップ
外周端側の位置にアルミニウムを主金属とするＥＱＲア
ルミニウム電極３８を図３に示すようにチップのコーナ
ー部を除く４辺の各中央部４個所に分散して形成する。
図示しないが、ゲート電極２７から外部に電気的に接続
するためのゲートパッドが同時形成され、ソース電極３
２はその一部を外部への電気的接続のためのソースパッ
ドとしている。Next, a sixth step is shown in FIG. 1 after the completion of this step.
After completion of the fifth step, contact windows are formed in the interlayer insulating film 31 and the gate oxide film 26 so that a part of the surface of the source region 30 and the surface of the base region 29 are exposed in the cell portion A, and the chip In the outer peripheral portion B, the interlayer insulating film 31 and the gate oxide film 26 in the scribe region D of the N + -type impurity region 35 are removed and
The interlayer insulating film 31 and the gate oxide film 26 are so formed that the end of the surface of the QR polysilicon electrode 37 on the outer peripheral end side of the chip and the N + -type impurity region 35 are partially exposed at four central portions of the four sides of the chip. Remove. The surface of the epitaxial layer 25 having undergone the above steps is covered with an aluminum film by sputtering, and this aluminum film is selectively removed by photolithography and dry etching, so that the base region 29 and the source region 30 are formed in the cell portion A. Electrode 32 electrically connected to the source electrode by ohmic contact
And an EQR polysilicon electrode 3 at the chip outer peripheral portion B.
7 and N + type impurity region 3
5 shows an EQR aluminum electrode 38 mainly composed of aluminum at a position on the outer peripheral end side of the chip of the EQR polysilicon electrode 37 on the interlayer insulating film 31 from the partially exposed surface of the interlayer insulating film 31 as shown in FIG. The chips are formed separately at the four central portions of each of the four sides excluding the corner portions of the chip.
Although not shown, a gate pad for electrically connecting the gate electrode 27 to the outside is simultaneously formed, and the source electrode 3
Reference numeral 2 designates a part thereof as a source pad for external electrical connection.
【００１６】この製造方法によれば、ＥＱＲポリシリコ
ン電極３７はゲート電極２７と同時に形成でき、工程を
増加させる必要がない。According to this manufacturing method, the EQR polysilicon electrode 37 can be formed simultaneously with the gate electrode 27, and there is no need to increase the number of steps.
【００１７】上記実施例において、ＥＱＲアルミニウム
電極を図３に示す平面パターンのもので説明したが、図
４に示すようにリング状のものであってもよい。ただ
し、この場合は、図３に示すものよりチップコーナー部
でのアルミスライドに対して少し不利となる。尚、図４
のＡ−Ａ断面のＥＱＲポリシリコン電極７７およびＥＱ
Ｒアルミニウム電極７８は図１に示すＥＱＲポリシリコ
ン電極３７およびＥＱＲアルミニウム電極３８と同一で
ある。上記実施例において、セル部Ａのエピタキシャル
層表面の平面的な構造を図２に示すソースが非環状パタ
ーンのもので説明したが、これに限定されることなく、
他の非環状パターンやソース領域がベース領域を取り囲
む環状パターンであってもよい。また、Ｕ字型溝を格子
状に形成されたもので説明したが、ストライプ状に形成
されたものであってもよい。また、一導電型としてＮ型
および他導電型としてＰ型で説明したが、一導電型とし
てＰ型および他導電型としてＮ型であってもよい。ま
た、半導体基板を高不純物濃度の一導電型で説明した
が、高不純物濃度の他導電型であってもよい。この場合
は、ＩＧＢＴに利用できる。また、半導体本体を半導体
基板とエピタキシャル層からなるもので説明したが、エ
ピタキシャル層を含まない半導体基板だけであってもよ
い。この場合、半導体基板の裏面を高濃度のＮ型不純物
層またはＰ型不純物層とする。In the above embodiment, the EQR aluminum electrode has been described as having the plane pattern shown in FIG. 3, but may be ring-shaped as shown in FIG. However, in this case, there is a slight disadvantage to the aluminum slide at the chip corner portion as compared with the one shown in FIG. FIG.
Polysilicon electrode 77 and EQ of AA cross section of FIG.
The R aluminum electrode 78 is the same as the EQR polysilicon electrode 37 and the EQR aluminum electrode 38 shown in FIG. In the above embodiment, the planar structure of the epitaxial layer surface of the cell portion A has been described with the source shown in FIG. 2 having a non-annular pattern, but is not limited thereto.
Another non-annular pattern or an annular pattern in which the source region surrounds the base region may be used. In addition, although the U-shaped grooves are described as being formed in a lattice shape, they may be formed in a stripe shape. Further, the N-type as one conductivity type and the P-type as another conductivity type have been described, but the P-type as one conductivity type and the N-type as another conductivity type may be used. In addition, although the semiconductor substrate has been described as one conductivity type with a high impurity concentration, another conductivity type with a high impurity concentration may be used. In this case, it can be used for IGBT. Further, although the semiconductor body has been described as including the semiconductor substrate and the epitaxial layer, the semiconductor body may include only the semiconductor substrate not including the epitaxial layer. In this case, the back surface of the semiconductor substrate is a high-concentration N-type impurity layer or a P-type impurity layer.
【００１８】[0018]
【発明の効果】本発明によれば、ＥＱＲポリシリコン電
極をフィールド酸化膜上に設けたので、従来のＥＱＲア
ルミニウム電極だけの場合のようにフィールド酸化膜＋
層間絶縁膜上にＥＱＲを設けた場合よりＥＱＲ効果を高
くできるので、ＥＱＲの長さ短縮によりチップ外周部を
短縮でき、チップ面積を縮小することができる。また、
本発明でのＥＱＲアルミニウム電極はＥＱＲポリシリコ
ン電極と高濃度一導電型不純物領域との電気的接続を取
る機能を有すればよいので面積を小さくでき、従来のＥ
ＱＲアルミニウム電極だけの場合よりソース電極との離
間距離を大きくとれ、更にＥＱＲポリシリコン電極は層
間絶縁膜の下に設けられておりソース電極とＥＱＲポリ
シリコン電極間は層間絶縁膜により分離されるため、温
度サイクル試験で発生するアルミニウムスライド現象に
よるソース電極とＥＱＲアルミニウム電極とのショート
を防止でき、信頼性を高くすることができる。また、Ｅ
ＱＲアルミニウム電極はリング状でもよいが、チップの
コーナー部に設けないようにした方が、特にアルミスラ
イドが大きく起こりやすいコーナー部でのソース電極と
ＥＱＲアルミニウム電極とのショートを完全に防止で
き、信頼性をより高くすることができる。また、本発明
の製造方法によれば、ＥＱＲポリシリコン電極をゲート
電極と同時に形成することにより、従来のＥＱＲアルミ
ニウム電極だけの場合と同じ工程数で製造でき、ウェー
ハ１枚当りの製造コストを従来と同一でチップ面積を縮
小することができるため、信頼性の高いチップを低コス
トで製造することができる。According to the present invention, since the EQR polysilicon electrode is provided on the field oxide film, the field oxide film is formed as in the case of the conventional EQR aluminum electrode alone.
Since the EQR effect can be enhanced as compared with the case where the EQR is provided on the interlayer insulating film, the outer peripheral portion of the chip can be shortened by shortening the length of the EQR, and the chip area can be reduced. Also,
The EQR aluminum electrode according to the present invention may have a function of establishing an electrical connection between the EQR polysilicon electrode and the high-concentration one-conductivity-type impurity region.
The distance between the source electrode and the QRR electrode is larger than that of the case of using only the QR aluminum electrode. Further, the EQR polysilicon electrode is provided below the interlayer insulating film, and the source electrode and the EQR polysilicon electrode are separated by the interlayer insulating film. In addition, the short circuit between the source electrode and the EQR aluminum electrode due to the aluminum slide phenomenon generated in the temperature cycle test can be prevented, and the reliability can be increased. Also, E
The QR aluminum electrode may be ring-shaped, but if it is not provided at the corner of the chip, it is possible to completely prevent a short circuit between the source electrode and the EQR aluminum electrode, especially at the corner where aluminum sliding is likely to occur greatly, and to improve reliability. Sex can be made higher. Further, according to the manufacturing method of the present invention, by forming the EQR polysilicon electrode and the gate electrode at the same time, it is possible to manufacture the same number of steps as in the case of using only the conventional EQR aluminum electrode, and to reduce the manufacturing cost per wafer. Since the chip area can be reduced in the same manner as described above, a highly reliable chip can be manufactured at low cost.
【図１】 本発明の１実施例である縦型パワーＭＯＳＦ
ＥＴの要部断面図。FIG. 1 is a vertical power MOSF according to an embodiment of the present invention.
Sectional drawing of the principal part of ET.
【図２】 図１の縦型パワーＭＯＳＦＥＴのＵ字型溝で
分離された半導体本体表面の１セル分の平面パターンを
示す１実施例のパターン図。FIG. 2 is a pattern diagram of one embodiment showing a planar pattern of one cell on the surface of a semiconductor body separated by a U-shaped groove of the vertical power MOSFET of FIG. 1;
【図３】 図１の縦型パワーＭＯＳＦＥＴのＥＱＲの平
面パターンを示す１実施例のパターン図。FIG. 3 is a pattern diagram of one embodiment showing a planar pattern of an EQR of the vertical power MOSFET of FIG. 1;
【図４】 図１の縦型パワーＭＯＳＦＥＴのＥＱＲの平
面パターンを示す他の実施例のパターン図。FIG. 4 is a pattern diagram of another embodiment showing a planar pattern of the EQR of the vertical power MOSFET of FIG. 1;
【図５】 図１の縦型パワーＭＯＳＦＥＴの製造工程を
示す要部断面図FIG. 5 is a cross-sectional view of a main part showing a manufacturing process of the vertical power MOSFET of FIG. 1;
【図６】 従来の縦型パワーＭＯＳＦＥＴの要部断面
図。FIG. 6 is a sectional view of a main part of a conventional vertical power MOSFET.
【図７】 図６に示す縦型パワーＭＯＳＦＥＴのＥＱＲ
の平面パターンを示すパターン図。7 is an EQR of the vertical power MOSFET shown in FIG.
FIG.
２１ 半導体本体 ２２ 半導体基板 ２３ Ｕ字型溝 ２４ 外周溝 ２５ エピタキシャル層 ２６ ゲート酸化膜 ２７ ゲート電極 ２８ ドレイン領域 ２９ ベース領域 ３０ ソース領域 ３１ 層間絶縁膜 ３２ ソース電極 ３４ Ｐ型不純物領域 ３５ Ｎ＋型不純物領域 ３６ フィールド酸化膜 ３７ ＥＱＲポリシリコン電極 ３８ ＥＱＲアルミニウム電極 ５３ シリコン酸化膜 ５４ 窒化膜 ５５ 初期溝 ５６ 外周初期溝 ５７ ＬＯＣＯＳ酸化膜 ５８ シリコン酸化膜 ５９ レジストパターン ６０ ポリシリコン膜 Reference Signs List 21 semiconductor body 22 semiconductor substrate 23 U-shaped groove 24 outer peripheral groove 25 epitaxial layer 26 gate oxide film 27 gate electrode 28 drain region 29 base region 30 source region 31 interlayer insulating film 32 source electrode 34 P-type impurity region 35 N + -type impurity region Reference Signs List 36 field oxide film 37 EQR polysilicon electrode 38 EQR aluminum electrode 53 silicon oxide film 54 nitride film 55 initial groove 56 outer peripheral initial groove 57 LOCOS oxide film 58 silicon oxide film 59 resist pattern 60 polysilicon film
Claims (9)
周端から所定距離離間した位置に外周溝が形成されセル
部およびチップ外周部に共通の低濃度一導電型ドレイン
領域を含む半導体本体を具備し、 セル部において、前記半導体本体に含まれ前記ドレイン
領域の表面層で前記Ｕ字型溝に分離された領域に設けた
他導電型ベース領域と、このベース領域の表面層に設け
た高濃度一導電型ソース領域と、前記Ｕ字型溝の内面に
設けたゲート酸化膜と、前記Ｕ字型溝にゲート酸化膜を
介して設けたポリシリコンからなるゲート電極と、この
ゲート電極と層間絶縁膜で絶縁し前記ベース領域および
ソース領域に電気的接続したアルミニウムを主金属とす
るソース電極とを具備し、 チップ外周部において、前記半導体本体に含まれ前記ド
レイン領域の表面層でチップ外周端と前記外周溝間に挟
まれた領域に設けた他導電型不純物領域と、この他導電
型不純物領域の表面層に設けた高濃度一導電型不純物領
域と、前記外周溝内に設けたフィールド酸化膜と、この
フィールド酸化膜上と前記層間絶縁膜下間に所定長で前
記高濃度一導電型不純物領域上に跨ってリング状に設け
たポリシリコンからなるＥＱＲポリシリコン電極と、こ
のＥＱＲポリシリコン電極のチップ外周端側の端部およ
び前記高濃度一導電型不純物領域に電気的接続したアル
ミニウムを主金属とするＥＱＲアルミニウム電極とを具
備した絶縁ゲート型半導体装置。1. A semiconductor including a U-shaped groove in a cell portion and an outer peripheral groove formed at a predetermined distance from an outer peripheral end of an outer peripheral portion of a chip, and a low-concentration one conductivity type drain region common to the outer peripheral portion of the cell portion and the chip. A main body, a cell region, a base region of another conductivity type provided in a region included in the semiconductor body and separated by the U-shaped groove in a surface layer of the drain region, and provided in a surface layer of the base region. A high-concentration one-conductivity-type source region, a gate oxide film provided on the inner surface of the U-shaped groove, a gate electrode made of polysilicon provided in the U-shaped groove with a gate oxide film interposed therebetween, And a source electrode made of aluminum as a main metal insulated by an interlayer insulating film and electrically connected to the base region and the source region. The drain region included in the semiconductor body in a chip outer peripheral portion. An impurity region of another conductivity type provided in a region sandwiched between the outer peripheral edge of the chip and the outer peripheral groove in the surface layer; a high-concentration one-conductivity-type impurity region provided in a surface layer of the other conductive type impurity region; And an EQR polysilicon electrode made of polysilicon provided in a ring shape over the field oxide film and the high concentration one conductivity type impurity region with a predetermined length between the field oxide film and the interlayer insulating film. And an EQR aluminum electrode having aluminum as a main metal electrically connected to an end of the EQR polysilicon electrode on the outer peripheral end of the chip and to the high-concentration one-conductivity-type impurity region.
のコーナー部を除いて設けられている請求項１記載の絶
縁ゲート型半導体装置。2. The insulated gate semiconductor device according to claim 1, wherein said EQR aluminum electrode is provided except for a corner of a rectangular chip.
の４辺の各中央部４個所に設けられている請求項２記載
の絶縁ゲート型半導体装置。3. The insulated gate semiconductor device according to claim 2, wherein said EQR aluminum electrodes are provided at four central portions on each of four sides of a rectangular chip.
設けられている請求項１記載の絶縁ゲート型半導体装
置。4. The insulated gate semiconductor device according to claim 1, wherein said EQR aluminum electrode is provided in a ring shape.
電極と同時に設けられた請求項１記載の絶縁ゲート型半
導体装置。5. The insulated gate semiconductor device according to claim 1, wherein said EQR polysilicon electrode is provided simultaneously with said gate electrode.
たエピタキシャル層である請求項１記載の絶縁ゲート型
半導体装置。6. The insulated gate semiconductor device according to claim 1, wherein said semiconductor body is an epitaxial layer formed on a semiconductor substrate.
求項６記載の絶縁ゲート型半導体装置。7. The insulated gate semiconductor device according to claim 6, wherein said semiconductor substrate is of a high concentration one conductivity type.
求項６記載の絶縁ゲート型半導体装置。8. The insulated gate semiconductor device according to claim 6, wherein said semiconductor substrate is of a high concentration and other conductivity type.
層を表面側に含む半導体本体上にシリコン酸化膜とシリ
コン窒化膜を順次形成した後、エッチングにより半導体
本体表面のセル部に初期溝とチップ外周部の外周端から
所定距離離間した位置に外周初期溝とを形成する第１工
程と、 第１工程完了後、前記シリコン窒化膜をマスクに前記初
期溝および外周初期溝の内面にＬＯＣＯＳ酸化膜を形成
することより初期溝がＵ字型溝および外周初期溝が外周
溝に形状変形され、このＬＯＣＯＳ酸化膜をマスクに、
セル部において、前記半導体層の表面層の前記Ｕ字型溝
に分離された領域に他導電型ベース領域を形成するとと
もにこのベース領域の表面層に高濃度一導電型ソース領
域を形成し、チップ外周部において、前記半導体層の表
面層のチップ外周端と前記外周溝に挟まれた領域に他導
電型不純物領域を形成するとともにこの他導電型不純物
領域の表面層に高濃度一導電型不純物領域を形成する第
２工程と、 第２工程完了後、前記Ｕ字型溝のＬＯＣＯＳ酸化膜を除
去するとともに前記外周溝のＬＯＣＯＳ酸化膜をフィー
ルド酸化膜として残す第３工程と、 第３工程完了後、Ｕ字型溝内面を含む露出した半導体本
体表面にゲート酸化膜を形成した後、その上からポリシ
リコン膜を被覆する第４工程と、 第４工程完了後、ポリシリコン膜をエッチングして、セ
ル部において、前記ソース領域表面の一部およびＵ字型
溝のポリシリコン膜を残してゲート電極を形成し、チッ
プ外周部において、前記フィールド酸化膜上に所定長で
前記高濃度一導電型不純物領域上の一部に跨ってリング
状にポリシリコン膜を残してＥＱＲポリシリコン電極を
形成し、その上から層間絶縁膜を被覆する第５工程と、 第５工程完了後、前記層間絶縁膜およびゲート酸化膜を
エッチングして、セル部において、前記ソース領域表面
の一部およびベース領域表面を露出し、チップ外周部に
おいて、前記高濃度一導電型不純物領域表面を露出する
とともに、前記ＥＱＲポリシリコン電極表面のチップ外
周端側の端部を露出して後、その上からアルミニウム膜
を被覆し、このアルミニウム膜をエッチングして、セル
部において前記ベース領域およびソース領域と電気的に
接続するソース電極を形成し、チップ外周部において、
前記ＥＱＲポリシリコン電極のチップ外周端側の端部お
よび前記高濃度一導電型不純物領域に電気的接続したア
ルミニウムを主金属とするＥＱＲアルミニウム電極を形
成する第６工程とを有する絶縁ゲート型半導体装置の製
造方法。9. A silicon oxide film and a silicon nitride film are sequentially formed on a semiconductor body including a low-concentration one-conductivity-type semiconductor layer serving as a drain region on a surface side, and an initial groove is formed in a cell portion on the semiconductor body surface by etching. A first step of forming an outer peripheral initial groove at a position separated from the outer peripheral end of the chip outer peripheral part by a predetermined distance; and after completion of the first step, LOCOS oxidation is performed on the inner surfaces of the initial groove and the outer peripheral initial groove using the silicon nitride film as a mask. By forming the film, the initial groove is deformed into a U-shaped groove and the outer peripheral initial groove is deformed into an outer peripheral groove. Using this LOCOS oxide film as a mask,
In the cell portion, a different conductivity type base region is formed in a region of the surface layer of the semiconductor layer separated by the U-shaped groove, and a high concentration one conductivity type source region is formed in a surface layer of the base region; In the outer peripheral portion, an impurity region of another conductivity type is formed in a region between the chip outer peripheral end of the surface layer of the semiconductor layer and the outer peripheral groove, and a high-concentration one conductivity type impurity region is formed in a surface layer of the impurity region of the other conductivity type. A second step of forming a LOCOS oxide film in the U-shaped groove and leaving the LOCOS oxide film in the outer peripheral groove as a field oxide film after the completion of the second step; and Forming a gate oxide film on the exposed surface of the semiconductor body including the inner surface of the U-shaped groove, and then covering the polysilicon film from above, and etching the polysilicon film after completion of the fourth process In the cell portion, a gate electrode is formed while leaving a part of the source region surface and the polysilicon film of the U-shaped groove. A fifth step of forming an EQR polysilicon electrode while leaving a polysilicon film in a ring shape over a part of the mold impurity region, and covering the interlayer insulating film from above; The film and the gate oxide film are etched to expose a part of the source region surface and the base region surface in the cell portion, and to expose the high concentration one conductivity type impurity region surface in the chip outer peripheral portion, After exposing the end portion of the surface of the polysilicon electrode on the chip outer peripheral end side, an aluminum film is coated thereon, and the aluminum film is etched to form a cell portion. Said base region and forming a source region and electrically source electrode connected, in the chip peripheral portion,
Forming an EQR aluminum electrode having aluminum as a main metal electrically connected to an end of the EQR polysilicon electrode on the chip outer peripheral end side and the high-concentration one-conductivity-type impurity region. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08097599A JP3417336B2 (en) | 1999-03-25 | 1999-03-25 | Insulated gate semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08097599A JP3417336B2 (en) | 1999-03-25 | 1999-03-25 | Insulated gate semiconductor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000277728A true JP2000277728A (en) | 2000-10-06 |
| JP3417336B2 JP3417336B2 (en) | 2003-06-16 |
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ID=13733525
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|---|---|---|---|
| JP08097599A Expired - Fee Related JP3417336B2 (en) | 1999-03-25 | 1999-03-25 | Insulated gate semiconductor device and method of manufacturing the same |
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