JP2000269256A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JP2000269256A
JP2000269256A JP6957099A JP6957099A JP2000269256A JP 2000269256 A JP2000269256 A JP 2000269256A JP 6957099 A JP6957099 A JP 6957099A JP 6957099 A JP6957099 A JP 6957099A JP 2000269256 A JP2000269256 A JP 2000269256A
Authority
JP
Japan
Prior art keywords
insulating resin
semiconductor device
resin layer
conductive adhesive
post
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6957099A
Other languages
Japanese (ja)
Inventor
Junichi Saeki
準一 佐伯
Hiroyuki Hozoji
裕之 宝蔵時
Masaaki Sato
正昭 佐藤
Shigeharu Tsunoda
重晴 角田
Kenji Yoshimi
健二 吉見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6957099A priority Critical patent/JP2000269256A/en
Publication of JP2000269256A publication Critical patent/JP2000269256A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device by forming post out of thermosetting conductive adhesive and electrically connecting a several electrodes on a semiconductor chip with the posts. SOLUTION: A semiconductor chip 1 is placed with its circuit face facing downward, and on-chip electrode 2 are formed at the ends of the circuit face. Posts 17 of conductive adhesive are vertically erected form the on-chip electrodes 2 using isotropic thermosetting resin containing flake-like Ag. An insulating resin layer 18 is formed on the circuit face of the semiconductor chip 1 except on the on-chip electrodes 2. The ends of the insulating resin layer 18 are set so as to be flush with the posts 17, and the posts 17 are electrically connected with internal terminals 19 on that plane. External terminals 21 are formed at the ends of the wiring portions 20 extending from the internal terminals 19 with a pitch wider than that of the electrodes 2 on the semiconductor chip 1.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体チップと外
部端子との電気的接続の一部に導電性接着剤を用いた半
導体装置およびその製造方法に関する。[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device using a conductive adhesive for a part of electrical connection between a semiconductor chip and an external terminal, and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】従来の半導体装置は、半導体チップに形
成された周辺電極を再配線層を用いて電極ピッチの広い
エリアアレイ型の電極に変換するように構成されてい
る。従って、再配線後のチップ電極のピッチは再配線前
のものに比べて広くなり、実装基板側の電極も比較的広
いピッチにでき、実装基板の配線も楽になり、低コスト
基板の使用も可能となると言った利点があった。2. Description of the Related Art A conventional semiconductor device is configured to convert a peripheral electrode formed on a semiconductor chip into an area array type electrode having a wide electrode pitch by using a redistribution layer. Therefore, the pitch of the chip electrodes after rewiring is wider than that before rewiring, the electrodes on the mounting board can be made relatively wide, wiring on the mounting board becomes easier, and low-cost boards can be used. There was an advantage that said.

【０００３】[0003]

【発明が解決しようとする課題】しかし、この再配線層
が再配線前の回路と近い距離にあると両者の間で電気容
量の増大が起きて電気特性が低下するので、再配線層と
再配線層前の回路との間に所定の距離が必要となる。こ
の再配線層と再配線前の回路との距離を開けるために金
属のポストを設けても良いが、金属の場合、この形成に
多大の時間を要し、生産効率が大幅に低下してしまう。However, if the redistribution layer is located at a short distance from the circuit before the redistribution, an increase in electric capacity occurs between the two and the electrical characteristics are degraded. A predetermined distance is required between the circuit and the circuit before the wiring layer. A metal post may be provided to increase the distance between the rewiring layer and the circuit before rewiring. However, in the case of metal, the formation takes a lot of time, and the production efficiency is greatly reduced. .

【０００４】一方、導電性接着剤によりポストを形成す
る例が、特開平９−９２７５１号に開示される。しか
し、このポストは熱可塑性の導電性接着剤で構成されて
いるので、回路基板への実装時に一括リフローを行う
と、ポストが溶融してしまい前述の距離を確保する事が
極めて困難である。さらには、半導体チップと外部電極
との電気的接続さえ確保できなくなり、半導体装置の信
頼性に課題が残る。すなわち、ポストを用いた半導体装
置における実装時の問題については一切着目が無い。On the other hand, an example of forming a post with a conductive adhesive is disclosed in Japanese Patent Application Laid-Open No. 9-92751. However, since this post is made of a thermoplastic conductive adhesive, if the package is reflowed at the time of mounting on a circuit board, the post melts and it is extremely difficult to secure the above-mentioned distance. Further, even electrical connection between the semiconductor chip and the external electrodes cannot be secured, and a problem remains in the reliability of the semiconductor device. That is, no attention is paid to the problem at the time of mounting in a semiconductor device using a post.

【０００５】本発明の目的は、導電性接着剤を用いた半
導体装置の信頼性を向上させることにある。An object of the present invention is to improve the reliability of a semiconductor device using a conductive adhesive.

【０００６】[0006]

【課題を解決するための手段】本発明は、上記目的を達
成するために、複数個の電極を有する半導体チップと、
該電極と電気的に接続されたポストと該ポストと電気的
に接続された配線とを有する絶縁性樹脂層と、該絶縁性
樹脂層に形成された配線と電気的に接続された外部電極
とを備えた半導体装置であって、該ポストが熱硬化性の
導電性接着剤で構成されたものである。According to the present invention, there is provided a semiconductor chip having a plurality of electrodes.
An insulating resin layer having a post electrically connected to the electrode and a wiring electrically connected to the post; and an external electrode electrically connected to the wiring formed on the insulating resin layer. Wherein the post is made of a thermosetting conductive adhesive.

【０００７】また、前記絶縁樹脂層が熱硬化性樹脂であ
るものである。Further, the insulating resin layer is a thermosetting resin.

【０００８】また、前記絶縁性樹脂層が前記半導体チッ
プよりも外側に張り出すように形成され、その絶縁性樹
脂層の張り出した領域に金属板が形成されたものであ
る。Further, the insulating resin layer is formed so as to protrude outside the semiconductor chip, and a metal plate is formed in a region where the insulating resin layer protrudes.

【０００９】また、前記絶縁性樹脂層が前記半導体チッ
プよりも外側に張り出すように形成され、少なくともそ
の絶縁性樹脂層の張り出した領域と前記半導体チップと
を熱硬化性の封止材で封止したものである。Further, the insulating resin layer is formed so as to protrude outside the semiconductor chip, and at least a region where the insulating resin layer protrudes and the semiconductor chip are sealed with a thermosetting sealing material. It is stopped.

【００１０】また、前記外部電極が熱硬化性の導電性接
着剤のバンプで形成されたものである。Further, the external electrode is formed of a thermosetting conductive adhesive bump.

【００１１】また、複数個の電極を有する半導体チップ
と、該電極と電気的に接続された熱硬化性の導電性接着
剤で形成されたポストと該ポストと電気的に接続された
配線とを有する熱硬化性の樹脂で形成された絶縁性樹脂
層と、該絶縁性樹脂層に形成された配線と電気的に接続
された外部電極とを備えた半導体装置の製造方法であっ
て、配線と該配線と電気的に接続されたポストとを有す
る絶縁性樹脂層と半導体チップとを位置合わせする工程
と、該半導体チップの有する電極と前記絶縁性樹脂層の
有するポストとを接続した状態で前記ポストと前記絶縁
性樹脂層とを熱硬化させる工程とを備えたものである。Also, a semiconductor chip having a plurality of electrodes, a post formed of a thermosetting conductive adhesive electrically connected to the electrodes, and a wiring electrically connected to the posts are formed. An insulating resin layer formed of a thermosetting resin having, and a method of manufacturing a semiconductor device including an external electrode electrically connected to a wiring formed in the insulating resin layer, comprising: A step of aligning an insulating resin layer having a post electrically connected to the wiring and the semiconductor chip, and the step of connecting the electrode of the semiconductor chip and the post of the insulating resin layer to each other. A step of thermally curing the post and the insulating resin layer.

【００１２】また、前記絶縁性樹脂層と前記ポストとを
それぞれの樹脂及び導電性接着剤がＢステージの状態で
位置合わせするものである。In addition, the insulating resin layer and the post are aligned with each other in a state where the respective resin and the conductive adhesive are in a B stage.

【００１３】また、前記絶縁性樹脂層は、テープ上に配
線を形成する工程と、該配線を形成したテープ上にＢス
テージの状態で絶縁性樹脂層を形成する工程と、該絶縁
性樹脂層の所定の位置を貫通させてポスト用のスルーホ
ールを形成する工程と、該スルーホールに熱硬化性の導
電性接着剤をＢステージの状態で充填させてポストを形
成する工程と、該ポストと電気的に接続されかつ前記外
部電極と電気的に接続するための配線を形成する工程と
を用いて形成されるものである。A step of forming a wiring on a tape, a step of forming an insulating resin layer in a B-stage state on the tape on which the wiring is formed, and a step of forming the insulating resin layer on the tape. Forming a post through-hole by penetrating a predetermined position of the post, filling the through-hole with a thermosetting conductive adhesive in a B-stage state to form a post, Forming a wiring that is electrically connected and electrically connected to the external electrode.

【００１４】[0014]

【発明の実施の形態】以下、本発明の実施例について図
を用いて説明する。Embodiments of the present invention will be described below with reference to the drawings.

【００１５】図1〜図14は本発明の第1の実施例を示す図
である。図1は第1の実施例の断面図であり、半導体チッ
プ1は回路面を下にしており、この端部にはチップ上電
極2が形成されている。このチップ上電極2はウエハー
（図示せず）段階で酸化膜形成防止のための金属処理、
例えばAuめっきなどが施されている。このチップ上電極
2から垂直方向に導電性接着剤のポスト17を立ててい
る。導電性接着剤のポスト17は導電性の充填材、例えば
フレーク状のAgを含有した等方性(導電特性に方向性を
持たない)の熱硬化性樹脂である。一方、半導体チップ1
の回路面においてチップ上電極2以外の部分には絶縁性
樹脂層18を形成してある。絶縁性樹脂層18は熱硬化性樹
脂であり、半導体チップ1と実装基板(図示せず)の線膨
張係数の違いに起因する熱応力を低減する必要性が高い
場合にはエラストマー(非常に弾性率の低い樹脂)が用い
られ、低コスト化を優先する場合には、従来の半導体封
止で使われているエポキシ系複合材料を用いる。導電性
接着剤のポスト17と絶縁性樹脂層18の終端部は同一平面
にあり、この平面上に導電性接着剤のポスト17と電気的
に接続させる内部端子19とここから伸びる配線部20を設
け、各配線部20の終端には半導体チップ1の電極2よりも
広いピッチで外部端子21が形成してある。内部端子19、
配線部20、外部端子21は金属材料、例えばCuで構成され
ており、通常のTAB(Tape Automated Bonding)テープを
製作する方法で絶縁基材22の上にメッキ法で形成されて
いる。接続の信頼性を高める場合には必要箇所にCu配線
の上からNi/AuメッキあるいはAuメッキを施す。絶縁基
材22は耐熱性の樹脂、例えばポリイミドなどが用いら
れ、外部端子21が存在する箇所には絶縁基材窓23が開け
られている。FIG. 1 to FIG. 14 are views showing a first embodiment of the present invention. FIG. 1 is a cross-sectional view of the first embodiment. A semiconductor chip 1 has a circuit surface facing down, and an on-chip electrode 2 is formed at this end. The electrode 2 on the chip is treated with a metal at a wafer (not shown) stage to prevent oxide film formation,
For example, Au plating is applied. This electrode on the chip
The conductive adhesive post 17 stands vertically from 2. The post 17 of the conductive adhesive is a conductive filler, for example, an isotropic (having no directionality in the conductive property) thermosetting resin containing flake Ag. On the other hand, semiconductor chip 1
An insulating resin layer 18 is formed on a portion of the circuit surface other than the on-chip electrode 2. The insulating resin layer 18 is a thermosetting resin, and when it is highly necessary to reduce thermal stress due to a difference in linear expansion coefficient between the semiconductor chip 1 and a mounting substrate (not shown), an elastomer (a very elastic resin) is used. If low cost resin is used and priority is given to cost reduction, an epoxy-based composite material used in conventional semiconductor encapsulation is used. The terminal 17 of the conductive adhesive post 17 and the terminal end of the insulating resin layer 18 are on the same plane, and the internal terminal 19 electrically connected to the conductive adhesive post 17 and the wiring portion 20 extending therefrom are located on this plane. The external terminals 21 are formed at the terminal of each wiring section 20 at a pitch wider than the electrode 2 of the semiconductor chip 1. Internal terminal 19,
The wiring portion 20 and the external terminals 21 are made of a metal material, for example, Cu, and are formed on the insulating base material 22 by a plating method using a normal TAB (Tape Automated Bonding) tape manufacturing method. In order to improve the reliability of the connection, Ni / Au plating or Au plating is applied to the necessary portions from above the Cu wiring. The insulating base material 22 is made of a heat-resistant resin, for example, polyimide or the like, and an insulating base material window 23 is opened at a position where the external terminal 21 exists.

【００１６】図2は図１の下平面図であり、絶縁基材22
の所定部に設けられた絶縁基材窓23に外部端子21がマト
リックス状に配置されている。図3は図1のA−A断面の下
側の平面図である。絶縁基材22の上に各内部端子19と各
外部端子21は各配線部20を通じて電気的に接続されてお
り、外部端子21は内部端子19よりも広いピッチでマトリ
ックス状に配置されている。図4は図1のA−A断面の上側
の平面図である。絶縁性樹脂層18の端部近くに導電性接
着剤のポスト17が配置されている。FIG. 2 is a bottom plan view of FIG.
The external terminals 21 are arranged in a matrix on an insulating base material window 23 provided at a predetermined portion of the device. FIG. 3 is a plan view of the lower side of the AA cross section in FIG. Each of the internal terminals 19 and each of the external terminals 21 are electrically connected on the insulating base material 22 through each of the wiring portions 20, and the external terminals 21 are arranged in a matrix at a wider pitch than the internal terminals 19. FIG. 4 is an upper plan view of the AA cross section of FIG. A post 17 made of a conductive adhesive is arranged near the end of the insulating resin layer 18.

【００１７】このように、熱硬化性の導電性接着剤によ
りポスト17を形成すると、再配線層となる内部端子19、
配線部20、外部端子21と、半導体チップ1の回路面との
距離を確保できるので、両者の間での電気容量の増大を
抑制し電気特性を確保する事ができる。As described above, when the posts 17 are formed by the thermosetting conductive adhesive, the internal terminals 19, which become the rewiring layer,
Since the distance between the wiring portion 20, the external terminal 21, and the circuit surface of the semiconductor chip 1 can be ensured, an increase in electric capacity between the two can be suppressed, and electric characteristics can be ensured.

【００１８】また、回路基板への実装時に一括リフロー
を行ったとしても、ポスト17は溶融することなく硬化す
るので、前述の距離を高信頼に確保する事ができる。Further, even if batch reflow is performed during mounting on a circuit board, the post 17 is cured without melting, so that the above-described distance can be secured with high reliability.

【００１９】次に図5〜図14を用いて本発明の第1の実施
例の製造プロセスを説明する。図5は絶縁基材22上に内
部端子19、配線部20、外部端子21を形成した状態のテー
プの平面図である。絶縁基材22には同じ材質でできた外
枠24、搬送、位置決め用のスプロケットホール25、外枠
24からの切断を容易にするためのスリット26、外枠24と
内部とを繋いでおくための吊り部27が設けられている。Next, the manufacturing process of the first embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a plan view of the tape in a state where the internal terminals 19, the wiring portions 20, and the external terminals 21 are formed on the insulating base material 22. An outer frame 24 made of the same material as the insulating base material 22, a sprocket hole 25 for transport and positioning, an outer frame
There are provided a slit 26 for facilitating cutting from the outer frame 24, and a suspending portion 27 for connecting the outer frame 24 to the inside.

【００２０】なお、図5のテープは縦方向には連続して
同様のパターンが形成されている。図6は図5のＢーＢ断
面図である。図5、図6の状態のテープは次のようにして
作られる。まず、絶縁基材22を打ち抜き法などにより加
工して、絶縁基材窓23、スプロケットホール25、スリッ
ト26が作られる。次にCu箔(図示せず)を絶縁基材22上に
ラミネートする。そして、感光性のホトレジスト(図示
せず)を塗布し、露光、現像処理により内部電極19、配
線部20、外部電極21の上のみにホトレジストが残り、そ
れ以外の箇所は銅箔が露出する。そして、絶縁基材22の
裏にも裏止めレジスト(図示せず)が塗布され、エッチン
グにより露出銅箔部は除去される。最後にホトレジスト
ならびに裏止めレジストは洗浄により除去され、図5、
図6の状態の配線付きテープが完成する。The tape shown in FIG. 5 has a similar pattern formed continuously in the vertical direction. FIG. 6 is a sectional view taken along line BB of FIG. The tape in the state shown in FIGS. 5 and 6 is produced as follows. First, the insulating base material 22 is processed by a punching method or the like to form an insulating base material window 23, a sprocket hole 25, and a slit 26. Next, a Cu foil (not shown) is laminated on the insulating base material 22. Then, a photosensitive photoresist (not shown) is applied, and the photoresist is left only on the internal electrodes 19, the wiring portions 20, and the external electrodes 21 by exposure and development processing, and the copper foil is exposed in other portions. Then, a backing resist (not shown) is also applied to the back of the insulating base material 22, and the exposed copper foil portion is removed by etching. Finally, the photoresist and backing resist are removed by washing, and FIG.
The tape with wiring in the state of FIG. 6 is completed.

【００２１】図7は図5のテープ上に絶縁性樹脂層18を形
成した状態の平面図であり、図8はそのＢ−Ｂ断面図で
ある。絶縁樹脂層18はBステージ(反応を少し進め、流動
はしにくく、接着性は失っていない状態)の熱硬化性樹
脂であり、印刷法などにより、内部端子19、配線部20、
外部端子21を覆うように絶縁基材22の上面に形成され
る。FIG. 7 is a plan view showing a state in which an insulating resin layer 18 is formed on the tape shown in FIG. 5, and FIG. 8 is a sectional view taken along the line BB of FIG. The insulating resin layer 18 is a B-stage (a little progression of the reaction, hard to flow, and has not lost the adhesiveness) thermosetting resin, and the internal terminals 19, the wiring section 20,
It is formed on the upper surface of the insulating base material 22 so as to cover the external terminals 21.

【００２２】図9は図8の状態のテープの絶縁樹脂層18の
所定位置に絶縁樹脂窓28を開け、内部端子19を露出させ
た状態の平面図であり、図10はそのＢ−Ｂ断面図であ
る。絶縁樹脂窓28はレーザー加工などにより設けられ
る。FIG. 9 is a plan view showing a state in which an insulating resin window 28 is opened at a predetermined position of the insulating resin layer 18 of the tape in the state of FIG. 8 and the internal terminals 19 are exposed, and FIG. FIG. The insulating resin window 28 is provided by laser processing or the like.

【００２３】図11は図9の状態のテープの絶縁樹脂窓28
に導電性接着剤のポスト17を形成した状態の平面図であ
り、図12はそのＢ−Ｂ断面図である。導電性接着剤のポ
スト17は導電性の充填材、例えばAgフレークなどを含有
した等方性の熱硬化性樹脂であり、このＢステージの状
態のものをステンシル、あるいはスクリーン印刷などに
より絶縁樹脂窓に注入して形成する。FIG. 11 shows the insulating resin window 28 of the tape in the state of FIG.
FIG. 12 is a plan view showing a state in which a post 17 of a conductive adhesive is formed in FIG. The post 17 of the conductive adhesive is an isotropic thermosetting resin containing a conductive filler, for example, Ag flake, and the B-stage state is formed by stencil or screen printing to form an insulating resin window. And formed by injection.

【００２４】図13は搭載する半導体チップ1の回路面の
平面図であり、複数のチップ上電極2が半導体チップ1の
周辺に並んでいる。これらのチップ上電極2はウエハー
段階で予めAuめっきなどの酸化膜防止処理が施されてい
る。FIG. 13 is a plan view of a circuit surface of the semiconductor chip 1 to be mounted, and a plurality of on-chip electrodes 2 are arranged around the semiconductor chip 1. These on-chip electrodes 2 are previously subjected to an oxide film prevention treatment such as Au plating at the wafer stage.

【００２５】図14は図13の半導体チップを図12の状態の
テープに重ね合わせた状態を示す断面図である。このと
きに、各チップ上電極2に対応する位置において各導電
性接着剤のポスト17が接触するとともに、絶縁性樹脂層
18が半導体チップ1の回路面のチップ上電極以外の部分
に接触する。ここで、半導体チップ1の上面は上型加熱
加圧治具29で、絶縁基材22の下面は下型加熱圧着治具30
が押し当てられ、加圧により導電性接着剤のポスト17は
チップ上電極2ならびに内部端子19と密着するととも
に、絶縁性樹脂層18は半導体チップ1の電極以外の回路
面ならびに配線部20、外部端子21を含む絶縁基材22と密
着する。同時に上型加熱加圧治具29、下型加熱加圧治具
30の熱により導電性接着剤のポスト17と絶縁性樹脂層18
は硬化反応が急速に進行し、先に述べた密着界面で相手
材料と強固に接着する。所定時間経過後、上型加熱加圧
治具29および下型加熱加圧治具30は取り除かれ、チップ
を搭載した第1の実施例による半導体装置31はベーク炉
(図示せず)に入れられ、製品としての問題のないレベル
まで硬化反応を進めた後に取り出される。その後、所定
の電気特性試験などを行い完成品となる。絶縁基材の外
枠24およびスプロケットホール25は所定の工程まで、搬
送、位置決めのために用いられ、用済み後に吊り部27が
切断される。FIG. 14 is a sectional view showing a state in which the semiconductor chip of FIG. 13 is superimposed on the tape in the state of FIG. At this time, the post 17 of each conductive adhesive contacts at a position corresponding to each on-chip electrode 2, and the insulating resin layer
18 comes into contact with a portion of the circuit surface of the semiconductor chip 1 other than the on-chip electrodes. Here, the upper surface of the semiconductor chip 1 is an upper heating and pressing jig 29, and the lower surface of the insulating base material 22 is a lower heating and pressing jig 30.
The post 17 of the conductive adhesive is brought into close contact with the on-chip electrode 2 and the internal terminal 19 by pressurization, and the insulating resin layer 18 is attached to the circuit surface other than the electrode of the semiconductor chip 1 and the wiring portion 20 and the external portion. It is in close contact with the insulating base material 22 including the terminals 21. At the same time, the upper mold heating and pressing jig 29 and the lower mold heating and pressing jig
The conductive adhesive post 17 and the insulating resin layer 18 are heated by the heat of 30.
The curing reaction progresses rapidly, and the resin firmly adheres to the mating material at the above-mentioned contact interface. After a lapse of a predetermined time, the upper heating / pressing jig 29 and the lower heating / pressing jig 30 are removed, and the semiconductor device 31 according to the first embodiment having chips mounted thereon is baked in a baking furnace.
(Not shown), and after the curing reaction has proceeded to a level that does not cause a problem as a product, it is removed. Thereafter, a predetermined electrical characteristic test or the like is performed to complete the product. The outer frame 24 and the sprocket holes 25 of the insulating base material are used for transportation and positioning up to a predetermined process, and the hanging portion 27 is cut after use.

【００２６】第1の実施例は、所定パターンを予め連続
的に形成したテープに半導体チップを搭載するため、半
導体装置31の組立が高能率に行えるメリットがある。ま
た、外部端子21は剛性のある絶縁基材23上にCu配線によ
り形成されており、外部端子21のピッチにずれを生じ難
く、実装しやすい。外部端子21の材質はCuであるが、必
要に応じてNiやAuメッキも施すことができ、どちらの材
質でも、この上にはんだバンプや導電性接着剤を搭載し
て実装基板との接続を取ることが容易である。The first embodiment has an advantage that the semiconductor device 31 can be assembled with high efficiency because the semiconductor chip is mounted on a tape on which a predetermined pattern is continuously formed in advance. Further, the external terminals 21 are formed by a Cu wiring on a rigid insulating base material 23, so that the pitch of the external terminals 21 hardly shifts and is easy to mount. Although the material of the external terminal 21 is Cu, it can be plated with Ni or Au as necessary.Either material can be connected to a mounting board by mounting a solder bump or a conductive adhesive thereon. Easy to take.

【００２７】第2の実施例を図15〜図17で説明する。図1
5は半導体ウエハー32およびこれに搭載する所定パター
ン形成済みのウエハー対応テープ33の断面図である。切
断後に複数のチップとなる半導体ウエハー32にはチップ
上電極2が形成されており、Auめっきなどの酸化膜防止
処理が施されている。一方、図5〜図12に示した方法で
組み立てられた所定パターン形成済みのウエハー対応テ
ープ33をウエハー32の所定位置に重ねる。このときの所
定パターン形成済みウエハー対応テープ33はチップとな
るべき素子の数に対応した縦横のマトリックス状のパタ
ーンが形成されている（平面図は図示せず）。また、便
宜上、2個のチップが得られるウエハー32を示してい
る。図16は所定パターン形成済みのウエハー対応テープ
33を半導体ウエハー32に押し当てて、上型加熱加圧治具
29および下型加熱加圧治具30で加熱圧着を行っている断
面図である。所定時間後、テープ33を搭載した半導体ウ
エハー32は治具29、30から取り出され、されにベーク炉
で硬化反応を進める。次に、半導体ウエハー32はテープ
33ごと個別半導体チップ1の状態にダイシング装置(図示
せず)で切断され、図17のような第2の実施例による半導
体装置34が得られる。この実施例はウエハー段階で一括
してパターン形成するので、第1の実施例よりも高能率
化を図りやすい。A second embodiment will be described with reference to FIGS. Figure 1
5 is a cross-sectional view of a semiconductor wafer 32 and a wafer-compatible tape 33 mounted on the semiconductor wafer 32 and having a predetermined pattern formed thereon. The on-chip electrode 2 is formed on the semiconductor wafer 32 that becomes a plurality of chips after cutting, and is subjected to an oxide film prevention treatment such as Au plating. On the other hand, the wafer-corresponding tape 33 with a predetermined pattern formed and assembled by the method shown in FIGS. 5 to 12 is overlaid on a predetermined position of the wafer 32. At this time, the wafer-corresponding tape 33 on which a predetermined pattern has been formed has vertical and horizontal matrix-like patterns corresponding to the number of elements to be formed into chips (a plan view is not shown). Also, for convenience, a wafer 32 from which two chips are obtained is shown. Figure 16 shows a wafer-compatible tape with a predetermined pattern formed.
33 is pressed against the semiconductor wafer 32, and the upper
FIG. 3 is a cross-sectional view in which thermocompression bonding is performed by a lower mold 29 and a lower mold heating and pressing jig 30. After a predetermined time, the semiconductor wafer 32 on which the tape 33 is mounted is removed from the jigs 29 and 30, and the curing reaction proceeds in a baking furnace. Next, the semiconductor wafer 32 is taped.
Each of the semiconductor chips 33 is cut into a state of the individual semiconductor chip 1 by a dicing device (not shown), and a semiconductor device 34 according to the second embodiment as shown in FIG. 17 is obtained. In this embodiment, since patterns are formed collectively at the wafer stage, it is easier to achieve higher efficiency than in the first embodiment.

【００２８】第3の実施例を図18〜図23で説明する。図1
8は半導体ウエハー32に絶縁性樹脂層18を形成した断面
図である。図19はレーザ加工などによりチップ上電極2
に絶縁樹脂窓28を形成した断面図である。図20は導電性
接着剤のポスト17を絶縁性樹脂窓28にステンシルあるい
はスクリーン印刷などにより形成した状態の断面図であ
る。図21はウエハー対応配線済テープ35(図5、図6の状
態に相当)を図20の加工まで終えた半導体ウエハー32に
位置合わせした状態の断面図である。図22はウエハー対
応配線済テープ35を半導体ウエハー32上の絶縁性樹脂
層、導電性接着剤のポスト17に接触させ、治具(図示せ
ず)で加熱加圧した後、所定時間ベーク炉で硬化させた
状態の断面図である。図23は図22の状態の半導体ウエハ
ー32を個々の半導体チップ1の状態に切断した状態の断
面図である。これにより、第3の実施例による半導体装
置36が得られる。この実施例では、ウエハー上で導電性
接着剤のポスト17を形成するので、第1、第2の実施例に
比べてチップ電極2と導電性接着剤のポスト17の位置合
わせが容易という利点を有する。A third embodiment will be described with reference to FIGS. Figure 1
FIG. 8 is a cross-sectional view in which the insulating resin layer 18 is formed on the semiconductor wafer 32. Fig. 19 shows the electrode 2 on the chip
FIG. 3 is a sectional view in which an insulating resin window 28 is formed. FIG. 20 is a sectional view showing a state in which the posts 17 of the conductive adhesive are formed on the insulating resin window 28 by stencil or screen printing. FIG. 21 is a cross-sectional view showing a state in which the wafer-mounted wired tape 35 (corresponding to the states in FIGS. 5 and 6) is aligned with the semiconductor wafer 32 after the processing shown in FIG. FIG. 22 shows a state in which the wiring tape 35 corresponding to the wafer is brought into contact with the insulating resin layer on the semiconductor wafer 32, the post 17 of the conductive adhesive, and heated and pressed with a jig (not shown). It is sectional drawing of the state hardened | cured. FIG. 23 is a cross-sectional view showing a state where the semiconductor wafer 32 in the state shown in FIG. 22 is cut into individual semiconductor chips 1. Thereby, the semiconductor device 36 according to the third embodiment is obtained. In this embodiment, since the conductive adhesive post 17 is formed on the wafer, there is an advantage that the alignment of the chip electrode 2 and the conductive adhesive post 17 is easier than in the first and second embodiments. Have.

【００２９】なお、第2の実施例による半導体装置34、
第3の実施例による半導体装置36は最終構造は第1の実施
例による半導体装置31ならびに図1と同じであり、半導
体チップと同じ面積の半導体装置になる。The semiconductor device 34 according to the second embodiment,
The semiconductor device 36 according to the third embodiment has the same final structure as the semiconductor device 31 according to the first embodiment and FIG. 1, and has the same area as the semiconductor chip.

【００３０】第4の実施例を図24〜図27で説明する。図2
4は第4の実施例の断面図であり、第1〜第3の実施例との
違いはCu配線であった部分が導電性樹脂になっているこ
とである。すなわち、導電性接着剤のポストに導電性接
着剤による内部端子37が接着され、ここから導電性接着
剤による配線部38により導電性接着剤による外部端子39
と繋がっている。図25は図24の下平面図であり、絶縁基
材22の所定部に設けられた絶縁基材窓23に導電性接着剤
による外部端子39がマトリックス状に配置されている。
図26は図24のA−A断面の上側の平面図である。絶縁性樹
脂層28の上に導電性接着剤による内部端子37、導電性接
着剤による配線部38、導電性接着剤による外部端子39が
形成され電気的に接続されている。これは、剥離可能な
カバーテープ(図示せず)の上に絶縁性樹脂層18を形成
し、レーザーなどで穴加工をした箇所に導電性接着剤の
ポスト17を形成して同一平面にした後に導電性接着剤を
用いてステンシルあるいはスクリーン印刷などにより、
内部端子37、配線部38、外部端子39を形成する。図27は
図24のA−A断面の下側の平面図である。絶縁基材22には
絶縁基材窓23のみが設けられており、ここには配線はな
い。この絶縁基材22を図26の状態まで組み立てられた前
記カバーテープの所定位置に貼り、カバーテープを剥離
してからチップ1に搭載して所定の加熱、加圧工程を経
て、図24の状態の半導体装置となる。また、第2、第3の
実施例のように半導体ウエハー32上で組み立ててもよ
い。第4の実施例では絶縁基材22にCu配線を施す必要が
なく、第1〜第3の実施例に比べ低コストにできるという
利点を有している。A fourth embodiment will be described with reference to FIGS. Figure 2
FIG. 4 is a cross-sectional view of the fourth embodiment. The difference from the first to third embodiments is that a portion that is a Cu wiring is made of a conductive resin. That is, the internal terminals 37 of the conductive adhesive are adhered to the posts of the conductive adhesive, and the external terminals 39 of the conductive adhesive are connected thereto from the wiring portions 38 of the conductive adhesive.
It is connected with. FIG. 25 is a bottom plan view of FIG. 24. External terminals 39 made of a conductive adhesive are arranged in a matrix on an insulating base material window 23 provided at a predetermined portion of the insulating base material 22.
FIG. 26 is an upper plan view of the AA cross section in FIG. On the insulating resin layer 28, an internal terminal 37 made of a conductive adhesive, a wiring portion 38 made of a conductive adhesive, and an external terminal 39 made of a conductive adhesive are formed and electrically connected. This is done by forming an insulating resin layer 18 on a peelable cover tape (not shown), forming a conductive adhesive post 17 in a hole processed by laser, etc. By stencil or screen printing using conductive adhesive,
An internal terminal 37, a wiring section 38, and an external terminal 39 are formed. FIG. 27 is a plan view of the lower side of the AA section in FIG. The insulating base 22 is provided with only the insulating base window 23, and there is no wiring here. The insulating base material 22 is applied to a predetermined position of the cover tape assembled up to the state of FIG. Semiconductor device. Also, as in the second and third embodiments, the semiconductor wafer 32 may be assembled. In the fourth embodiment, there is no need to provide Cu wiring on the insulating base material 22, and there is an advantage that the cost can be reduced as compared with the first to third embodiments.

【００３１】第5の実施例を図28〜図31を用いて説明す
る。図28は第5の実施例の断面図である。第1の実施例と
の違いは絶縁性樹脂層18が半導体チップ1の外側に張り
出し、同様に配線部20、外部端子21、絶縁基材22もチッ
プ1の外側に張り出していること、ならびに張り出した
部分の絶縁性樹脂層18の上に金属などで加工された補強
板40が装着され、半導体チップ1と補強板40の間を封止
材41で充填していることである。図29は図28の下平面図
であり。絶縁基材22の所定部に設けられた絶縁基材窓23
に外部端子21がマトリックス状に形成されている。図30
は図28のA−A断面の下側の平面図である。内部端子19は
絶縁基材22の平面上において内部端子19の列の外側と内
側に配置されている外部端子21と配線部20により電気的
に接続されており、外部端子21は内部端子19よりも広い
ピッチでマトリックス状に配置されている。図31は図28
のA−A断面の上側の平面図である。絶縁樹脂層18の平面
上の内部に導電性接着剤のポスト17が配置されている。The fifth embodiment will be described with reference to FIGS. FIG. 28 is a sectional view of the fifth embodiment. The difference from the first embodiment is that the insulating resin layer 18 extends outside the semiconductor chip 1, and similarly, the wiring portion 20, the external terminals 21, and the insulating base material 22 also extend outside the chip 1, and That is, a reinforcing plate 40 made of metal or the like is mounted on the insulating resin layer 18 in the above-mentioned portion, and the space between the semiconductor chip 1 and the reinforcing plate 40 is filled with a sealing material 41. FIG. 29 is a bottom plan view of FIG. Insulating base material window 23 provided at a predetermined portion of insulating base material 22
The external terminals 21 are formed in a matrix. Fig. 30
FIG. 29 is a plan view of the lower side of the AA cross section in FIG. 28. The internal terminals 19 are electrically connected to the external terminals 21 arranged outside and inside the row of the internal terminals 19 on the plane of the insulating base material 22 by the wiring portion 20, and the external terminals 21 are Are also arranged in a matrix at a wide pitch. FIG. 31 is FIG. 28
3 is a plan view of the upper side of the AA cross section of FIG. A post 17 made of a conductive adhesive is arranged inside a plane of the insulating resin layer 18.

【００３２】第5の実施例の製造方法を以下に述べる。
図30の状態の配線テープは図5、図6に示した第1の実施
例と同様であり、配線パターンが異なるだけである。ま
た、この上への絶縁樹脂層18および導電性接着剤のポス
ト17の形成方法も図7〜図１２に示した第１の実施例と
同様であり、導電性接着剤のポスト１７の絶縁樹脂層18
の平面上の位置が異なるだけである。次に、ここまで組
み立てられた状態のテープに半導体チップ1と補強板40
を搭載し、加熱、加圧手段により同時に接着接続をす
る。そして、半導体チップ1と補強板40の間の隙間を封
止材41、例えば液状の熱硬化性樹脂により封止して、ま
た、加熱手段により硬化させる。最後に絶縁基材22の搬
送部(図示せず)や吊り部(図示せず)を除去して第5の実
施例による半導体装置が完成する。The manufacturing method of the fifth embodiment will be described below.
The wiring tape in the state of FIG. 30 is the same as that of the first embodiment shown in FIGS. 5 and 6, except for the wiring pattern. The method of forming the insulating resin layer 18 and the conductive adhesive post 17 thereon is also the same as that of the first embodiment shown in FIGS. Tier 18
Only the position on the plane is different. Next, the semiconductor chip 1 and the reinforcing plate 40 are attached to the tape thus assembled.
Is mounted and simultaneously connected by heating and pressing means. Then, a gap between the semiconductor chip 1 and the reinforcing plate 40 is sealed with a sealing material 41, for example, a liquid thermosetting resin, and is cured by a heating means. Finally, the transfer section (not shown) and the suspension section (not shown) of the insulating base material 22 are removed to complete the semiconductor device according to the fifth embodiment.

【００３３】第5の実施例では、外部端子21を半導体チ
ップ1の外側にも配置できるため、ピン数の多い製品で
もピッチを狭くせずに実装ができ、実装基板の配線が容
易なため、低コストの実装基板の使用が可能となる。ま
た、補強板40により、半導体チップ1の外側の外部端子2
1も平面を保て、封止材41により補強板40と半導体チッ
プ1は強固に接着されるので、半導体チップ1の内側と外
側の外部端子21は全体で平面が保て、実装しやすい半導
体装置となる。In the fifth embodiment, since the external terminals 21 can be arranged outside the semiconductor chip 1, even a product having a large number of pins can be mounted without reducing the pitch, and the wiring of the mounting board is easy. It is possible to use a low-cost mounting board. Further, the external terminals 2 outside the semiconductor chip 1 are provided by the reinforcing plate 40.
1 also keeps a flat surface, and the reinforcing plate 40 and the semiconductor chip 1 are firmly adhered to each other by the encapsulating material 41. Device.

【００３４】第6の実施例を図32を用いて説明する。第5
の実施例との違いは補強板40を用いず、半導体チップ1
の上面と側面ならびに絶縁性樹脂層18の上面を封止材41
で一括して覆っていることである。これは、図30に記載
の配線テープに絶縁性樹脂層18ならびに導電性接着剤17
を形成した後、半導体チップ1のみを加熱加圧して搭載
する。その後で、封止用金型(図示せず)を用いて配線テ
ープの外枠(図示せず)を固定するとともに封止材を注入
し、所定部を封止する。封止材は通常の半導体パッケー
ジに用いられるトランスファモールド用のエポキシ複合
材料などを用いればよい。第6の実施例では第5の実施例
に比べ、生産数の多いときに高能率化と低コスト化を図
りやすい。A sixth embodiment will be described with reference to FIG. number 5
The difference from the embodiment is that the reinforcing plate 40 is not used and the semiconductor chip 1
The upper surface and side surfaces of the insulating resin layer 18 and the upper surface of the
That is to cover all at once. This is because the wiring tape shown in FIG.
After the formation, only the semiconductor chip 1 is mounted by heating and pressing. Thereafter, an outer frame (not shown) of the wiring tape is fixed using a sealing mold (not shown), and a sealing material is injected to seal a predetermined portion. As a sealing material, an epoxy composite material for transfer molding used for a normal semiconductor package may be used. In the sixth embodiment, as compared with the fifth embodiment, it is easier to achieve higher efficiency and lower cost when the number of products is large.

【００３５】第7の実施例を図33に示す。第5の実施例と
の違いは内部端子19から配線部20が半導体チップ1の外
側に伸び、外部端子21はすべて半導体チップ1の外側に
形成されていることである。このような外部端子19の配
列の場合、少ない列数で非常に多くの外部端子を設ける
ことができるので、第5の実施例に比べ、実装がさらに
容易で実装基板の配線も楽になり、低コストの実装基板
の使用が可能になる。また、第6の実施例と同様の構造
にもできることは言うまでもない。FIG. 33 shows a seventh embodiment. The difference from the fifth embodiment is that the wiring portion 20 extends from the internal terminal 19 to the outside of the semiconductor chip 1, and the external terminals 21 are all formed outside the semiconductor chip 1. In the case of such an arrangement of the external terminals 19, a very large number of external terminals can be provided with a small number of columns, so that the mounting is easier and the wiring of the mounting board is easier than in the fifth embodiment, and The use of a cost-effective mounting substrate becomes possible. Needless to say, a structure similar to that of the sixth embodiment can be used.

【００３６】これまでに述べた半導体装置を基板実装す
るときの実施例を図34〜図42に示す。図34は第8の実施
例であり、第1から第3の実施例による半導体装置をはん
だバンプ42を用いて実装基板6の上の電極7に搭載したと
きの断面図である。第1の実施例の場合には、図14の工
程の後に、はんだボールあるいははんだペーストをマス
クなどを使って半導体装置の外部端子21の上に搭載し、
リフローにより溶融させて外部端子21と接合する。半導
体装置の外部端子21はCuで形成され、必要に応じてAuや
Ni/Auめっきが施されてあり、はんだと強固な接合がで
きる。また、第2の実施例の場合は図16の工程の後、第3
の実施例の場合は図22の工程の後にウエハー上ではんだ
バンプ42を形成し、その後で個別の半導体装置に分離す
る。なお、導電性接着材のポスト17および絶縁性樹脂層
18はすでに硬化を完了した熱硬化性樹脂であり、はんだ
バンプ形成時の高温でも溶融はせず、機能に変化はな
い。図34において、導電性接着剤のポスト17、ならびに
絶縁性樹脂層18の厚さが厚い場合には、はんだバンプ42
の高さと併せて、半導体チップ1と実装基板6との距離を
長くできるので、絶縁樹脂層18の材質は弾性率の大きい
安価な材料を用いても実装後の信頼性の確保が容易でア
ンダーフィルの必要はない。また、半導体装置の高さを
低くする必要がある場合は、絶縁樹脂層18を薄くして、
ここに低弾性率の材料を用いることにより、実装後の信
頼性の確保ができ、アンダーフィルの必要がない。実装
後にリペアが必要な場合は局部加熱により、はんだバン
プ42を溶かし、半導体装置を取り外せばよい。FIGS. 34 to 42 show an embodiment in which the semiconductor device described above is mounted on a substrate. FIG. 34 shows the eighth embodiment, and is a cross-sectional view when the semiconductor device according to the first to third embodiments is mounted on the electrode 7 on the mounting substrate 6 using the solder bumps. In the case of the first embodiment, after the process of FIG. 14, solder balls or solder paste is mounted on the external terminals 21 of the semiconductor device using a mask or the like,
It is melted by reflow and joined to the external terminal 21. The external terminals 21 of the semiconductor device are formed of Cu, and Au or
Ni / Au plating is applied to enable strong bonding with solder. In the case of the second embodiment, after the step of FIG.
In the case of this embodiment, the solder bumps 42 are formed on the wafer after the step shown in FIG. 22, and then separated into individual semiconductor devices. The conductive adhesive post 17 and the insulating resin layer
Reference numeral 18 denotes a thermosetting resin which has already been cured, does not melt even at a high temperature at the time of forming a solder bump, and does not change its function. In FIG. 34, when the conductive adhesive post 17 and the insulating resin layer 18 are thick, the solder bump 42
And the distance between the semiconductor chip 1 and the mounting board 6 can be lengthened, so that even if an inexpensive material having a high elastic modulus is used as the material of the insulating resin layer 18, it is easy to secure the reliability after mounting, and There is no need for a fill. When it is necessary to reduce the height of the semiconductor device, the insulating resin layer 18 is thinned,
By using a material having a low elastic modulus here, reliability after mounting can be ensured, and there is no need for underfill. If repair is required after mounting, the solder bumps 42 may be melted by local heating, and the semiconductor device may be removed.

【００３７】図35は第9の実施例であり、第1から第3の
実施例による半導体装置を導電性接着剤バンプ43を用い
て実装基板6の上の電極7に搭載したときの断面図であ
る。導電性接着剤バンプ43もAgフレークなどを含有した
熱硬化性の樹脂である。第1の実施例の場合には、図14
の工程の後に、導電性接着剤バンプ43をステンシルある
いはスクリーン印刷などにより半導体装置の外部端子21
の上に塗布し、加熱硬化させる。また、第2の実施例の
場合は図16の工程の後、第3の実施例の場合は図２２の
工程の後に半導体ウエハー３２上でこの作業を行う。一
方、基板実装時には図35において実装基板上の電極 7の
上に導電性接着剤のペースト(図示せず)を塗布してお
き、半導体装置にあらかじめ形成した硬化完了した導電
性接着剤バンプ43を重ねて、実装基板6を加熱し、導電
性接着剤のペーストを硬化させて接続が完了する。第9
の実施例では、導電性接着剤を用いて実装するので、は
んだバンプ42を用いる第8の実施例に比べて接続時の温
度を90℃程度低くでき、耐熱性を必要としない安価な実
装基板を使用できる。また、第8の実施例と同様の理由
により実装後のアンダーフィルの必要はない。FIG. 35 shows a ninth embodiment, in which the semiconductor device according to the first to third embodiments is mounted on the electrode 7 on the mounting substrate 6 using the conductive adhesive bump 43. It is. The conductive adhesive bump 43 is also a thermosetting resin containing Ag flake or the like. In the case of the first embodiment, FIG.
After the step (c), the conductive adhesive bumps 43 are formed on the external terminals 21 of the semiconductor device by stencil or screen printing.
And heat-cured. In the case of the second embodiment, this operation is performed on the semiconductor wafer 32 after the step of FIG. 16, and in the case of the third embodiment, after the step of FIG. On the other hand, at the time of board mounting, a conductive adhesive paste (not shown) is applied on the electrodes 7 on the mounting board in FIG. 35, and the cured conductive adhesive bump 43 formed in advance on the semiconductor device is applied. Once again, the mounting substrate 6 is heated and the paste of the conductive adhesive is cured to complete the connection. 9th
In this embodiment, since the mounting is performed using a conductive adhesive, the temperature at the time of connection can be lowered by about 90 ° C. as compared with the eighth embodiment using the solder bumps 42, and an inexpensive mounting board that does not require heat resistance. Can be used. Also, there is no need for underfill after mounting for the same reason as in the eighth embodiment.

【００３８】図36は第10の実施例であり、第4の実施例
による半導体装置を導電性接着剤バンプ43を用いて実装
基板6の上の電極7に搭載したときの断面図である。この
場合、半導体装置には導電性接着剤による外部端子39が
設けられており、導電性接着剤バンプ43とは強固に接続
するため、第9の実施例に比べ接続信頼性が向上する。FIG. 36 shows a tenth embodiment, and is a cross-sectional view when the semiconductor device according to the fourth embodiment is mounted on the electrodes 7 on the mounting substrate 6 using the conductive adhesive bumps 43. In this case, since the semiconductor device is provided with the external terminals 39 made of a conductive adhesive and is firmly connected to the conductive adhesive bumps 43, connection reliability is improved as compared with the ninth embodiment.

【００３９】図37は第11の実施例であり、第5の実施例
による半導体装置をはんだバンプ42を用いて実装基板6
の上の電極7に搭載したときの断面図である。この場
合、第8の実施例に比べ広いピッチで実装ができ、直径
の大きいはんだバンプ42を用いることができるので、実
装基板43から半導体チップ1までの距離を高くできる、
実装後の接続信頼性が向上する。また、実装基板上電極
のピッチも広いので実装基板6の配線が楽になり、低コ
ストの実装基板6の使用が可能となる。FIG. 37 shows an eleventh embodiment, in which the semiconductor device according to the fifth embodiment is mounted on a mounting substrate 6 by using solder bumps 42.
FIG. 4 is a cross-sectional view when mounted on an electrode 7 above. In this case, mounting can be performed at a wider pitch than in the eighth embodiment, and since the solder bumps 42 having a large diameter can be used, the distance from the mounting substrate 43 to the semiconductor chip 1 can be increased.
Connection reliability after mounting is improved. Further, since the pitch of the electrodes on the mounting substrate is wide, the wiring of the mounting substrate 6 becomes easy, and the low-cost mounting substrate 6 can be used.

【００４０】図38は第12の実施例であり、第5の実施例
による半導体装置を導電性接着剤バンプ43を用いて実装
基板6の上の電極7に搭載したときの断面図である。この
場合、第11の実施例に比べて接続温度を下げられ、耐熱
性を必要としない安価な実装基板を使用できる。FIG. 38 shows a twelfth embodiment, and is a cross-sectional view when the semiconductor device according to the fifth embodiment is mounted on the electrodes 7 on the mounting substrate 6 using the conductive adhesive bumps 43. In this case, an inexpensive mounting board which can lower the connection temperature and does not require heat resistance can be used as compared with the eleventh embodiment.

【００４１】図39は第13の実施例であり、第6の実施例
による半導体装置をはんだバンプ42を用いて実装基板6
の上の電極7に搭載したときの断面図である。実装時の
効果は第11の実施例と同様である。FIG. 39 shows a thirteenth embodiment, in which the semiconductor device according to the sixth embodiment is mounted on a mounting substrate 6 by using solder bumps 42.
FIG. 4 is a cross-sectional view when mounted on an electrode 7 above. The effect at the time of mounting is the same as that of the eleventh embodiment.

【００４２】図40は第14の実施例であり、第6の実施例
による半導体装置を導電性接着剤バンプ43を用いて実装
基板6の上の電極7に搭載したときの断面図である。実装
時の効果は第12の実施例と同様である。FIG. 40 is a cross-sectional view of a fourteenth embodiment, in which the semiconductor device according to the sixth embodiment is mounted on the electrodes 7 on the mounting substrate 6 using the conductive adhesive bumps 43. The effect at the time of mounting is the same as that of the twelfth embodiment.

【００４３】図41は第15の実施例であり、第7の実施例
による半導体装置をはんだバンプ42を用いて実装基板6
の電極7に搭載したときの断面図である。この場合、第1
1の実施例に比べ同じ端子数でも少ない列数のはんだバ
ンプの数で済むので、実装基板6の配線がさらに楽にな
り、低コストの実装基板の使用が可能になる。FIG. 41 shows a fifteenth embodiment, in which a semiconductor device according to the seventh embodiment is mounted on a mounting substrate 6 by using solder bumps 42.
FIG. 4 is a cross-sectional view when mounted on the electrode 7 of FIG. In this case, the first
Since the number of solder bumps in the number of rows is small even with the same number of terminals as in the first embodiment, the wiring of the mounting board 6 is further facilitated, and a low-cost mounting board can be used.

【００４４】図42は第16の実施例であり、第7の実施例
による半導体装置を導電性接着剤バンプ43を用いて実装
基板6の上の電極7に搭載してときの断面図である。この
場合、第15の実施例に比べて接続温度を下げられ、耐熱
性を必要としない安価な実装基板を使用できる。FIG. 42 is a cross-sectional view of the sixteenth embodiment, in which the semiconductor device according to the seventh embodiment is mounted on the electrode 7 on the mounting substrate 6 using the conductive adhesive bump 43. . In this case, the connection temperature can be reduced as compared with the fifteenth embodiment, and an inexpensive mounting board that does not require heat resistance can be used.

【００４５】[0045]

【発明の効果】本発明によれば、半導体装置を実装した
場合であっても高信頼にチップ電極と再配線層との距離
を確保できるので、半導体装置の信頼性を向上させる事
ができる。According to the present invention, even when a semiconductor device is mounted, the distance between the chip electrode and the rewiring layer can be ensured with high reliability, so that the reliability of the semiconductor device can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施例の半導体装置の断面図。FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

【図２】図1の下平面図。FIG. 2 is a lower plan view of FIG. 1;

【図３】図1のA−A断面の下平面図。FIG. 3 is a lower plan view taken along the line AA of FIG. 1;

【図４】図1のA−A断面の上平面図。FIG. 4 is an upper plan view of a section AA in FIG. 1;

【図５】本発明の第1の実施例の半導体装置に用いる配
線テープの上平面図。FIG. 5 is a top plan view of a wiring tape used in the semiconductor device according to the first embodiment of the present invention.

【図６】図5のB−B断面図。FIG. 6 is a sectional view taken along line BB of FIG. 5;

【図７】図5の配線テープに絶縁性樹脂層を形成した状
態の上平面図。FIG. 7 is an upper plan view showing a state in which an insulating resin layer is formed on the wiring tape of FIG. 5;

【図８】図7のB−B断面図。8 is a sectional view taken along the line BB of FIG. 7;

【図９】図7に絶縁性樹脂窓を形成した状態の上平面
図。FIG. 9 is an upper plan view showing a state where an insulating resin window is formed in FIG. 7;

【図１０】図9のB−Ｂ断面図。FIG. 10 is a sectional view taken along line BB of FIG. 9;

【図１１】図９に導電性接着剤のポストを形成した状態
の上平面図。FIG. 11 is an upper plan view of FIG. 9 in which a post of a conductive adhesive is formed.

【図１２】図11のB−B断面図。FIG. 12 is a sectional view taken along line BB of FIG. 11;

【図１３】本発明の第1の実施例に用いる半導体チップ
の電極形成面の平面図。FIG. 13 is a plan view of an electrode formation surface of a semiconductor chip used in the first embodiment of the present invention.

【図１４】図12の組立テープと図13の半導体チップを加
熱加圧接着している工程の断面図。14 is a sectional view of a step of bonding the assembly tape of FIG. 12 and the semiconductor chip of FIG. 13 under heat and pressure.

【図１５】本発明の第2の実施例でウエハー上にパター
ン形成済みテープを位置合わせした状態の断面図。FIG. 15 is a cross-sectional view showing a state where a patterned tape is positioned on a wafer in a second embodiment of the present invention.

【図１６】図15の次の工程でウエハー上にパターン形成
済みテープを加圧加熱圧着している状態の断面図。FIG. 16 is a cross-sectional view showing a state in which a tape on which a pattern has been formed is pressure-heated and pressed on a wafer in the next step of FIG. 15;

【図１７】第2の実施例によるウエハー切断後の半導体
装置の断面図。FIG. 17 is a cross-sectional view of the semiconductor device after cutting the wafer according to the second embodiment.

【図１８】本発明の第3の実施例でウエハー上に絶縁性
樹脂層を形成した状態の断面図。FIG. 18 is a sectional view showing a state in which an insulating resin layer is formed on a wafer according to a third embodiment of the present invention.

【図１９】図18に絶縁樹脂窓を形成した状態の断面図。FIG. 19 is a sectional view showing a state where an insulating resin window is formed in FIG. 18;

【図２０】図19に導電性接着剤のポストを形成した状態
の断面図。FIG. 20 is a cross-sectional view showing a state where a post of a conductive adhesive is formed in FIG. 19;

【図２１】図20に配線済みテープを位置合わせした状態
の断面図。FIG. 21 is a cross-sectional view of the state in which the wired tape is aligned with FIG. 20;

【図２２】図21で両者を熱圧着した状態の断面図。FIG. 22 is a cross-sectional view of a state where both are thermocompression-bonded in FIG. 21;

【図２３】第３の実施例によるウエハー切断後の半導体
装置の断面図。FIG. 23 is a cross-sectional view of the semiconductor device after cutting the wafer according to the third embodiment.

【図２４】本発明の第4の実施例による半導体装置の断
面図。FIG. 24 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.

【図２５】図24の下平面図。FIG. 25 is a lower plan view of FIG. 24;

【図２６】図24のA−A断面の上平面図。FIG. 26 is an upper plan view of a section AA in FIG. 24;

【図２７】図24のA−A断面の下平面図。FIG. 27 is a bottom plan view taken along the line AA of FIG. 24;

【図２８】本発明の第5の実施例による半導体装置の断
面図。FIG. 28 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.

【図２９】図28の下平面図。FIG. 29 is a lower plan view of FIG. 28;

【図３０】図28のA−A断面の下平面図。FIG. 30 is a lower plan view of the section AA in FIG. 28;

【図３１】図28のA−A断面の上平面図。FIG. 31 is an upper plan view of an AA cross section in FIG. 28;

【図３２】本発明の第6の実施例による半導体装置の断
面図。FIG. 32 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention.

【図３３】本発明の第7の実施例による半導体装置の断
面図。FIG. 33 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention.

【図３４】本発明の第8の実施例による半導体装置の断
面図。FIG. 34 is a sectional view of a semiconductor device according to an eighth embodiment of the present invention.

【図３５】本発明の第9の実施例による半導体装置の基
板実装状態の断面図。FIG. 35 is a sectional view of a semiconductor device according to a ninth embodiment of the present invention when mounted on a substrate;

【図３６】本発明の第10の実施例による半導体装置の基
板実装状態の断面図。FIG. 36 is a sectional view of a semiconductor device according to a tenth embodiment of the present invention when mounted on a substrate;

【図３７】本発明の第11の実施例による半導体装置の基
板実装状態の断面図。FIG. 37 is a sectional view of a semiconductor device according to an eleventh embodiment of the present invention when mounted on a substrate;

【図３８】本発明の第12の実施例による半導体装置の基
板実装状態の断面図。FIG. 38 is a sectional view of a semiconductor device according to a twelfth embodiment of the present invention, which is mounted on a substrate;

【図３９】本発明の第13の実施例による半導体装置の基
板実装状態の断面図。FIG. 39 is a sectional view of a semiconductor device according to a thirteenth embodiment of the present invention when mounted on a substrate;

【図４０】本発明の第14の実施例による半導体装置の基
板実装状態の断面図。FIG. 40 is a sectional view of a semiconductor device according to a fourteenth embodiment of the present invention when mounted on a substrate;

【図４１】本発明の第15の実施例による半導体装置の基
板実装状態の断面図。FIG. 41 is a sectional view of a semiconductor device according to a fifteenth embodiment of the present invention, which is mounted on a substrate;

【図４２】本発明の第16の実施例による半導体装置の基
板実装状態の断面図。FIG. 42 is a sectional view of a semiconductor device according to a sixteenth embodiment of the present invention when mounted on a substrate;

【符号の説明】[Explanation of symbols]

1 ・・・半導体チップ 2 ・・・チップ上電極 3 ・・・有機絶縁層保護膜 4 ・・・第1の重合可能な導電性接着剤層 5 ・・・重合可能な導電性接着剤バンプ 6 ・・・実装基板 7 ・・・基板上電極 8 ・・・第2の重合可能な導電性接着剤層 9 ・・・導電性接着剤 10・・・導電性弾性樹脂バンプ 11・・・熱可塑性絶縁性樹脂 12・・・熱可塑性導電性接着剤バンプ 13・・・チップキャリア 14・・・チップキャリア上電極 15・・・バンプ 16・・・熱可塑性導電性接着剤層 17・・・導電性接着剤のポスト 18・・・絶縁性樹脂層 19・・・内部端子 20・・・配線部 21・・・外部端子 22・・・絶縁基材 23・・・絶縁基材窓 24・・・絶縁基材の外枠 25・・・スプロケットホール 26・・・スリット 27・・・吊り部 28・・・絶縁樹脂窓 29・・・上型加熱加圧治具 30・・・下型加熱加圧治具 31・・・第1の実施例による半導体装置 32・・・半導体ウエハー 33・・・所定パターン形成済ウエハー対応テープ 34・・・第2の実施例による半導体装置 35・・・ウエハー対応配線済テープ 36・・・第3の実施例による半導体装置 37・・・導電性接着剤による内部端子 38・・・導電性接着剤による配線部 39・・・導電性接着剤による外部端子 40・・・補強板 41・・・封止材 42・・・はんだバンプ 43・・・導電性接着剤バンプ 1 ・ ・ ・ Semiconductor chip 2 ・ ・ ・ Electrode on chip 3 ・ ・ ・ Protective film for organic insulating layer 4 ・ ・ ・ First polymerizable conductive adhesive layer 5 ・ ・ ・ Polymerizable conductive adhesive bump 6・ ・ ・ Mounting substrate 7 ・ ・ ・ Electrode on substrate 8 ・ ・ ・ Second polymerizable conductive adhesive layer 9 ・ ・ ・ Conductive adhesive 10 ・ ・ ・ Conductive elastic resin bump 11 ・ ・ ・ Thermoplastic Insulating resin 12 ・ ・ ・ Thermoplastic conductive adhesive bump 13 ・ ・ ・ Chip carrier 14 ・ ・ ・ Chip carrier upper electrode 15 ・ ・ ・ Bump 16 ・ ・ ・ Thermoplastic conductive adhesive layer 17 ・ ・ ・ Conductivity Adhesive post 18 ・ ・ ・ Insulating resin layer 19 ・ ・ ・ Internal terminal 20 ・ ・ ・ Wiring part 21 ・ ・ ・ External terminal 22 ・ ・ ・ Insulating substrate 23 ・ ・ ・ Insulating substrate window 24 ・ ・ ・ Insulating Base frame 25 ・ ・ ・ Sprocket hole 26 ・ ・ ・ Slit 27 ・ ・ ・ Suspension 28 ・ ・ ・ Insulating resin window 29 ・ ・ ・ Upper heating and pressing jig 30 ・ ・ ・ Bottom Mold heating / pressing jig 31 ... Semiconductor device according to first embodiment 32 ... Semiconductor wafer 33 ... Tape corresponding to wafer with predetermined pattern formed 34 ... Semiconductor device according to second embodiment 35 ...・ Wired tape for wafer 36 ・ ・ ・ Semiconductor device according to the third embodiment 37 ・ ・ ・ Internal terminal made of conductive adhesive 38 ・ ・ ・ Wiring part made of conductive adhesive 39 ・ ・ ・ Outer part made of conductive adhesive Terminal 40: Reinforcement plate 41: Sealant 42: Solder bump 43: Conductive adhesive bump

───────────────────────────────────────────────────── フロントページの続き (72)発明者 佐藤 正昭 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所生産技術研究所内 (72)発明者 角田 重晴 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所生産技術研究所内 (72)発明者 吉見 健二 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所生産技術研究所内 Ｆターム(参考） 5F044 QQ03 QQ04  ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Masaaki Sato 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd. Production Technology Research Laboratory (72) Inventor Shigeharu Kakuda 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Kenji Yoshimi, Hitachi, Ltd. (72) Inventor Kenji Yoshimi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term, Hitachi Manufacturing Co., Ltd. F-term (reference) 5F044 QQ03 QQ04

Claims (8)

【特許請求の範囲】[Claims] 【請求項１】複数個の電極を有する半導体チップと、該
電極と電気的に接続されたポストと該ポストと電気的に
接続された配線とを有する絶縁性樹脂層と、該絶縁性樹
脂層に形成された配線と電気的に接続された外部電極と
を備えた半導体装置であって、該ポストが熱硬化性の導
電性接着剤で構成されたことを特徴とする半導体装置。An insulating resin layer having a semiconductor chip having a plurality of electrodes, a post electrically connected to the electrodes, and a wiring electrically connected to the posts, and the insulating resin layer 2. A semiconductor device comprising: a wiring formed on the substrate; and an external electrode electrically connected to the post, wherein the post is made of a thermosetting conductive adhesive. 【請求項２】前記絶縁樹脂層が熱硬化性樹脂であること
を特徴とする請求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein said insulating resin layer is a thermosetting resin. 【請求項３】前記絶縁性樹脂層が前記半導体チップより
も外側に張り出すように形成され、その絶縁性樹脂層の
張り出した領域に金属板が形成されたことを特徴とする
請求項１または２記載の半導体装置。3. The semiconductor device according to claim 1, wherein the insulating resin layer is formed so as to protrude outside the semiconductor chip, and a metal plate is formed in a region where the insulating resin layer protrudes. 3. The semiconductor device according to 2. 【請求項４】前記絶縁性樹脂層が前記半導体チップより
も外側に張り出すように形成され、少なくともその絶縁
性樹脂層の張り出した領域と前記半導体チップとを熱硬
化性の封止材で封止したことを特徴とする請求項１また
は２記載の半導体装置。4. The semiconductor device according to claim 1, wherein the insulating resin layer is formed so as to extend outside the semiconductor chip, and at least a region where the insulating resin layer extends and the semiconductor chip are sealed with a thermosetting sealing material. 3. The semiconductor device according to claim 1, wherein said semiconductor device is stopped. 【請求項５】前記外部電極が熱硬化性の導電性接着剤の
バンプで形成されたことを特徴とする請求項１〜４のい
ずれかに記載の半導体装置。5. The semiconductor device according to claim 1, wherein said external electrode is formed of a bump made of a thermosetting conductive adhesive. 【請求項６】複数個の電極を有する半導体チップと、該
電極と電気的に接続された熱硬化性の導電性接着剤で形
成されたポストと該ポストと電気的に接続された配線と
を有する熱硬化性の樹脂で形成された絶縁性樹脂層と、
該絶縁性樹脂層に形成された配線と電気的に接続された
外部電極とを備えた半導体装置の製造方法であって、 配線と該配線と電気的に接続されたポストとを有する絶
縁性樹脂層と半導体チップとを位置合わせする工程と、 該半導体チップの有する電極と前記絶縁性樹脂層の有す
るポストとを接続した状態で前記ポストと前記絶縁性樹
脂層とを熱硬化させる工程とを備えたことを特徴とする
半導体装置の製造方法。6. A semiconductor chip having a plurality of electrodes, a post made of a thermosetting conductive adhesive electrically connected to the electrodes, and a wiring electrically connected to the posts. An insulating resin layer formed of a thermosetting resin having
What is claimed is: 1. A method of manufacturing a semiconductor device, comprising: a wiring formed on an insulating resin layer; and an external electrode electrically connected to the wiring, the insulating resin having a wiring and a post electrically connected to the wiring. Aligning the layer and the semiconductor chip; and thermally curing the post and the insulating resin layer in a state where the electrode of the semiconductor chip is connected to the post of the insulating resin layer. A method for manufacturing a semiconductor device. 【請求項７】前記絶縁性樹脂層と前記ポストとをそれぞ
れの樹脂及び導電性接着剤がＢステージの状態で位置合
わせすることを特徴とする請求項6記載の半導体装置の
製造方法。7. The method for manufacturing a semiconductor device according to claim 6, wherein the insulating resin layer and the post are aligned with each other in a state where the resin and the conductive adhesive are at a B stage. 【請求項８】前記絶縁性樹脂層は、テープ上に配線を形
成する工程と、該配線を形成したテープ上にＢステージ
の状態で絶縁性樹脂層を形成する工程と、該絶縁性樹脂
層の所定の位置を貫通させてポスト用のスルーホールを
形成する工程と、該スルーホールに熱硬化性の導電性接
着剤をＢステージの状態で充填させてポストを形成する
工程と、該ポストと電気的に接続されかつ前記外部電極
と電気的に接続するための配線を形成する工程とを用い
て形成されることを特徴とする請求項６または７記載の
半導体装置の製造方法。8. An insulating resin layer comprising: a step of forming a wiring on a tape; a step of forming an insulating resin layer in a B stage state on the tape on which the wiring is formed; Forming a post through-hole by penetrating a predetermined position of the post, filling the through-hole with a thermosetting conductive adhesive in a B-stage state to form a post, Forming a wiring that is electrically connected and electrically connected to the external electrode. The method of manufacturing a semiconductor device according to claim 6, wherein:
JP6957099A 1999-03-16 1999-03-16 Semiconductor device and its manufacture Pending JP2000269256A (en)

Priority Applications (1)

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JP6957099A JP2000269256A (en) 1999-03-16 1999-03-16 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6957099A JP2000269256A (en) 1999-03-16 1999-03-16 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JP2000269256A true JP2000269256A (en) 2000-09-29

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002168715A (en) * 2000-12-04 2002-06-14 Toyoda Mach Works Ltd Semiconductor pressure detector and assembling method thereof
US6696317B1 (en) 1999-11-04 2004-02-24 Nec Electronics Corporation Method of manufacturing a flip-chip semiconductor device with a stress-absorbing layer made of thermosetting resin
JP2010067654A (en) * 2008-09-09 2010-03-25 Sony Corp Manufacturing method of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6696317B1 (en) 1999-11-04 2004-02-24 Nec Electronics Corporation Method of manufacturing a flip-chip semiconductor device with a stress-absorbing layer made of thermosetting resin
US6767761B2 (en) 1999-11-04 2004-07-27 Nec Electronics Corporation Method of manufacturing a flip-chip semiconductor device with a stress-absorbing layer made of thermosetting resin
JP2002168715A (en) * 2000-12-04 2002-06-14 Toyoda Mach Works Ltd Semiconductor pressure detector and assembling method thereof
JP2010067654A (en) * 2008-09-09 2010-03-25 Sony Corp Manufacturing method of semiconductor device

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