JP2000262052A - Drive circuit of synchronously rectifying single crystal forward converter - Google Patents
Drive circuit of synchronously rectifying single crystal forward converterInfo
- Publication number
- JP2000262052A JP2000262052A JP11058867A JP5886799A JP2000262052A JP 2000262052 A JP2000262052 A JP 2000262052A JP 11058867 A JP11058867 A JP 11058867A JP 5886799 A JP5886799 A JP 5886799A JP 2000262052 A JP2000262052 A JP 2000262052A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor switch
- terminal
- fet
- turned
- transformer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Rectifiers (AREA)
- Dc-Dc Converters (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、同期整流方式のス
イッチング電源、特に1石フォワードコンバータのドラ
イブ回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous rectification type switching power supply, and more particularly to a drive circuit for a single-rock forward converter.
【0002】[0002]
【従来の技術】従来の同期整流方式の1石フォワードコ
ンバータの回路構成は図3に示す通りである。主トラン
ス105の1次コイルには半導体スイッチ103が直列
接続してあり、直流電源104から入力する直流電力は
制御回路106からのQゲート信号を入力する半導体ス
イッチ103のスイッチングにより、高周波電力に変換
される。主トランス105の2次出力回路には整流用半
導体スイッチ101と還流用半導体スイッチ102が設
けてあって、入力した高周波電力を同期整流して直流電
力に変換し、さらに、リアクタ108とコンデンサ10
9より成るフィルタ回路を介して平滑化された直流電力
を送出する。また、還流用半導体スイッチ102のゲー
ト端子とソース端子の間にはドライブ・トランス107
の1次コイルが接続してあり、その2次コイルは制御回
路106からのゲート信号(Qゲート信号と反対位相)
により接地するように構成してある。2. Description of the Related Art FIG. 3 shows a circuit configuration of a conventional synchronous rectification type single-rock forward converter. A semiconductor switch 103 is connected in series to the primary coil of the main transformer 105. DC power input from a DC power supply 104 is converted into high-frequency power by switching of the semiconductor switch 103 inputting a Q gate signal from a control circuit 106. Is done. The secondary output circuit of the main transformer 105 is provided with a rectifying semiconductor switch 101 and a circulating semiconductor switch 102. The input high-frequency power is synchronously rectified and converted into DC power.
9 and sends out the smoothed DC power through the filter circuit. A drive transformer 107 is connected between the gate terminal and the source terminal of the semiconductor switch 102 for return.
Are connected, and the secondary coil is connected to a gate signal (opposite phase to the Q gate signal) from the control circuit 106.
It is configured to be grounded.
【0003】[0003]
【発明が解決しようとする課題】上述した回路構成によ
ると、還流用半導体スイッチがオンしている期間、ドラ
イブ・トランス107をドライブさせているので、制御
ドライブ損失も大きく、ドライブ・トランスも大きくせ
ざるを得なかった。According to the above-described circuit configuration, the drive transformer 107 is driven while the return semiconductor switch is on, so that a large control drive loss and a large drive transformer are required. I had no choice.
【0004】[0004]
【課題を解決するための手段】本発明は、上述した従来
方式の同期整流方式の1石フォワードコンバータのドラ
イブ回路の欠点を解消するためになされたものであり、
主トランスのフライバック電圧を利用してオンとなる還
流用半導体スイッチに蓄積されたエネルギーを、整流用
半導体スイッチがオンとなる前にドライブ・トランスを
介してディスチャージさせるようにした。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the drive circuit of the conventional synchronous rectification type single-rock forward converter.
The energy stored in the return semiconductor switch, which is turned on using the flyback voltage of the main transformer, is discharged via the drive transformer before the rectification semiconductor switch is turned on.
【0005】[0005]
【発明の実施の形態】本発明の実施例を図面を参照しな
がら説明する。図1は本発明による実施例の回路構成を
示すブロック図である。直流電源4の両極間にはコンデ
ンサ5が並列接続してあり、さらに、主トランス6の1
次コイルとメインスイッチであるFET1との直列回路
が並列接続してある。主トランス6の2次コイルには、
整流用半導体スイッチであるFET3と還流用半導体ス
イッチであるFET2が接続してあり、リアクタ107
と並列コンデンサ18より成るフィルタ回路が出力回路
に接続してある。Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a circuit configuration of an embodiment according to the present invention. A capacitor 5 is connected in parallel between the two poles of the DC power supply 4.
A series circuit of the next coil and the main switch FET1 is connected in parallel. The secondary coil of the main transformer 6 has
The rectifying semiconductor switch FET3 and the refluxing semiconductor switch FET2 are connected, and the reactor 107
And a filter circuit comprising a parallel capacitor 18 is connected to the output circuit.
【0006】FET3のドレイン端子にアノード端子を
接続したダイオード9のカソード端子はFET2のゲー
ト端子に接続してある。ダイオード9のカソード端子と
FET2のゲート端子との接続点と、FET2とFET
3におけるソース端子同士の接続点との間には、ドライ
ブ・トランス8の2次コイルが並列接続してある。ま
た、ドライブ・トランス8の1次コイルは、ソース端子
を接地したFET16のゲート端子を介して制御回路7
に接続してある。The cathode terminal of the diode 9 whose anode terminal is connected to the drain terminal of the FET 3 is connected to the gate terminal of the FET 2. A connection point between the cathode terminal of the diode 9 and the gate terminal of the FET 2;
3, a secondary coil of the drive transformer 8 is connected in parallel between the source terminal and the connection point. The primary coil of the drive transformer 8 is connected to the control circuit 7 via the gate terminal of the FET 16 whose source terminal is grounded.
Connected to
【0007】ドライブ・トランス8の2次コイルには、
P形トランジスタ10が並列接続してあり、P形トラン
ジスタ10のコレクタ端子とベース端子との間に接続し
た抵抗13と、ベース端子にアノード端子を接続しカソ
ード端子をP形トランジスタ10のエミッタ端子に接続
したダイオード11とがP形トランジスタ10のコレク
タ端子とエミッタ端子間に並列接続してある。さらに、
ダイオード11のアノード端子にカソード端子を接続し
てアノード端子を抵抗14の一端に接続したダイオード
12と、抵抗14の他端にカソード端子を接続しアノー
ド端子をP形トランジスタ10のコレクタ端子に接続し
たダイオード15が設けてあり、抵抗14とダイオード
15より成る直列回路はドライブ・トランス8の2次コ
イルに並列接続してある。また、FET2のゲート端子
とP形トランジスタ10のエミッタ端子との間にはFE
T2のゲート端子にアノード端子を接続したダイオード
19が設けてある。The secondary coil of the drive transformer 8 includes:
A P-type transistor 10 is connected in parallel, a resistor 13 connected between the collector terminal and the base terminal of the P-type transistor 10, an anode terminal connected to the base terminal, and a cathode terminal connected to the emitter terminal of the P-type transistor 10. The connected diode 11 is connected in parallel between the collector terminal and the emitter terminal of the P-type transistor 10. further,
A diode 12 having a cathode terminal connected to the anode terminal of the diode 11 and an anode terminal connected to one end of the resistor 14, and a cathode terminal connected to the other end of the resistor 14 and an anode terminal connected to the collector terminal of the P-type transistor 10. A diode 15 is provided, and a series circuit including the resistor 14 and the diode 15 is connected in parallel to a secondary coil of the drive transformer 8. An FE is connected between the gate terminal of the FET 2 and the emitter terminal of the P-type transistor 10.
A diode 19 having an anode terminal connected to the gate terminal of T2 is provided.
【0008】次に、本発明によるドライブ回路の動作に
ついて説明する。メインスイッチ1がオフとなると主ト
ランス6の2次コイルにフライバッグ電圧が発生し、ダ
イオード9を介してFET2のゲート端子に入力する。
フライバック電圧をゲート端子に入力したFET2はそ
の入力容量Ciss によってオンし続ける。フライバック
電圧によりFET2がオンした後、Qゲート信号と反対
位相のゲート信号によりFET16がオンとなり、ドラ
イブ・トランス8の2次コイルにもFET2のゲート・
ソース間電圧が印加される。但し、フライバック電圧を
ドライブ・トランス8からのドライブ電圧より高く設定
することでドライブ・トランス8からのパワーは伝達さ
れず、制御損失は少なくなる。一方、制御回路からのゲ
ート信号(Qゲート信号と反対位相)がオフした場合、
P形トランジスタ10のベース電位が落ちてオンとなる
ので、FET2のゲート・ソース間はショートとなり、
ディスチャージされる。Next, the operation of the drive circuit according to the present invention will be described. When the main switch 1 is turned off, a flyback voltage is generated in the secondary coil of the main transformer 6 and input to the gate terminal of the FET 2 via the diode 9.
The FET 2 that has input the flyback voltage to the gate terminal continues to be turned on by the input capacitance Ciss. After the FET2 is turned on by the flyback voltage, the FET16 is turned on by the gate signal having the opposite phase to the Q gate signal, and the secondary coil of the drive transformer 8 is connected to the gate of the FET2.
A source-to-source voltage is applied. However, by setting the flyback voltage higher than the drive voltage from the drive transformer 8, the power from the drive transformer 8 is not transmitted, and the control loss is reduced. On the other hand, when the gate signal (opposite phase to the Q gate signal) from the control circuit is turned off,
Since the base potential of the P-type transistor 10 drops and turns on, the gate-source of the FET 2 is short-circuited,
Discharged.
【0009】図2に、本発明による半導体スイッチの動
作波形を示す。制御回路7から出力されるQゲート信号
波形と反対位相のゲート信号波形(2つのゲート信号間
にはデッドタイムが設けてある)およびメインスイッチ
1のドレイン・ソース間電圧波形とFET2のゲート信
号波形を示している。FET3のゲート信号波形は制御
回路7から出力されるQゲート信号波形と同一であるか
ら、FET3がオンとなる前にFET2はオフとなって
いることが判る。また、ダイオード19の設置により、
ドライブ・トランス8の電圧に関係なくドライブはフラ
イバック電圧を利用し、ディスチャージはドライブ・ト
ランス8によりP形トランジスタ10をオンにすること
により行う。FIG. 2 shows operation waveforms of the semiconductor switch according to the present invention. A gate signal waveform having a phase opposite to the Q gate signal waveform output from the control circuit 7 (a dead time is provided between two gate signals), a drain-source voltage waveform of the main switch 1 and a gate signal waveform of the FET 2 Is shown. Since the gate signal waveform of the FET 3 is the same as the Q gate signal waveform output from the control circuit 7, it is understood that the FET 2 is turned off before the FET 3 is turned on. Also, by installing the diode 19,
The drive uses the flyback voltage regardless of the voltage of the drive transformer 8, and the discharge is performed by turning on the P-type transistor 10 by the drive transformer 8.
【0010】[0010]
【発明の効果】以上説明したように、本発明による同期
整流方式の1石フォワードコンバータは、還流用半導体
スイッチのゲート回路にダイオードが設けてあり、ま
た、還流用半導体スイッチがオンとなったときのエネル
ギーをディスチャージできるドライブ・トランスが還流
用半導体スイッチのゲート〜ソース間に並列接続してあ
る。主トランスのフライバック電圧を利用して還流用半
導体スイッチをドライブさせ、ディスチャージをドライ
ブ・トランスにて行うことにより、制御ドライブ電力を
減少させることができるばかりでなく、メイントランス
のフライバック電圧を還流用半導体スイッチのCissに
て吸収できるので、主トランスの1次側に設けるスナバ
回路の小型化が可能である。As described above, the synchronous rectification type single-pole forward converter according to the present invention has a diode provided in the gate circuit of the freewheeling semiconductor switch, and operates when the freewheeling semiconductor switch is turned on. Is connected in parallel between the gate and the source of the semiconductor switch for reflux. By driving the return semiconductor switch using the flyback voltage of the main transformer and performing the discharge with the drive transformer, not only the control drive power can be reduced, but also the flyback voltage of the main transformer is returned. Therefore, the size of the snubber circuit provided on the primary side of the main transformer can be reduced.
【図1】本発明による実施例を示すブロック図。FIG. 1 is a block diagram showing an embodiment according to the present invention.
【図2】波形図。FIG. 2 is a waveform diagram.
【図3】従来方式の同期整流方式の1石フォワードコン
バータの回路構成を示すブロック図。FIG. 3 is a block diagram showing a circuit configuration of a conventional synchronous rectification single-rock forward converter.
1,2,3,16 FET 4 直流電源 5,18 コンデンサ 6,8 トランス 7 制御回路 10 トランジスタ 9,11,12,15,19 ダイオード 13,14 抵抗 17 リアクタ 1,2,3,16 FET 4 DC power supply 5,18 Capacitor 6,8 Transformer 7 Control circuit 10 Transistor 9,11,12,15,19 Diode 13,14 Resistance 17 Reactor
Claims (1)
イッチを2次出力回路に設けて同期整流を行う同期整流
方式の1石フォワードコンバータにおいて、 整流用半導体スイッチのドレイン端子にアノード端子を
接続したダイオードのカソード端子を還流用半導体スイ
ッチのゲート端子に接続すると共に、還流用半導体スイ
ッチのゲート端子とダイオードのカソード端子との接続
点と、整流用半導体スイッチと還流用半導体スイッチの
ソース端子同士の接続点との間に並列接続した2次コイ
ル、および制御回路からのゲート信号によって制御され
るソース端子を接地した半導体スイッチを設けた1次コ
イルより成るドライブ・トランスを設け、 制御回路が出力するメインスイッチのゲート信号により
整流用半導体スイッチがオンとなる前に、主トランスの
フライバック電圧によってオンとなった還流用半導体ス
イッチのエネルギーを、ドライブ・トランスを介してデ
ィスチャージさせるようにしたことを特徴とする同期整
流方式の1石フォワードコンバータのドライブ回路。1. A synchronous rectification type single-switch forward converter in which a rectifying semiconductor switch and a refluxing semiconductor switch are provided in a secondary output circuit to perform synchronous rectification, wherein a diode having an anode terminal connected to a drain terminal of the rectifying semiconductor switch. And the connection point between the gate terminal of the semiconductor switch for reflux and the cathode terminal of the diode, and the connection point between the source terminals of the semiconductor switch for rectification and the semiconductor switch for reflux. A drive transformer comprising a primary coil provided with a secondary coil connected in parallel between the power supply and a semiconductor switch grounded at a source terminal controlled by a gate signal from a control circuit, and a main switch output by the control circuit Before the rectifying semiconductor switch is turned on by the gate signal of The energy of the reflux semiconductor switch which becomes on by the transformer of the flyback voltage, 1 transistor forward converter of the driving circuit of a synchronous rectification type, characterized in that through the drive transformer has to be discharged.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP05886799A JP3478328B2 (en) | 1999-03-05 | 1999-03-05 | Drive circuit for single rectifier type forward converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP05886799A JP3478328B2 (en) | 1999-03-05 | 1999-03-05 | Drive circuit for single rectifier type forward converter |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2000262052A true JP2000262052A (en) | 2000-09-22 |
JP3478328B2 JP3478328B2 (en) | 2003-12-15 |
Family
ID=13096695
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP05886799A Expired - Fee Related JP3478328B2 (en) | 1999-03-05 | 1999-03-05 | Drive circuit for single rectifier type forward converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3478328B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009171827A (en) * | 2008-01-18 | 2009-07-30 | Lite-On Technology Corp | Driving circuit and power converter incorporated therein |
-
1999
- 1999-03-05 JP JP05886799A patent/JP3478328B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009171827A (en) * | 2008-01-18 | 2009-07-30 | Lite-On Technology Corp | Driving circuit and power converter incorporated therein |
JP4642096B2 (en) * | 2008-01-18 | 2011-03-02 | 光寶科技股▲ふん▼有限公司 | Drive circuit and power converter incorporating the drive circuit |
Also Published As
Publication number | Publication date |
---|---|
JP3478328B2 (en) | 2003-12-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6373727B1 (en) | Synchronous rectification in a flyback converter | |
JP2758137B2 (en) | Power converter | |
KR100729058B1 (en) | External driving circuit for bridge type synchronous rectification | |
US5590032A (en) | Self-synchronized drive circuit for a synchronous rectifier in a clamped-mode power converter | |
US6304463B1 (en) | Single-ended forward converter circuit with quasi-optimal resetting for synchronous rectification | |
US5818704A (en) | Synchronizing/driving circuit for a forward synchronous rectifier | |
US6839246B1 (en) | Self-driving circuit for a DC/DC converter | |
JPH1189232A (en) | Switching electric power supply equipment | |
EP3723258A1 (en) | Switching converter | |
US7400519B2 (en) | Switching power supply | |
CN110719019B (en) | Secondary active clamping control circuit | |
JP3515675B2 (en) | Synchronous rectification circuit | |
JP3328671B2 (en) | Synchronous rectification circuit, forward converter including the same, and synchronous rectification method | |
JP3478328B2 (en) | Drive circuit for single rectifier type forward converter | |
JPH07245946A (en) | Semiconductor switching circuit | |
JPH10136646A (en) | Synchronous rectifier | |
JP2751961B2 (en) | DC / DC converter | |
JP2882472B2 (en) | Power supply circuit using power insulated gate type FET | |
JP2001037214A (en) | Power source circuit | |
JPH07337006A (en) | Synchronous rectifier circuit | |
GB2313495A (en) | Synchronous/driving circuit for a synchronous rectifier | |
JPH09285116A (en) | Power supply circuit | |
JP2003333845A (en) | Switching power supply | |
JPH05344718A (en) | Drive circuit of power converter | |
JPH10146052A (en) | Synchronized rectifier |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20030826 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081003 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081003 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091003 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091003 Year of fee payment: 6 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091003 Year of fee payment: 6 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091003 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101003 Year of fee payment: 7 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101003 Year of fee payment: 7 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101003 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111003 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111003 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121003 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121003 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131003 Year of fee payment: 10 |
|
LAPS | Cancellation because of no payment of annual fees |