JP2000221539A - Array substrate, method for correcting array substrate, and liquid crystal display device - Google Patents
Array substrate, method for correcting array substrate, and liquid crystal display deviceInfo
- Publication number
- JP2000221539A JP2000221539A JP1974999A JP1974999A JP2000221539A JP 2000221539 A JP2000221539 A JP 2000221539A JP 1974999 A JP1974999 A JP 1974999A JP 1974999 A JP1974999 A JP 1974999A JP 2000221539 A JP2000221539 A JP 2000221539A
- Authority
- JP
- Japan
- Prior art keywords
- pixel
- electrode
- shielding film
- gate
- light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、歩留まりを向上し
たアレイ基板、アレイ基板の修正方法および液晶表示装
置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate having improved yield, a method of repairing the array substrate, and a liquid crystal display device.
【０００２】[0002]
【従来の技術】従来、この種の液晶表示装置としては、
たとえば特開平９−４３６３１号公報に記載の構成が知
られている。この特開平９−４３６３１号公報には、ゲ
ート線および信号線を絶縁膜を介して直交させて配設
し、これらゲート線および信号線の交点近傍に薄膜トラ
ンジスタを設け、この薄膜トランジスタで画素電極を制
御している。また、画素電極の一部とゲート線とを絶縁
膜を介して対向させて配設し、これら画素電極およびゲ
ート線との間で補助容量を形成している。2. Description of the Related Art Conventionally, as this type of liquid crystal display device,
For example, a configuration described in JP-A-9-43631 is known. In Japanese Patent Application Laid-Open No. 9-43631, a gate line and a signal line are arranged orthogonally via an insulating film, a thin film transistor is provided near an intersection of the gate line and the signal line, and a pixel electrode is controlled by the thin film transistor. are doing. Further, a part of the pixel electrode and the gate line are arranged to face each other with an insulating film interposed therebetween, and an auxiliary capacitance is formed between the pixel electrode and the gate line.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記特
開平９−４３６３１号公報に記載の液晶表示装置では、
絶縁膜にピンホールが生ずるなどしてゲート線と画素電
極との間で短絡が生ずると、画素電極にゲート線の電位
が印加され、該当する画素電極が滅点となってしまい点
欠点が生ずる問題を有している。However, in the liquid crystal display device described in JP-A-9-43631,
If a short circuit occurs between the gate line and the pixel electrode due to the occurrence of a pinhole in the insulating film, for example, the potential of the gate line is applied to the pixel electrode, and the corresponding pixel electrode becomes a dark spot, causing a point defect. Have a problem.
【０００４】本発明は、上記問題点に鑑みなされたもの
で、点欠点が生じても容易に修正できるアレイ基板、ア
レイ基板の修正方法および液晶表示装置を提供すること
を目的とする。SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide an array substrate, a method of repairing an array substrate, and a liquid crystal display device that can be easily corrected even if a point or defect occurs.
【０００５】[0005]
【課題を解決するための手段】本発明は、複数のゲート
線と、これら複数のゲート線に電気的に絶縁した状態で
交差して設けられた複数の信号線と、これらゲート線お
よび信号線の交点近傍に設けられた薄膜トランジスタ
と、画素を形成する画素部、および、前記ゲート線と対
向し補助容量を形成し前記画素部と電気的に切り離し可
能な補助容量電極部を有し、前記薄膜トランジスタによ
り制御されマトリクス状に配設された画素電極と、この
画素電極の画素部に少なくとも一部が対向して設けられ
この画素部との間で補助容量を形成可能で前記ゲート線
に絶縁した状態で配設され導電性を有する遮光膜と、前
記ゲート電極および前記遮光膜の少なくともいずれか一
方に電気的に絶縁して配設され、処理により前記ゲート
電極および前記遮光膜を電気的に接続する接続膜とを具
備したものである。According to the present invention, there are provided a plurality of gate lines, a plurality of signal lines provided so as to intersect with the plurality of gate lines while being electrically insulated from the plurality of gate lines, and a plurality of the gate lines and the signal lines. A thin film transistor provided in the vicinity of the intersection of the pixel portion, a pixel portion forming a pixel, and an auxiliary capacitance electrode portion facing the gate line to form an auxiliary capacitance and being electrically separated from the pixel portion, A pixel electrode arranged in a matrix controlled by the above, and a state in which an auxiliary capacitor can be formed between the pixel portion and at least a part thereof, and is insulated from the gate line. A light-shielding film having conductivity and disposed at least one of the gate electrode and the light-shielding film so as to be electrically insulated from the gate electrode and the light-shielding film by processing. The is obtained; and a connection layer that electrically connects.
【０００６】そして、ゲート線と画素電極の補助容量電
極部とが短絡している場合に、画素電極の画素部と補助
容量電極とを電気的に切り離し、ゲート電極と遮光膜と
を接続膜を介して電気的に接続し、遮光膜および画素電
極の画素部で補助容量を形成することにより、ゲート線
と画素電極の補助容量電極とが短絡していても、該当す
る画素電極にゲート線から電位が印加されることを防止
するとともに遮光膜と画素電極の画素部との間で補助容
量を形成することにより該当する画素電極を通常どおり
動作させることができ、点欠点が生ずることを防止す
る。When the gate line and the auxiliary capacitance electrode portion of the pixel electrode are short-circuited, the pixel portion of the pixel electrode and the auxiliary capacitance electrode are electrically separated from each other, and the gate electrode and the light shielding film are connected to each other by a connection film. Even if the gate line and the auxiliary capacitance electrode of the pixel electrode are short-circuited, the corresponding pixel electrode is connected to the corresponding pixel electrode by forming an auxiliary capacitance in the pixel portion of the light shielding film and the pixel electrode. By preventing the potential from being applied and forming an auxiliary capacitor between the light-shielding film and the pixel portion of the pixel electrode, the corresponding pixel electrode can be operated as usual, thereby preventing the occurrence of point defects. .
【０００７】また、ゲート線と遮光膜とは同層に形成さ
れているもので、遮光膜の形成のための工程の増加を防
止する。The gate line and the light-shielding film are formed in the same layer, thereby preventing an increase in steps for forming the light-shielding film.
【０００８】さらに、ゲート線および画素電極の補助容
量電極部の対向面積と、遮光膜および画素電極の画素部
の対向面積とは等しいもので、補助容量電極部を画素部
から電気的に切り離して画素電極の画素部と遮光部との
間で補助容量を形成しても補助容量は変わらないので、
点欠点がなくなる。Further, the opposing areas of the gate line and the auxiliary capacitance electrode portion of the pixel electrode are equal to the opposing areas of the light shielding film and the pixel portion of the pixel electrode, and the auxiliary capacitance electrode portion is electrically separated from the pixel portion. Even if an auxiliary capacitance is formed between the pixel portion of the pixel electrode and the light shielding portion, the auxiliary capacitance does not change.
There are no point defects.
【０００９】[0009]
【発明の実施の形態】以下、本発明の液晶表示装置の一
実施の形態を図面を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the liquid crystal display device of the present invention will be described below with reference to the drawings.
【００１０】図１および図２に示すように、１は透光性
を有する絶縁基板としてのガラス基板で、このガラス基
板１にはアルミニウム(Ａｌ)あるいはタンタル(Ｔａ)製
の平行な複数のゲート線２が配設され、これらゲート線
２にはゲート電極３が一体的に形成されているととも
に、同層にいわゆるフローティングブラックマトリクス
である遮光膜４がゲート線２に対して直交する方向に形
成されている。また、これらゲート線２およびゲート電
極３上には、窒化シリコン(ＳｉＮx )あるいは酸化シリ
コン（ＳｉＯx ）のゲート絶縁膜５が全面に形成されて
いる。As shown in FIGS. 1 and 2, reference numeral 1 denotes a glass substrate serving as a light-transmitting insulating substrate. The glass substrate 1 has a plurality of parallel gates made of aluminum (Al) or tantalum (Ta). Lines 2 are provided. Gate electrodes 3 are formed integrally with these gate lines 2, and a light-shielding film 4, which is a so-called floating black matrix, is formed in the same layer in a direction orthogonal to the gate lines 2. Have been. On these gate lines 2 and gate electrodes 3, a gate insulating film 5 of silicon nitride (SiN x ) or silicon oxide (SiO x ) is formed on the entire surface.
【００１１】さらに、ゲート絶縁膜５のゲート電極３上
には、ソース領域6aおよびドレイン領域6bを有する多結
晶シリコンなどの半導体層６が形成され、半導体層６の
中央上部にはチャネル層７が形成されている。Further, a semiconductor layer 6 such as polycrystalline silicon having a source region 6a and a drain region 6b is formed on the gate electrode 3 of the gate insulating film 5, and a channel layer 7 is formed on the upper center of the semiconductor layer 6. Is formed.
【００１２】また、ゲート絶縁膜５上には、ＩＴＯ（In
dium Tin Oxide）の画素電極８がマトリクス状に配設さ
れ、この画素電極８は周縁の対向する２辺がゲート絶縁
膜５を介して遮光膜４の一部と対向して形成された画素
部8aと、この画素部8aから幅狭の切離部8bを介して同様
にゲート絶縁膜５を介してゲート線２と対向して形成さ
れた補助容量電極部8cとを有している。なお、遮光膜４
および画素部8aの対向している面積と、ゲート線２およ
び補助容量電極部8cの対向している面積はほぼ等しく設
定され、ゲート線２および遮光膜４は同層に形成されて
いるため画素部8aおよび補助容量電極8cとの距離は等し
いので、いずれも容量が等しい。On the gate insulating film 5, ITO (In
A pixel portion 8 is formed in a matrix shape. The pixel electrode 8 is formed such that two opposing sides of the periphery of the pixel electrode 8 face a part of the light shielding film 4 via the gate insulating film 5. 8a, and an auxiliary capacitance electrode portion 8c formed opposite to the gate line 2 via the gate insulating film 5 through a narrow separation portion 8b from the pixel portion 8a. The light shielding film 4
The opposing area of the pixel portion 8a and the opposing area of the gate line 2 and the auxiliary capacitance electrode portion 8c are set substantially equal to each other, and the gate line 2 and the light shielding film 4 are formed in the same layer. Since the distance between the portion 8a and the auxiliary capacitance electrode 8c is equal, both have the same capacitance.
【００１３】さらに、半導体層６のソース領域6a上には
チタン（Ｔｉ）あるいはモリブデン（Ｍｏ）などの金属
のソース電極11が形成され、ドレイン領域6b上および画
素電極８の一部の上部にかけてドレイン電極12が形成さ
れ、ソース電極11はゲート線２と直交する複数本の信号
線13と一体に形成され、ゲート線２および遮光膜４に対
向して接続膜15が形成され、薄膜トランジスタ16を形成
している。そして、これらの表面に保護膜17が形成さ
れ、アレイ基板18を形成している。Further, a source electrode 11 made of a metal such as titanium (Ti) or molybdenum (Mo) is formed on the source region 6a of the semiconductor layer 6, and the drain electrode extends over the drain region 6b and a part of the pixel electrode 8. An electrode 12 is formed, a source electrode 11 is formed integrally with a plurality of signal lines 13 orthogonal to the gate line 2, a connection film 15 is formed facing the gate line 2 and the light shielding film 4, and a thin film transistor 16 is formed. are doing. Then, a protective film 17 is formed on these surfaces to form an array substrate 18.
【００１４】また、同様にガラス基板21上に、カラーフ
ィルタ22およびブラックマトリクス23が形成され、これ
らカラーフィルタ22およびブラックマトリクス23上には
ＩＴＯなどの対向電極24が形成され、対向基板25を形成
している。Similarly, a color filter 22 and a black matrix 23 are formed on a glass substrate 21, and a counter electrode 24 such as ITO is formed on the color filter 22 and the black matrix 23 to form a counter substrate 25. are doing.
【００１５】そして、アレイ基板18の表面に配光膜26を
形成し、対向基板25の表面にも配光膜27を形成し、これ
ら配光膜26，27を対向させて周囲を封着し、アレイ基板
18および対向基板25間に液晶を挟持して液晶層28を形成
し、液晶表示装置を形成する。A light distribution film 26 is formed on the surface of the array substrate 18, a light distribution film 27 is also formed on the surface of the counter substrate 25, and the light distribution films 26 and 27 are opposed to each other to seal the periphery. , Array substrate
A liquid crystal is sandwiched between 18 and the counter substrate 25 to form a liquid crystal layer 28, thereby forming a liquid crystal display device.
【００１６】つぎに、上記実施の形態の動作について説
明する。Next, the operation of the above embodiment will be described.
【００１７】ゲート線２および信号線13の信号に従いそ
れぞれ対応する薄膜トランジスタ14が動作され、この薄
膜トランジスタ14により画素電極８が制御され液晶層28
を駆動して表示し、補助容量電極部8cとゲート線２との
間の補助容量で表示している状態を維持する。In accordance with the signals on the gate line 2 and the signal line 13, the corresponding thin film transistors 14 are operated.
Are driven and displayed, and the state of display by the auxiliary capacitance between the auxiliary capacitance electrode portion 8c and the gate line 2 is maintained.
【００１８】しかしながら、たとえばゲート線２と画素
電極８の補助容量電極部8cとの間のゲート絶縁膜５にピ
ンホールが生じているとリーク電流が生じて短絡し、画
素電極８とゲート線２の電位が等しくなり、ノーマリー
ホワイトの状態では滅点として表示され、点欠点を生じ
てしまい不良画素となる。However, if a pinhole is formed in the gate insulating film 5 between the gate line 2 and the auxiliary capacitance electrode portion 8c of the pixel electrode 8, for example, a leak current is generated and a short circuit occurs. Are equal to each other, and are displayed as dark spots in a normally white state, resulting in a point defect and a defective pixel.
【００１９】そこで、補助容量電極部8cと画素部8aとを
接続している切離部8bをレーザなどにより切断し、画素
部8aとゲート線２とを電気的に開放し、ゲート線２の電
位と画素部8aの電位とを異ならせ、点欠点でない状態に
する。さらに、この状態では補助容量がなくなり液晶層
28に加わる電位が変化するために中間調では周囲と異な
る輝度となるので、図３に示すように、接続膜15および
ゲート線２と接続膜15および遮光膜４とにレーザを照射
して電気的に接続し、遮光膜４と画素部8aの対向する部
分で補助容量を形成する。なお、遮光膜４および画素部
8aの対向している面積と、ゲート線２および補助容量電
極部8cの対向している面積はほぼ等しく設定され、ゲー
ト線２および遮光膜４は同層に形成されているため画素
部8aおよび補助容量電極8cとの距離は等しいので、いず
れも容量が等しく、表示に悪影響を与えることを防止で
き、不良画素を良点化して歩留まりの向上を図ることが
できる。Then, the separation portion 8b connecting the storage capacitor electrode portion 8c and the pixel portion 8a is cut by a laser or the like, and the pixel portion 8a and the gate line 2 are electrically opened, and the gate line 2 is disconnected. The potential and the potential of the pixel portion 8a are made different from each other, so that the pixel portion 8a is not in a point defect. Furthermore, in this state, the auxiliary capacitance is lost and the liquid crystal layer
Since the potential applied to the pixel 28 changes, the brightness becomes different from that of the surroundings in the halftone. Therefore, as shown in FIG. And a storage capacitor is formed at a portion where the light shielding film 4 and the pixel portion 8a face each other. The light shielding film 4 and the pixel portion
The facing area of the gate line 2a and the facing area of the gate line 2 and the auxiliary capacitance electrode section 8c are set substantially equal to each other. Since the gate line 2 and the light shielding film 4 are formed in the same layer, the pixel section 8a and the Since the distances from the auxiliary capacitance electrodes 8c are equal, the capacitances are the same in each case, and it is possible to prevent the display from being adversely affected, improve defective pixels, and improve the yield.
【００２０】[0020]
【発明の効果】本発明によれば、ゲート線と画素電極の
補助容量電極部とが短絡している場合に、画素電極の画
素部と補助容量電極とを電気的に切り離し、ゲート電極
と遮光膜とを接続膜を介して電気的に接続し、遮光膜お
よび画素電極の画素部で補助容量を形成することによ
り、ゲート線と画素電極の補助容量電極とが短絡してい
ても、該当する画素電極にゲート線から電位が印加され
ることを防止するとともに遮光膜と画素電極の画素部と
の間で補助容量を形成することにより該当する画素電極
を通常どおり動作させることができ、点欠点が生ずるこ
とを防止できる。According to the present invention, when the gate line and the auxiliary capacitance electrode of the pixel electrode are short-circuited, the pixel portion of the pixel electrode and the auxiliary capacitance electrode are electrically separated from each other, and the gate electrode is shielded from light. The film is electrically connected via a connection film, and an auxiliary capacitance is formed by the light-shielding film and the pixel portion of the pixel electrode, so that even if the gate line and the auxiliary capacitance electrode of the pixel electrode are short-circuited, By preventing the potential from being applied from the gate line to the pixel electrode and forming an auxiliary capacitor between the light-shielding film and the pixel portion of the pixel electrode, the corresponding pixel electrode can be operated as usual, and the Can be prevented from occurring.
【図１】本発明の一実施の形態のアレイ基板を示す平面
図である。FIG. 1 is a plan view showing an array substrate according to an embodiment of the present invention.
【図２】同上液晶表示装置を図１のＡ−Ａ断面に対応し
て示す断面図である。FIG. 2 is a cross-sectional view showing the liquid crystal display device corresponding to the AA cross section in FIG.
【図３】同上図１のＢ−Ｂ断面に対応して示す断面図で
ある。FIG. 3 is a sectional view corresponding to a section taken along line BB of FIG. 1;
２ ゲート線 ４ 遮光膜 ８ 画素電極 8a 画素部 8c 補助容量電極部 13 信号線 14 薄膜トランジスタ 15 接続膜 18 アレイ基板 25 対向基板 28 液晶層 2 Gate line 4 Shielding film 8 Pixel electrode 8a Pixel portion 8c Auxiliary capacitance electrode portion 13 Signal line 14 Thin film transistor 15 Connection film 18 Array substrate 25 Opposite substrate 28 Liquid crystal layer
Claims (6)
て設けられた複数の信号線と、 これらゲート線および信号線の交点近傍に設けられた薄
膜トランジスタと、 画素を形成する画素部、および、前記ゲート線と対向し
補助容量を形成し前記画素部と電気的に切り離し可能な
補助容量電極部を有し、前記薄膜トランジスタにより制
御されマトリクス状に配設された画素電極と、 この画素電極の画素部に少なくとも一部が対向して設け
られこの画素部との間で補助容量を形成可能で前記ゲー
ト線に絶縁した状態で配設され導電性を有する遮光膜
と、 前記ゲート電極および前記遮光膜の少なくともいずれか
一方に電気的に絶縁して配設され、処理により前記ゲー
ト電極および前記遮光膜を電気的に接続する接続膜とを
具備したことを特徴とするアレイ基板。1. A plurality of gate lines, a plurality of signal lines provided to intersect with the plurality of gate lines in an electrically insulated state, and a thin film transistor provided near an intersection of the gate lines and the signal lines. And a pixel portion forming a pixel, and an auxiliary capacitance electrode portion facing the gate line and forming an auxiliary capacitance, which can be electrically separated from the pixel portion, and arranged in a matrix controlled by the thin film transistor. A pixel electrode and a pixel portion of the pixel electrode, at least a portion of which is provided so as to face the pixel portion, an auxiliary capacitance can be formed between the pixel electrode and the pixel portion, and the pixel electrode is electrically insulated from the gate line. A light-shielding film, and a contact that is electrically insulated and disposed on at least one of the gate electrode and the light-shielding film, and electrically connects the gate electrode and the light-shielding film by processing. Array substrate, characterized by comprising a membrane.
いることを特徴とする請求項１記載のアレイ基板。2. The array substrate according to claim 1, wherein the gate line and the light-shielding film are formed in the same layer.
部の対向面積と、遮光膜および画素電極の画素部の対向
面積とは等しいことを特徴とする請求項１または２記載
のアレイ基板。3. The array substrate according to claim 1, wherein a facing area of the gate line and the storage capacitor electrode portion of the pixel electrode is equal to a facing area of the light shielding film and the pixel portion of the pixel electrode.
線に電気的に絶縁した状態で交差して設けられた複数の
信号線と、これらゲート線および信号線の交点近傍に設
けられた薄膜トランジスタと、画素を形成する画素部、
および、前記ゲート線と対向し補助容量を形成し前記画
素部と電気的に切り離し可能な補助容量電極部を有し、
前記薄膜トランジスタにより制御されマトリクス状に配
設された画素電極と、この画素電極の画素部に少なくと
も一部が対向して設けられこの画素部との間で補助容量
を形成可能で前記ゲート線に絶縁した状態で配設され導
電性を有する遮光膜と、前記ゲート電極および前記遮光
膜の少なくともいずれか一方に電気的に絶縁して配設さ
れ、処理により前記ゲート電極および前記遮光膜を電気
的に接続する接続膜とを具備したアレイ基板の修正方法
であって、 前記ゲート線と前記画素電極の補助容量電極部との短絡
している場合に、前記画素電極の画素部と補助容量電極
とを電気的に切り離し、前記ゲート電極と前記遮光膜と
を接続膜を介して電気的に接続し、前記遮光膜および前
記画素電極の画素部で補助容量を形成することを特徴と
するアレイ基板の修正方法。4. A plurality of gate lines, a plurality of signal lines provided to intersect with the plurality of gate lines in an electrically insulated state, and a thin film transistor provided near an intersection of the gate lines and the signal lines. And a pixel portion forming a pixel,
And an auxiliary capacitance electrode portion facing the gate line to form an auxiliary capacitance and electrically disconnectable from the pixel portion;
A pixel electrode controlled by the thin film transistor and arranged in a matrix and at least a part of a pixel portion of the pixel electrode is provided so as to face the pixel portion, and an auxiliary capacitance can be formed between the pixel portion and the pixel portion. A light-shielding film having conductivity and disposed in a state in which the gate electrode and the light-shielding film are electrically insulated and disposed on at least one of the gate electrode and the light-shielding film. A method for repairing an array substrate comprising a connection film to be connected, wherein when the gate line and the auxiliary capacitance electrode portion of the pixel electrode are short-circuited, the pixel portion of the pixel electrode and the auxiliary capacitance electrode are connected to each other. Electrically disconnecting, electrically connecting the gate electrode and the light-shielding film through a connection film, and forming an auxiliary capacitance in the pixel portion of the light-shielding film and the pixel electrode. How to fix ray boards.
いることを特徴とする請求項４記載のアレイ基板の修正
方法。5. The method according to claim 4, wherein the gate line and the light-shielding film are formed in the same layer.
基板と、 このアレイ基板に対向して設けられた対向基板と、 これらアレイ基板および対向基板間に挟持された液晶層
とを具備したことを特徴とする液晶表示装置。6. An array substrate according to any one of claims 1 to 3, a counter substrate provided to face the array substrate, and a liquid crystal layer sandwiched between the array substrate and the counter substrate. A liquid crystal display device characterized by the above-mentioned.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1974999A JP2000221539A (en) | 1999-01-28 | 1999-01-28 | Array substrate, method for correcting array substrate, and liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1974999A JP2000221539A (en) | 1999-01-28 | 1999-01-28 | Array substrate, method for correcting array substrate, and liquid crystal display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000221539A true JP2000221539A (en) | 2000-08-11 |
Family
ID=12008003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1974999A Pending JP2000221539A (en) | 1999-01-28 | 1999-01-28 | Array substrate, method for correcting array substrate, and liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000221539A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010140052A (en) * | 1999-03-05 | 2010-06-24 | Semiconductor Energy Lab Co Ltd | Display device |
| CN104672421B (en) * | 2015-02-11 | 2017-06-06 | 黄山中泽新材料有限公司 | Compound oil ink binder polyurethane resin preparation method and intaglio printing compound oil ink |
-
1999
- 1999-01-28 JP JP1974999A patent/JP2000221539A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010140052A (en) * | 1999-03-05 | 2010-06-24 | Semiconductor Energy Lab Co Ltd | Display device |
| CN104672421B (en) * | 2015-02-11 | 2017-06-06 | 黄山中泽新材料有限公司 | Compound oil ink binder polyurethane resin preparation method and intaglio printing compound oil ink |
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