JP2000216330A - Stacked semiconductor device and its manufacture - Google Patents

Stacked semiconductor device and its manufacture

Info

Publication number
JP2000216330A
JP2000216330A JP11017134A JP1713499A JP2000216330A JP 2000216330 A JP2000216330 A JP 2000216330A JP 11017134 A JP11017134 A JP 11017134A JP 1713499 A JP1713499 A JP 1713499A JP 2000216330 A JP2000216330 A JP 2000216330A
Authority
JP
Japan
Prior art keywords
chip
chips
wiring
adhesive resin
electrically conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP11017134A
Other languages
Japanese (ja)
Inventor
Fumiaki Matsushima
文明 松島
Shuji Koeda
周史 小枝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP11017134A priority Critical patent/JP2000216330A/en
Publication of JP2000216330A publication Critical patent/JP2000216330A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PROBLEM TO BE SOLVED: To easily manufacture chip-on-chip structure where multiple IC are stacked by forming an electric continuity wiring from bonding pads to the end faces of chips, bonding and stacking the chips by means of adhesion resin layers and connecting all the chips stacked by an electric continuity wiring. SOLUTION: An electric continuity wiring 13 is formed by discharging a molten solder material from an ink jet head from respective bonding pads 12 to a cut part where wiring connection with the other IC chip 11 is assumed. Electron beam curing-type adhesion 14 is applied on the surface of a silicon wafer. The silicon wafer is cut and divided into each IC chip 11. IC having the electric functions of different types are similarly worked and overlapped. Electron beams are radiated and the IC chips 11 are bonded. Then, a continuity wiring 15 is formed by discharging a molten solder material from the ink jet head to the side part of an IC chip stack body where the IC chips 11 are overlapped.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体ＩＣチップを
積層化して形成される積層型ＩＣチップおよびその製造
方法に関する。The present invention relates to a laminated IC chip formed by laminating semiconductor IC chips and a method for manufacturing the same.

【０００２】[0002]

【従来の技術】従来より、実装密度の高い構造を実現す
るためにＩＣチップを積層するチップオンチップ構造が
提案されており、その際ＩＣチップ間の電気的接続にも
様々な提案がされている。例えば特開平８−２６４７１
２では図５に示されるようにＩＣチップ５１に形成され
た貫通したスルーホール５２により積層されたＩＣチッ
プが金属５３により電気的に接続される形態が提案され
ており、また特開平５−６３１３７も同様である。さら
には特許番号第２６０５９６８号では同一属性のあるボ
ンディングパッドの位置関係も考慮された形態がとられ
ている。2. Description of the Related Art Conventionally, a chip-on-chip structure in which IC chips are stacked in order to realize a structure having a high mounting density has been proposed. At that time, various proposals have been made for electrical connection between IC chips. I have. For example, JP-A-8-26471
In FIG. 2, as shown in FIG. 5, there is proposed a form in which IC chips stacked by penetrating through holes 52 formed in the IC chip 51 are electrically connected by a metal 53. The same is true for Further, Japanese Patent No. 2605968 takes a form in which the positional relationship between bonding pads having the same attribute is also considered.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら従来の方
法ではいずれも集積回路の形成されたＩＣチップもしく
はシリコンウエハーに貫通したスルーホールを形成する
点において容易ではない。すなわち、形成された集積回
路に何らダメージを与えることなくスルーホールを作製
することは困難が伴う。一方集積回路形成前のシリコン
ウエハーにあらかじめスルーホールを形成するなら集積
回路の形成に困難をきたすことが容易に予測される。However, any of the conventional methods is not easy in that a through hole is formed in an IC chip or a silicon wafer on which an integrated circuit is formed. That is, it is difficult to form a through hole without damaging the formed integrated circuit. On the other hand, if through holes are formed in advance on a silicon wafer before forming an integrated circuit, it is easily predicted that formation of an integrated circuit will be difficult.

【０００４】[0004]

【課題を解決するための手段】上記の従来技術の問題点
を解決するためのもので請求項１記載の積層型半導体装
置はＩＣチップの各ボンディングパッドからチップ端面
までに電気的導通配線が形成され、さらに該チップの全
面もしくは一部に接着性のある樹脂層が形成され、同様
に形成された電気的に別機能を持つ複数のチップが該樹
脂層により接着、積層され、さらに各チップ端面を横断
してなる電気的導通配線により積層された全チップが接
続されたことを特徴とする。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, the stacked semiconductor device according to the first aspect of the present invention has an electrically conductive wiring formed from each bonding pad of an IC chip to a chip end face. Further, an adhesive resin layer is formed on the entire surface or a part of the chip, and a plurality of similarly formed chips having different functions are bonded and laminated by the resin layer. , And all the stacked chips are connected by the electrically conductive wiring crossing the line.

【０００５】請求項２記載の積層型半導体装置の製造方
法は複数のＩＣチップが形成されたシリコンウエハーの
各チップ内のボンディングパッドから少なくとも各チッ
プ切断位置までに電気的導通配線を形成する第一の工
程、第一の工程を経たシリコンウエハーの電気的導通配
線形成面の全面もしくは一部に接着性のある樹脂層を形
成する第二の工程、第二の工程を経たウエハーを切断に
より個々のＩＣチップに分割する第三の工程、同様に形
成された電気的に別機能を持つＩＣチップが積層され、
接着性のある樹脂の硬化によって互いに接着にされる第
四の工程、積層された各ＩＣチップが第一の工程で作製
された電気的導通配線の端面同士で各ＩＣチップ端面を
横断する方向に電気的導通配線により接続される第五の
工程からなることを特徴とする。According to a second aspect of the present invention, there is provided a method of manufacturing a stacked semiconductor device, wherein an electrically conductive wiring is formed from a bonding pad in each chip of a silicon wafer having a plurality of IC chips formed thereon to at least each chip cutting position. Step, a second step of forming an adhesive resin layer on the entire surface or a part of the electrically conductive wiring forming surface of the silicon wafer after the first step, and cutting the wafer after the second step into individual parts. Third step of dividing into IC chips, similarly formed IC chips having electrically different functions are laminated,
The fourth step in which the laminated IC chips are adhered to each other by curing the adhesive resin, in a direction in which the laminated IC chips cross the IC chip end faces between the end faces of the electrically conductive wirings produced in the first step. The method is characterized in that the method includes a fifth step of connecting by electric conduction wiring.

【０００６】請求項３記載の積層型半導体装置の製造方
法は請求項２において電気的導通配線がインクジェット
方式で形成されることを特徴とする。According to a third aspect of the present invention, there is provided a method of manufacturing a stacked semiconductor device according to the second aspect, wherein the electrically conductive wiring is formed by an ink jet method.

【０００７】請求項４記載の積層型半導体装置の製造方
法は請求項２において電気的導通配線材料が金属もしく
は導電性粒子を含有する導電性樹脂から選ばれてなるこ
とを特徴とする。According to a fourth aspect of the present invention, there is provided a method for manufacturing a stacked semiconductor device according to the second aspect, wherein the electrically conductive wiring material is selected from a metal or a conductive resin containing conductive particles.

【０００８】請求項５記載の積層型半導体装置の製造方
法は請求項２において第四の工程のＩＣチップの接着樹
脂の硬化が一枚のチップを重ねる毎に行われるかもしく
は全ＩＣチップを重ねた後に一括して行われることを特
徴とする。According to a fifth aspect of the present invention, there is provided a method of manufacturing a stacked semiconductor device according to the second aspect, wherein the curing of the adhesive resin of the IC chip in the fourth step is performed every time one chip is stacked, or all IC chips are stacked. Is performed in a lump after the operation.

【０００９】請求項６記載の積層型半導体装置の製造方
法は請求項２において接着樹脂の硬化が熱硬化もしくは
電子線硬化でおこなわれることを特徴とする。According to a sixth aspect of the present invention, there is provided a method of manufacturing a stacked semiconductor device according to the second aspect, wherein the curing of the adhesive resin is performed by heat curing or electron beam curing.

【００１０】請求項７記載の積層型半導体装置の製造方
法は請求項２において接着性のある樹脂層を形成する第
二の工程が第三の工程のＩＣチップへの切断の後に行わ
れることを特徴とする。According to a seventh aspect of the present invention, there is provided a method of manufacturing a stacked semiconductor device according to the second aspect, wherein the second step of forming an adhesive resin layer is performed after the cutting into IC chips in the third step. Features.

【００１１】請求項8記載の積層型半導体装置の製造方
法は請求項２においてＩＣチップへ切断する第三の工程
がシリコンウエハー状態で積層、接着樹脂の硬化を行っ
た後に実施されることを特徴とする。In the method for manufacturing a stacked semiconductor device according to the present invention, the third step of cutting into IC chips is performed after the laminating and bonding resin are cured in a silicon wafer state. And

【００１２】（作用）インクジェット方式による電気的
導通配線の形成について説明を加える。従来はメッキあ
るいはスパッタにより金属膜を形成し、さらにフォトリ
ソグラフィー、エッチング等を用いて配線に加工してい
た。インクジェット方式とは元来パーソナルコンピュー
タの周辺機器であるプリンターのインク吐出技術であり
１０ピコリットル程度以上の微少液滴を微少ノズル先端
から吐出して描画する技術である。近年低融点の溶融し
た金属、金属ペースト等もヘッドノズルから吐出できる
ことが確認できた。したがってこの技術で直接的に電気
的配線が描画形成できる。配線幅も最小２０μm程度の
微細配線が可能である。したがって、本技術は大掛かり
なプロセスを用いない極めて簡単な配線形成技術として
将来性が高い。(Operation) The formation of the electrically conductive wiring by the ink jet method will be described. Conventionally, a metal film has been formed by plating or sputtering, and further processed into wiring using photolithography, etching, or the like. The ink jet system is an ink ejection technology of a printer which is originally a peripheral device of a personal computer, and is a technology in which a minute droplet of about 10 picoliter or more is ejected from a tip of a minute nozzle to draw. In recent years, it has been confirmed that a low melting point molten metal, metal paste, and the like can be discharged from the head nozzle. Therefore, the electrical wiring can be directly drawn and formed by this technique. Fine wiring with a minimum wiring width of about 20 μm is possible. Therefore, the present technology has a high future potential as an extremely simple wiring forming technology without using a large-scale process.

【００１３】[0013]

【発明の実施の形態】以下本発明の実施の形態を実施例
により説明する。Embodiments of the present invention will be described below with reference to embodiments.

【００１４】（実施例１）図２はＩＣチップを形成した
６インチ径のシリコンウエハーを示す。図３はその表面
の一部を示すもので３１は配線接続用のボンディングパ
ッドである。ボンディングパッド以外の部分３２はプラ
ズマＣＶＤで形成した絶縁膜で覆われている。本実施例
では各ＩＣチップの周辺部のみにボンディングパッドを
形成したものを用いた。ボンディングパッドの個数は数
十から数百になるが説明を容易にするために個数を少な
くして描いた。また実線部３３は後工程で切断される位
置を示す。各ボンディングパッドは通常アルミニウムで
形成されており必要に応じてバリアメタル層でカバーさ
れる。本実施例ではチタンタングステン合金（ＴｉＷ）
とその上を銅でカバーしたものを用いた。Embodiment 1 FIG. 2 shows a 6-inch diameter silicon wafer on which IC chips are formed. FIG. 3 shows a part of the surface, and 31 is a bonding pad for wiring connection. Portions 32 other than the bonding pads are covered with an insulating film formed by plasma CVD. In the present embodiment, the one in which bonding pads are formed only in the peripheral portion of each IC chip is used. Although the number of bonding pads is several tens to several hundreds, the number is reduced for ease of explanation. Further, a solid line portion 33 indicates a position to be cut in a later step. Each bonding pad is usually made of aluminum and is covered with a barrier metal layer as needed. In this embodiment, titanium tungsten alloy (TiW)
And one covered with copper was used.

【００１５】第一の工程として各ボンディングパッドか
ら後工程で他のＩＣチップとの配線接続が想定される切
断部までの間にインクジェットヘッドから溶融したはん
だ材料を吐出することにより厚み約１０μm、幅３０μm
の電気的導通配線３４を形成した。インクジェットで塗
出できる金属は現状では５０℃から数１００℃で溶融す
る金属が適用できるレベルになってきた。これによって
形成される配線の密着性を高めるためにＩＣが形成され
たシリコンウエハーにプラズマエッチングなどの乾式表
面処理を行ってもよい。本実施例では酸素プラズマによ
ってシリコンウエハーの上の絶縁膜表面をライトエッチ
ングした。As a first step, a molten solder material is ejected from an ink jet head from each bonding pad to a cut portion where a wiring connection to another IC chip is assumed in a later step, so that the thickness is about 10 μm and the width is about 10 μm. 30 μm
Was formed. Metals that can be applied by ink jet at present have reached a level where metals melting at 50 ° C. to several 100 ° C. can be applied. A dry surface treatment such as plasma etching may be performed on the silicon wafer on which the IC is formed in order to enhance the adhesion of the wiring formed thereby. In this embodiment, the surface of the insulating film on the silicon wafer is lightly etched by oxygen plasma.

【００１６】第二の工程としてこのシリコンウエハーの
表面に電子線硬化型の接着性樹脂を塗布した。該接着性
樹脂はＩＣチップ周辺部に図４の４１のように塗布され
た。少なくとも上記電気的導通配線の上には樹脂層が形
成される。厚みは特に限定はないが本実施例では１００
μmとした。周辺部全域に接着性樹脂層を形成しないの
はＩＣから発生する熱が外部に逃げ易くするためであ
る。As a second step, an electron beam-curable adhesive resin was applied to the surface of the silicon wafer. The adhesive resin was applied to the periphery of the IC chip as shown at 41 in FIG. A resin layer is formed at least on the electrical conduction wiring. Although the thickness is not particularly limited, it is 100 in this embodiment.
μm. The reason why the adhesive resin layer is not formed in the entire peripheral portion is to make it easier for heat generated from the IC to escape to the outside.

【００１７】第三の工程として全工程で作製したシリコ
ンウエハーを一つ一つのＩＣチップに切断して分割し
た。As a third step, the silicon wafer produced in all the steps was cut into individual IC chips and divided.

【００１８】第四の工程として異種の電気的機能を持つ
ＩＣを同様に加工して計３枚を重ねあわせた。最上部に
置かれたＩＣチップは接着性樹脂を被覆せず各ボンディ
ングパッドには回路基板に電気的に接続するためのはん
だによるバンプが形成された。続いて電子線を照射して
三枚のＩＣチップを接着した。As a fourth step, ICs having different electrical functions were processed in the same manner, and a total of three ICs were superposed. The topmost IC chip was not coated with an adhesive resin, and each bonding pad was formed with a solder bump for electrical connection to a circuit board. Subsequently, three IC chips were bonded by irradiating an electron beam.

【００１９】第五の工程として図１に示すようにＩＣチ
ップ１１を三枚重ね合せたＩＣチップ積層体の側面部に
おいてインクジェットヘッドから溶融したはんだ材料を
吐出することにより厚み約１０μm、幅３０μmの電気的
導通配線１５を形成した。１２はボンディングパッド、
１３は第一の工程で形成した電気的導通配線、１４は接
着性樹脂層である。この配線形成前に少なくとも配線形
成部の表面を洗浄と配線密着性改善のためプラズマエッ
チングなどの乾式表面処理を行ってもよい。本実施例で
は酸素プラズマによってライトエッチングした。この配
線は前述のボンディングパッドから引き出した電気的導
通配線の端面と接合されることにより三次元的な電気的
接続を可能にした。以上のようにして実装密度の高いチ
ップオンチップ構造が実現できた。As a fifth step, as shown in FIG. 1, a molten solder material is ejected from an ink jet head on a side surface of an IC chip laminated body in which three IC chips 11 are stacked to form a chip having a thickness of about 10 μm and a width of 30 μm. The electrically conductive wiring 15 was formed. 12 is a bonding pad,
Reference numeral 13 denotes an electrically conductive wiring formed in the first step, and reference numeral 14 denotes an adhesive resin layer. Before forming the wiring, at least the surface of the wiring forming portion may be subjected to dry surface treatment such as plasma etching for cleaning and improving the wiring adhesion. In this embodiment, light etching is performed by oxygen plasma. The wiring is joined to the end surface of the electrically conductive wiring drawn from the above-mentioned bonding pad, thereby enabling three-dimensional electrical connection. As described above, a chip-on-chip structure having a high mounting density was realized.

【００２０】（実施例２）実施例１と同様であるが金属
による電気的導通配線の変わりに銀粒子を含んだ樹脂、
所謂銀ペーストを用いた。一般に金属よりは抵抗が高く
なるため厚み約3０μm、幅３０μm の配線として形成し
た。また第二の工程で用いる接着樹脂は熱硬化性アクリ
ルを用いた。銀ペーストも熱硬化型であったため一括硬
化できた。以上の結果実施例１と同様に実装密度の高い
チップオンチップ構造が実現できた。ペースト材は配線
抵抗に影響を与えないなら特に制限されない。含有する
樹脂、有機溶剤成分も他の構造に影響を与えなければ制
限されない。以上のように本発明の大きな優位性は配線
形成工程の容易性にある。(Embodiment 2) The same as Embodiment 1, except that a resin containing silver particles is used instead of an electrically conductive wiring made of metal.
A so-called silver paste was used. Generally, since the resistance is higher than that of metal, the wiring is formed as a wiring having a thickness of about 30 μm and a width of 30 μm. The adhesive resin used in the second step was thermosetting acrylic. Since the silver paste was also a thermosetting type, it could be cured at once. As a result, a chip-on-chip structure having a high mounting density was realized as in the first embodiment. The paste material is not particularly limited as long as it does not affect the wiring resistance. The contained resin and organic solvent components are not limited as long as they do not affect other structures. As described above, a great advantage of the present invention lies in the easiness of the wiring forming process.

【００２１】（実施例３）実施例１と基本的には同様で
あるが第三の工程の個々のＩＣチップへの切断を第一の
工程の直後に行い、洗浄の後本来第二の工程である接着
樹脂の塗布を各ＩＣチップへ分割してから実施した。接
着樹脂塗布後に切断すると接着樹脂上が切断時に発生す
る粉塵で汚染され洗浄によっても除去しにくいことがあ
るため実施した。以上の結果実施例１と同様に実装密度
の高いチップオンチップ構造が実現できた。(Embodiment 3) Basically the same as the embodiment 1, but the cutting into the individual IC chips in the third step is performed immediately after the first step, and after the cleaning, the second step is originally performed. Was applied to each IC chip after the application of the adhesive resin was performed. The cutting was performed after the application of the adhesive resin because the adhesive resin was sometimes contaminated with dust generated at the time of cutting and was difficult to remove even by washing. As a result, a chip-on-chip structure having a high mounting density was realized as in the first embodiment.

【００２２】（実施例４）実施例１と基本的には同様で
あるが第三の工程の個々のＩＣチップへの切断を第二の
工程と第四の工程の後に実施した。すなわち、第二の工
程でシリコンウエハー上に接着樹脂を塗布した後第四の
積層、硬化工程をウエハー状態のまま行った。積層、硬
化は一枚重ねるごとに熱硬化工程により実施した。積層
状態で一括して切断した。この一括して切断できる点に
優位性がある。以上の結果実施例１と同様に実装密度の
高いチップオンチップ構造が実現できた。(Embodiment 4) Basically the same as the embodiment 1, but the cutting into the individual IC chips in the third step is performed after the second step and the fourth step. That is, after the adhesive resin was applied on the silicon wafer in the second step, the fourth laminating and curing step was performed in a wafer state. Lamination and curing were carried out by a heat curing process each time one sheet was laminated. The pieces were cut in a lump in a stacked state. There is an advantage in that it can be cut at once. As a result, a chip-on-chip structure having a high mounting density was realized as in the first embodiment.

【００２３】（実施例５）実施例４と同様であるがシリ
コンウエハーの積層を５枚で行い、硬化は電子線により
一回で行った。さらに積層状態で一括して切断した。以
上の結果実施例１と同様に実装密度の高いチップオンチ
ップ構造が実現できた。(Example 5) The same as Example 4, except that five silicon wafers were laminated, and curing was performed once with an electron beam. Furthermore, they were cut in a lump in a laminated state. As a result, a chip-on-chip structure having a high mounting density was realized as in the first embodiment.

【００２４】本実施例では電気的導通配線の形成法とし
てインクジェット技術のみを適用しているが、例えば真
空中で微細ノズルから金属の微小粒子を吐出して金属膜
を形成する方法も検討されており本発明に対しても適用
可能性が高い。In this embodiment, only the ink-jet technique is applied as a method of forming the electrically conductive wiring. However, for example, a method of discharging a metal fine particle from a fine nozzle in a vacuum to form a metal film has been studied. It is highly applicable to the present invention.

【００２５】[0025]

【発明の効果】以上のように本発明により多数のＩＣが
積層されたチップオンチップ構造を容易に製造すること
が可能となった。As described above, according to the present invention, a chip-on-chip structure in which a large number of ICs are stacked can be easily manufactured.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一つの実施例を模式的に示す断面図。FIG. 1 is a sectional view schematically showing one embodiment of the present invention.

【図２】本発明で用いたＩＣチップが形成されたシリコ
ンウエハーを模式的に示す図。FIG. 2 is a diagram schematically showing a silicon wafer on which an IC chip used in the present invention is formed.

【図３】実施例１の第一の工程を説明するための図。FIG. 3 is a view for explaining a first step of the first embodiment.

【図４】実施例１の第二の工程を説明するための図。FIG. 4 is a view for explaining a second step of the first embodiment.

【図５】従来の一例を示す図。FIG. 5 is a diagram showing an example of the related art.

【符号の説明】[Explanation of symbols]

１１．ＩＣチップ １２．ボンディングパッド １３．電気的導通配線 １４．接着性樹脂 １５．電気的導通配線 ３１．ボンディングパッド ３２．絶縁膜で被覆された部分 ３３．切断位置 ３４．電気的導通配線 ４１．接着性樹脂塗布部 ５１．ＩＣチップ ５２．スルーホール ５３．金属配線 11. IC chip 12. Bonding pad 13. Electrical conduction wiring 14. Adhesive resin 15. Electrical conduction wiring 31. Bonding pad 32. Part covered with insulating film 33. Cutting position 34. Electrical conduction wiring 41. Adhesive resin application part 51. IC chip 52. Through hole 53. Metal wiring

Claims (8)

【特許請求の範囲】[Claims] 【請求項１】ＩＣチップの各ボンディングパッドからチ
ップ端面までに電気的導通配線が形成され、さらに該チ
ップの全面もしくは一部に接着性のある樹脂層が形成さ
れ、同様に形成された電気的に別機能を持つ複数のチッ
プが該樹脂層により接着、積層され、さらに各チップ端
面を横断してなる電気的導通配線により積層された全チ
ップが接続されたことを特徴とする積層型半導体装置。An electrically conductive wiring is formed from each bonding pad of an IC chip to a chip end face, and an adhesive resin layer is formed on the entire surface or a part of the chip. Wherein a plurality of chips having different functions are adhered and laminated by the resin layer, and all the laminated chips are connected by electrical conduction wirings traversing each chip end face. . 【請求項２】複数のＩＣチップが形成されたシリコンウ
エハーの各チップ内のボンディングパッドから少なくと
も各チップ切断位置までに電気的導通配線を形成する第
一の工程、第一の工程を経たシリコンウエハーの電気的
導通配線形成面の全面もしくは一部に接着性のある樹脂
層を形成する第二の工程、第二の工程を経たウエハーを
切断により個々のＩＣチップに分割する第三の工程、同
様に形成された電気的に別機能を持つＩＣチップが積層
され、接着性のある樹脂の硬化によって互いに接着にさ
れる第四の工程、積層された各ＩＣチップが第一の工程
で作製された電気的導通配線の末端同士で各ＩＣチップ
切断面を横断する方向に電気的導通配線により接続され
る第五の工程からなることを特徴とする積層型半導体装
置の製造方法。A first step of forming an electrically conductive wiring from a bonding pad in each chip of the silicon wafer on which a plurality of IC chips are formed to at least a cutting position of each chip; A second step of forming an adhesive resin layer on the entire surface or a part of the electrically conductive wiring forming surface, a third step of cutting the wafer after the second step into individual IC chips by cutting, and the like. In the fourth step, the IC chips having electrically different functions formed in the first step are laminated and bonded to each other by curing the adhesive resin, and the laminated IC chips are produced in the first step. 5. A method of manufacturing a stacked semiconductor device, comprising: a fifth step of connecting the ends of the electrically conductive wiring with the electrical conductive wiring in a direction crossing the cut surface of each IC chip. 【請求項３】電気的導通配線がインクジェット方式で形
成されることを特徴とする請求項２記載の積層型半導体
装置の製造方法。3. The method according to claim 2, wherein the electrically conductive wiring is formed by an ink jet method. 【請求項４】電気的導通配線材料が金属もしくは導電性
粒子を含有する導電性樹脂から選ばれてなることを特徴
とする請求項２記載の積層型半導体装置の製造方法。4. The method for manufacturing a stacked semiconductor device according to claim 2, wherein the electrically conductive wiring material is selected from a metal or a conductive resin containing conductive particles. 【請求項５】第四の工程のＩＣチップの接着樹脂の硬化
が一枚のチップを重ねる毎に行われるかもしくは全ＩＣ
チップを重ねた後に一括して行われることを特徴とする
請求項２記載の積層型半導体装置の製造方法。5. The method according to claim 4, wherein the curing of the adhesive resin of the IC chip in the fourth step is performed every time one chip is stacked, or
3. The method for manufacturing a stacked semiconductor device according to claim 2, wherein the steps are performed collectively after the chips are stacked. 【請求項６】接着樹脂の硬化が熱硬化もしくは電子線硬
化でおこなわれることを特徴とする請求項２記載の積層
型半導体装置の製造方法。6. The method according to claim 2, wherein the curing of the adhesive resin is performed by heat curing or electron beam curing. 【請求項７】接着性のある樹脂層を形成する第二の工程
が第三の工程のＩＣチップへの切断の後に行われること
を特徴とする請求項２記載の積層型半導体装置の製造方
法。7. The method for manufacturing a stacked semiconductor device according to claim 2, wherein the second step of forming an adhesive resin layer is performed after cutting into IC chips in the third step. . 【請求項８】ＩＣチップへ切断する第三の工程がシリコ
ンウエハー状態で積層、接着樹脂の硬化を行った後に実
施されることを特徴とする請求項２記載の積層型半導体
装置の製造方法。8. The method according to claim 2, wherein the third step of cutting into IC chips is performed after laminating and curing the adhesive resin in a silicon wafer state.
JP11017134A 1999-01-26 1999-01-26 Stacked semiconductor device and its manufacture Withdrawn JP2000216330A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11017134A JP2000216330A (en) 1999-01-26 1999-01-26 Stacked semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11017134A JP2000216330A (en) 1999-01-26 1999-01-26 Stacked semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JP2000216330A true JP2000216330A (en) 2000-08-04

Family

ID=11935566

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11017134A Withdrawn JP2000216330A (en) 1999-01-26 1999-01-26 Stacked semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JP2000216330A (en)

Cited By (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001156254A (en) * 1999-11-26 2001-06-08 Nec Corp Semiconductor device three-dimensional semiconductor device using it and its manufacturing method as well as template
US6504244B2 (en) * 2000-02-02 2003-01-07 Nec Corporation Semiconductor device and semiconductor module using the same
JP2003078108A (en) * 2001-08-31 2003-03-14 Hitachi Chem Co Ltd Semiconductor package board, semiconductor package using the same and its laminate, and method of manufacturing them
US6810814B2 (en) 2002-04-16 2004-11-02 Seiko Epson Corporation Method for fabricating pattern, apparatus for fabricating pattern, conductive film wiring, method for fabricating device, electro-optical apparatus, and electronic apparatus
US6871339B2 (en) 2002-04-19 2005-03-22 Seiko Epson Corporation Method of manufacturing a device, device manufacturing apparatus, device, and electronic apparatus
US7008809B2 (en) 2003-05-16 2006-03-07 Seiko Epson Corporation Pattern formation method and pattern formation apparatus, method for manufacturing device, electro-optical device, electronic device, and method for manufacturing active matrix substrate
US7138304B2 (en) 2003-05-16 2006-11-21 Seiko Epson Corporation Method for forming thin film pattern, device and production method therefor, electro-optical apparatus and electronic apparatus, and production method for active matrix substrate
KR100668857B1 (en) 2005-07-07 2007-01-16 주식회사 하이닉스반도체 Stack type package
US7199033B2 (en) 2003-05-28 2007-04-03 Seiko Epson Corporation Pattern forming method, device, method of manufacture thereof, electro-optical apparatus, and electronic apparatus
US7220682B2 (en) 2003-05-12 2007-05-22 Seiko Epson Corporation Pattern and fabricating method therefor, device and fabricating method therefor, electro-optical apparatus, electronic apparatus, and method for fabricating active matrix substrate
US7230341B2 (en) 2003-03-13 2007-06-12 Seiko Epson Corporation Electronic device and method of manufacturing the same, circuit board, and electronic instrument
US7235415B2 (en) 2003-05-28 2007-06-26 Seiko Epson Corporation Film pattern formation method, device and method for manufacturing the same, electro-optical device, electronic device, and method for manufacturing active matrix substrate
JP2007523482A (en) * 2004-02-18 2007-08-16 インフィネオン テクノロジーズ アクチエンゲゼルシャフト SEMICONDUCTOR ELEMENT HAVING LAMINATED SEMICONDUCTOR CHIP AND METHOD FOR MANUFACTURING SAME
US7278725B2 (en) 2002-04-19 2007-10-09 Seiko Epson Corporation Layer forming method, layer forming apparatus, device, manufacturing method for device, and electronic apparatus
US7282779B2 (en) 2003-05-30 2007-10-16 Seiko Epson Corporation Device, method of manufacture thereof, manufacturing method for active matrix substrate, electro-optical apparatus and electronic apparatus
US7320902B2 (en) 2003-03-13 2008-01-22 Seiko Epson Corporation Electronic device and method of manufacturing the same, chip carrier, circuit board, and electronic instrument
US7335991B2 (en) 2004-09-30 2008-02-26 Seiko Epson Corporation Pattern forming structure, pattern forming method, device, electro-optical device, and electronic apparatus
US7364622B2 (en) 2002-03-13 2008-04-29 Seiko Epson Corporation Method and apparatus for fabricating a device, and the device and an electronic equipment
US7387903B2 (en) 2003-07-15 2008-06-17 Seiko Epson Corporation Method for manufacturing layer pattern, method for manufacturing wiring, and method for manufacturing electronic equipment
KR100841284B1 (en) * 2006-03-17 2008-06-25 세이코 엡슨 가부시키가이샤 Method of forming metal wiring and method of manufacturing active matrix substrate
CN100429747C (en) * 2005-05-16 2008-10-29 精工爱普生株式会社 Bank structure, wiring pattern forming method, device, electro-optical device, and electronic apparatus
US7454831B2 (en) 2004-11-16 2008-11-25 Seiko Epson Corporation Method for mounting an electronic element on a wiring board
JP2009054835A (en) * 2007-08-28 2009-03-12 Toshiba Corp Semiconductor device and its manufacturing method
US7514350B2 (en) 2003-03-13 2009-04-07 Seiko Epson Corporation Electronic device and method of manufacturing the same, circuit board, and electronic instrument
US7560297B2 (en) 2005-11-16 2009-07-14 Seiko Epson Corporation Active matrix substrate, manufacturing method thereof, electro-optical device, and electronic apparatus
US7582545B2 (en) 2005-07-20 2009-09-01 Seiko Epson Corporation Forming method for film pattern, device, electro-optical apparatus, electronic apparatus, and manufacturing method for active matrix substrate
US7582333B2 (en) 2003-03-11 2009-09-01 Seiko Epson Corporation Pattern forming method, pattern forming apparatus, method of manufacturing device, conductive film wiring, electro-optical device, and electronic apparatus
US7667232B2 (en) 2004-10-13 2010-02-23 Seiko Epson Corporation Bank structure, method of forming bank structure, device, electro-optical device and electronic apparatus
US7678697B2 (en) 2003-05-09 2010-03-16 Seiko Epson Corporation Substrate, device, method of manufacturing device, method of manufacturing active matrix substrate, electro-optical apparatus and electronic apparatus
US7691562B2 (en) 2005-07-20 2010-04-06 Seiko Epson Corporation Method for forming film pattern, and method for manufacturing device, electro-optical device, electronic apparatus and active matrix substrate
US7732817B2 (en) 2004-09-30 2010-06-08 Seiko Epson Corporation Pattern formed structure, method of forming pattern, device, electrooptical device and electronic equipment
US7794785B2 (en) 2003-04-22 2010-09-14 Seiko Epson Corporation Cleaning method, storage method, pattern formation method, device manufacturing method, electro-optical device, and electronic apparatus
US7799407B2 (en) 2005-05-16 2010-09-21 Seiko Epson Corporation Bank structure, wiring pattern forming method, device, electro-optical device, and electronic apparatus
US7803515B2 (en) 2005-11-04 2010-09-28 Seiko Epson Corporation Film pattern forming method, device, electro-optical apparatus, and electronic appliance
US7964955B2 (en) 2004-11-16 2011-06-21 Seiko Epson Corporation Electronic device package and electronic equipment
US8033648B2 (en) 2006-09-29 2011-10-11 Brother Kogyo Kabushiki Kaisha Pattern forming apparatus and pattern forming method

Cited By (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001156254A (en) * 1999-11-26 2001-06-08 Nec Corp Semiconductor device three-dimensional semiconductor device using it and its manufacturing method as well as template
US6504244B2 (en) * 2000-02-02 2003-01-07 Nec Corporation Semiconductor device and semiconductor module using the same
JP2003078108A (en) * 2001-08-31 2003-03-14 Hitachi Chem Co Ltd Semiconductor package board, semiconductor package using the same and its laminate, and method of manufacturing them
US7364622B2 (en) 2002-03-13 2008-04-29 Seiko Epson Corporation Method and apparatus for fabricating a device, and the device and an electronic equipment
US6810814B2 (en) 2002-04-16 2004-11-02 Seiko Epson Corporation Method for fabricating pattern, apparatus for fabricating pattern, conductive film wiring, method for fabricating device, electro-optical apparatus, and electronic apparatus
US7146910B2 (en) 2002-04-16 2006-12-12 Seiko Epson Corporation Method for fabricating pattern, apparatus for fabricating pattern, conductive film wiring, method for fabricating device, electro-optical apparatus, and electronic apparatus
US6871339B2 (en) 2002-04-19 2005-03-22 Seiko Epson Corporation Method of manufacturing a device, device manufacturing apparatus, device, and electronic apparatus
US7278725B2 (en) 2002-04-19 2007-10-09 Seiko Epson Corporation Layer forming method, layer forming apparatus, device, manufacturing method for device, and electronic apparatus
US7582333B2 (en) 2003-03-11 2009-09-01 Seiko Epson Corporation Pattern forming method, pattern forming apparatus, method of manufacturing device, conductive film wiring, electro-optical device, and electronic apparatus
US7230341B2 (en) 2003-03-13 2007-06-12 Seiko Epson Corporation Electronic device and method of manufacturing the same, circuit board, and electronic instrument
US7611925B2 (en) 2003-03-13 2009-11-03 Seiko Epson Corporation Electronic device and method of manufacturing the same, chip carrier, circuit board, and electronic instrument
US7564142B2 (en) 2003-03-13 2009-07-21 Seiko Epson Corporation Electronic device and method of manufacturing the same, circuit board, and electronic instrument
US7320902B2 (en) 2003-03-13 2008-01-22 Seiko Epson Corporation Electronic device and method of manufacturing the same, chip carrier, circuit board, and electronic instrument
US7514350B2 (en) 2003-03-13 2009-04-07 Seiko Epson Corporation Electronic device and method of manufacturing the same, circuit board, and electronic instrument
US7794785B2 (en) 2003-04-22 2010-09-14 Seiko Epson Corporation Cleaning method, storage method, pattern formation method, device manufacturing method, electro-optical device, and electronic apparatus
US7678697B2 (en) 2003-05-09 2010-03-16 Seiko Epson Corporation Substrate, device, method of manufacturing device, method of manufacturing active matrix substrate, electro-optical apparatus and electronic apparatus
CN100403511C (en) * 2003-05-12 2008-07-16 精工爱普生株式会社 Pattern and fabricating method therefor, device and fabricating method therefor, electro-optical apparatus, electronic apparatus
US7220682B2 (en) 2003-05-12 2007-05-22 Seiko Epson Corporation Pattern and fabricating method therefor, device and fabricating method therefor, electro-optical apparatus, electronic apparatus, and method for fabricating active matrix substrate
EP1925974A2 (en) 2003-05-12 2008-05-28 Seiko Epson Corporation Fabrication of a wiring pattern and of an active matrix substrate
US7008809B2 (en) 2003-05-16 2006-03-07 Seiko Epson Corporation Pattern formation method and pattern formation apparatus, method for manufacturing device, electro-optical device, electronic device, and method for manufacturing active matrix substrate
US7138304B2 (en) 2003-05-16 2006-11-21 Seiko Epson Corporation Method for forming thin film pattern, device and production method therefor, electro-optical apparatus and electronic apparatus, and production method for active matrix substrate
US7365008B2 (en) 2003-05-28 2008-04-29 Seiko Epson Corporation Pattern forming method, device, method of manufacture thereof, electro-optical apparatus, and electronic apparatus
CN100442954C (en) * 2003-05-28 2008-12-10 精工爱普生株式会社 Thin film pattern forming method, device and method of manufacture, electrooptical device
US7235415B2 (en) 2003-05-28 2007-06-26 Seiko Epson Corporation Film pattern formation method, device and method for manufacturing the same, electro-optical device, electronic device, and method for manufacturing active matrix substrate
US7199033B2 (en) 2003-05-28 2007-04-03 Seiko Epson Corporation Pattern forming method, device, method of manufacture thereof, electro-optical apparatus, and electronic apparatus
US7282779B2 (en) 2003-05-30 2007-10-16 Seiko Epson Corporation Device, method of manufacture thereof, manufacturing method for active matrix substrate, electro-optical apparatus and electronic apparatus
US7387903B2 (en) 2003-07-15 2008-06-17 Seiko Epson Corporation Method for manufacturing layer pattern, method for manufacturing wiring, and method for manufacturing electronic equipment
JP2007523482A (en) * 2004-02-18 2007-08-16 インフィネオン テクノロジーズ アクチエンゲゼルシャフト SEMICONDUCTOR ELEMENT HAVING LAMINATED SEMICONDUCTOR CHIP AND METHOD FOR MANUFACTURING SAME
US7732817B2 (en) 2004-09-30 2010-06-08 Seiko Epson Corporation Pattern formed structure, method of forming pattern, device, electrooptical device and electronic equipment
US7335991B2 (en) 2004-09-30 2008-02-26 Seiko Epson Corporation Pattern forming structure, pattern forming method, device, electro-optical device, and electronic apparatus
US7667232B2 (en) 2004-10-13 2010-02-23 Seiko Epson Corporation Bank structure, method of forming bank structure, device, electro-optical device and electronic apparatus
US7964955B2 (en) 2004-11-16 2011-06-21 Seiko Epson Corporation Electronic device package and electronic equipment
US7454831B2 (en) 2004-11-16 2008-11-25 Seiko Epson Corporation Method for mounting an electronic element on a wiring board
CN100429747C (en) * 2005-05-16 2008-10-29 精工爱普生株式会社 Bank structure, wiring pattern forming method, device, electro-optical device, and electronic apparatus
US7799407B2 (en) 2005-05-16 2010-09-21 Seiko Epson Corporation Bank structure, wiring pattern forming method, device, electro-optical device, and electronic apparatus
KR100668857B1 (en) 2005-07-07 2007-01-16 주식회사 하이닉스반도체 Stack type package
US7391106B2 (en) 2005-07-07 2008-06-24 Hynix Semiconductor Inc. Stack type package
US7582545B2 (en) 2005-07-20 2009-09-01 Seiko Epson Corporation Forming method for film pattern, device, electro-optical apparatus, electronic apparatus, and manufacturing method for active matrix substrate
US7691562B2 (en) 2005-07-20 2010-04-06 Seiko Epson Corporation Method for forming film pattern, and method for manufacturing device, electro-optical device, electronic apparatus and active matrix substrate
US7803515B2 (en) 2005-11-04 2010-09-28 Seiko Epson Corporation Film pattern forming method, device, electro-optical apparatus, and electronic appliance
US7560297B2 (en) 2005-11-16 2009-07-14 Seiko Epson Corporation Active matrix substrate, manufacturing method thereof, electro-optical device, and electronic apparatus
US7727869B2 (en) 2006-03-17 2010-06-01 Seiko Epson Corporation Method of forming metal wiring and method of manufacturing active matrix substrate
KR100841284B1 (en) * 2006-03-17 2008-06-25 세이코 엡슨 가부시키가이샤 Method of forming metal wiring and method of manufacturing active matrix substrate
US8033648B2 (en) 2006-09-29 2011-10-11 Brother Kogyo Kabushiki Kaisha Pattern forming apparatus and pattern forming method
JP2009054835A (en) * 2007-08-28 2009-03-12 Toshiba Corp Semiconductor device and its manufacturing method

Similar Documents

Publication Publication Date Title
JP2000216330A (en) Stacked semiconductor device and its manufacture
JP4343044B2 (en) Interposer, manufacturing method thereof, and semiconductor device
JP4081666B2 (en) Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
KR101103857B1 (en) Printed wiring board and method for manufacturing the same
KR100852597B1 (en) Method for manufacturing semiconductor device
JP3908157B2 (en) Method of manufacturing flip chip type semiconductor device
JP4716819B2 (en) Manufacturing method of interposer
US11521948B2 (en) Method of manufacturing semiconductor device
JP5942823B2 (en) Electronic component device manufacturing method, electronic component device, and electronic device
JP2007157844A (en) Semiconductor device, and method of manufacturing same
JP2004022730A (en) Semiconductor device and its producing process
JP2007180395A (en) Manufacturing method of semiconductor device
US6906428B2 (en) Electronic component having a semiconductor chip and method for populating a circuit carrier during the production of the electronic component
JP4603383B2 (en) Wiring board, semiconductor device, and manufacturing method thereof
CN114188316A (en) Packaging method and packaging structure of fan-out type stacked chip
KR100746862B1 (en) Semiconductor device and fabrication method therefor
JP2022042482A (en) Connector achieving versatile interconnection and manufacturing method thereof
JP5033682B2 (en) SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING SAME, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
JPWO2002035602A1 (en) Bump forming method and bump forming apparatus
KR20190001919A (en) Semiconductor package and method for manufacturing the semiconductor package
CN114171406A (en) Packaging method and packaging structure of fan-out type stacked chip
JP2004063804A (en) Semiconductor device, stacked type semiconductor device and manufacturing method thereof
JP2004119472A (en) Semiconductor device, its manufacturing method, circuit board, and electronic apparatus
JP4642061B2 (en) Circuit device manufacturing method
KR100584003B1 (en) Method for manufacturing stack chip package

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040311

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050622

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050628

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20050810