JP2000195823A - Plating method and plating apparatus - Google Patents
Plating method and plating apparatusInfo
- Publication number
- JP2000195823A JP2000195823A JP10372817A JP37281798A JP2000195823A JP 2000195823 A JP2000195823 A JP 2000195823A JP 10372817 A JP10372817 A JP 10372817A JP 37281798 A JP37281798 A JP 37281798A JP 2000195823 A JP2000195823 A JP 2000195823A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- wafer
- cathode electrode
- current
- shielding plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Electroplating Methods And Accessories (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electroplating And Plating Baths Therefor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体ウェハ，そ
の製造法，電気めっき方法および電気めっき装置に関わ
り、特に均一なめっき層を形成可能なものに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer, a method for manufacturing the same, an electroplating method and an electroplating apparatus, and more particularly to a semiconductor wafer capable of forming a uniform plating layer.
【０００２】[0002]
【従来の技術】電気めっき法においては、被めっき物上
の電流密度分布あるいはめっき液の濃度を極力均一にす
ることでめっき層の膜厚ばらつきを抑制する。被めっき
物上のめっき層の厚さを均一にする方法として次のよう
な方法が用いられている。2. Description of the Related Art In an electroplating method, variations in the thickness of a plating layer are suppressed by making the current density distribution on a plating object or the concentration of a plating solution as uniform as possible. The following method has been used as a method for making the thickness of a plating layer on an object to be plated uniform.
【０００３】特開平10−140393号公報では、めっき装置
内のカソードとアノードの間に補助カソードを取り入れ
ている。補助カソードは電極間に平行に設置され、これ
により凹凸のある金属条を均一にめっき可能としてい
る。In Japanese Patent Application Laid-Open No. 10-140393, an auxiliary cathode is incorporated between a cathode and an anode in a plating apparatus. The auxiliary cathode is placed in parallel between the electrodes, so that uneven metal strips can be plated uniformly.
【０００４】特開平10−140392号公報ではアノードとカ
ソードの間に電流遮蔽板を多数配置している。電流遮蔽
板の形状は、電極に垂直な方向に長い板となっており、
これにより凹凸のある金属条を均一にめっき可能として
いる。In Japanese Patent Application Laid-Open No. 10-140392, a large number of current shielding plates are arranged between an anode and a cathode. The shape of the current shielding plate is a plate that is long in the direction perpendicular to the electrodes,
Thereby, a metal strip having irregularities can be plated uniformly.
【０００５】特開平10−96097 号公報では、アノード電
極と交互にバイポーラコンダクターを配置している。こ
れにより、めっき層に生じる平行縞を防止し、めっき膜
厚を均一化している。In JP-A-10-96097, bipolar conductors are arranged alternately with anode electrodes. This prevents parallel stripes from occurring in the plating layer and makes the plating film thickness uniform.
【０００６】特開平8−31834号公報ではめっき液を噴流
状にして半導体ウェハに吹き付けている。半導体ウェハ
は噴流に垂直に当たるように配置され、これにより均一
なめっき層を得ている。In Japanese Patent Application Laid-Open No. Hei 8-31834, a plating solution is jetted onto a semiconductor wafer. The semiconductor wafer is arranged so as to be perpendicular to the jet, thereby obtaining a uniform plating layer.
【０００７】特開平10−130896号公報では、カソード付
近に電流密度センサーを設け、このセンサーの測定結果
を用いて電流密度分布が均一になるよう電流遮蔽板の穴
径，位置を変化させながらめっきする方法について記述
されている。In Japanese Patent Application Laid-Open No. H10-130896, a current density sensor is provided near a cathode, and plating is performed while changing the hole diameter and position of a current shielding plate so as to make the current density distribution uniform using the measurement results of the sensor. It describes how to do it.
【０００８】[0008]
【発明が解決しようとする課題】半導体ウェハ上に形成
された導電性薄膜をカソード電極とする場合、薄膜の抵
抗値が高いため、給電点付近と給電点から離れた場所で
の電流密度比が大きくなる。半導体ウェハの場合、給電
に適した部位はウェハ外周部などごく限られている。こ
のため、めっき膜厚が給電点（ウェハ外周部）付近で厚
くなり膜厚分布が不均一となる。めっき膜厚が厚くなっ
たウェハ外周部では、膜の抵抗が減少してさらに電界が
集中し易くなる。このような不具合を避けるには特開平
10−140392号公報，特開平10−130896号公報にあるよう
に電流遮蔽板を導入してウェハ上での電流密度分布を均
一化する必要がある。但し特開平10−140392号公報で
は、電流分布の不均一発生原因が薄膜抵抗に基づいたも
のではなく、電極や装置の幾何的形状がもたらすもので
あるため、これに最適化された遮蔽板の形状および配置
ではない。また、特開平10−130896号公報のように、遮
蔽板の開口率や遮蔽板位置をオンラインで変化させた場
合には、次のような課題がある。When a conductive thin film formed on a semiconductor wafer is used as a cathode electrode, the resistance of the thin film is high, so that the current density ratio between the vicinity of the power supply point and the place remote from the power supply point is low. growing. In the case of a semiconductor wafer, a portion suitable for power supply is extremely limited, such as the outer peripheral portion of the wafer. For this reason, the plating film thickness becomes thick near the feeding point (the outer peripheral portion of the wafer), and the film thickness distribution becomes non-uniform. At the outer peripheral portion of the wafer where the plating film thickness is increased, the resistance of the film is reduced, and the electric field is more likely to be concentrated. To avoid such problems,
As disclosed in JP-A-10-140392 and JP-A-10-130896, it is necessary to introduce a current shielding plate to make the current density distribution on the wafer uniform. However, in Japanese Patent Application Laid-Open No. 10-140392, the cause of the non-uniformity of the current distribution is not based on the thin-film resistance, but is caused by the geometrical shape of the electrodes and the device. Not the shape and arrangement. Further, when the aperture ratio of the shielding plate and the position of the shielding plate are changed on-line as in JP-A-10-130896, there are the following problems.
【０００９】（１）半導体ウェハ上に形成する導電性薄
膜の厚さは通常１〜２μｍ以下と薄く、かつ成膜速度が
１００ｎｍ／min 以上と高いために最適な遮蔽板穴径お
よび遮蔽板位置を探索し穴径および位置を変化させてい
る時間内にめっき処理が終了してしまう。(1) The thickness of the conductive thin film formed on the semiconductor wafer is usually as thin as 1 to 2 μm or less, and the film forming rate is as high as 100 nm / min or more, so that the optimum hole diameter and position of the shield plate are optimal. And the plating process is completed within a time period in which the hole diameter and the position are changed.
【００１０】（２）遮蔽板の開口率，遮蔽板の位置を電
流密度の計測結果にしたがって自動的に変化させる装置
が必要なため装置コストが上昇する。(2) Since a device for automatically changing the aperture ratio of the shielding plate and the position of the shielding plate in accordance with the current density measurement result is required, the cost of the device increases.
【００１１】（３）特に半導体ウェハにウェハ外周部か
ら給電するタイプのめっき装置の場合には、ウェハの外
周部付近で電流密度が増大する。このため、ウェハ外周
部の電流密度を抑制するような形状の遮蔽板を用意する
必要があるがこれに対応していない。(3) Particularly in the case of a plating apparatus of a type in which power is supplied to a semiconductor wafer from the outer periphery of the wafer, the current density increases near the outer periphery of the wafer. For this reason, it is necessary to prepare a shielding plate having a shape that suppresses the current density at the outer peripheral portion of the wafer, but this is not supported.
【００１２】また、半導体ウェハに形成した導電性薄膜
に特有の課題として、めっき後に導電性膜を化学機械研
磨処理（ＣＭＰ）した場合に、めっき層の厚いウェハ外
周部だけが削り残しとなる課題が挙げられる。上記の公
知例ではいずれもこの課題を解決することが困難であ
る。Another problem specific to the conductive thin film formed on the semiconductor wafer is that when the conductive film is subjected to chemical mechanical polishing (CMP) after plating, only the outer peripheral portion of the wafer having a thick plating layer is left uncut. Is mentioned. In any of the above-mentioned known examples, it is difficult to solve this problem.
【００１３】本発明の目的は、簡潔な構造のめっき装置
により、ウェハ外周部めっき層厚さがウェハ内側のめっ
き層厚さより薄く、かつ半導体ウェハ上の外周部を除く
広い面積において均一な厚さのめっき層を形成可能なめ
っき装置およびめっき方法を提供することにある。An object of the present invention is to provide a plating apparatus having a simple structure, wherein the thickness of a plating layer on the outer peripheral portion of a wafer is smaller than the thickness of a plating layer on the inner side of the wafer, and the thickness is uniform over a wide area excluding the outer peripheral portion on the semiconductor wafer. It is an object of the present invention to provide a plating apparatus and a plating method capable of forming a plating layer.
【００１４】また、本発明の目的は、均一な厚さのめっ
き層を有する半導体ウェハおよびその製造法を提供する
ことにある。Another object of the present invention is to provide a semiconductor wafer having a plating layer having a uniform thickness and a method for manufacturing the same.
【００１５】[0015]
【課題を解決するための手段】本発明では、めっき処理
された半導体ウェハの外周部めっき層厚さがウェハ外周
部より内側のめっき層厚さより薄くなるようにめっきす
ることを特徴とするめっき方法が提供される。外周部で
のめっき膜厚が厚い場合、めっき層を化学機械研磨（Ｃ
ＭＰ）処理する際に研磨残りが生じるなどの不具合が発
生する。これに対し、ウェハ外周部のめっき層厚さを抑
制した場合では、上記不具合を回避できる。また、給電
点とウェハとの接触抵抗により生じるウェハ面内でのめ
っき層厚さの不均一性を抑制可能である。ウェハ外周部
でめっき層が極端に薄くなる場合にはウェハ外周部をカ
ットするなどして除外すれば対処できる。According to the present invention, a plating method is characterized in that plating is performed so that the thickness of a plating layer on an outer peripheral portion of a plated semiconductor wafer is smaller than the thickness of a plating layer on the inner side of the outer peripheral portion of the wafer. Is provided. If the plating thickness at the outer periphery is large, the plating layer is chemically mechanically polished (C
When performing the MP) treatment, defects such as remaining polishing may occur. On the other hand, when the thickness of the plating layer at the outer peripheral portion of the wafer is suppressed, the above problem can be avoided. Further, the nonuniformity of the thickness of the plating layer in the wafer surface caused by the contact resistance between the power supply point and the wafer can be suppressed. In the case where the plating layer becomes extremely thin in the outer peripheral portion of the wafer, it can be dealt with by excluding it by cutting the outer peripheral portion of the wafer.
【００１６】好ましくは半導体ウェハ上に形成された導
電性物質に、半導体ウェハ外周部から給電してカソード
電極とする電気めっき装置において、めっき液が満たさ
れた筒状のめっき槽と、前記筒状のめっき槽の上下に対
向させて配置したカソード電極およびアノード電極と、
前記めっき槽の内壁に接しカソード電極とアノード電極
の間に両者に平行に配置された有孔の１つもしくは複数
の電流遮蔽板とからなることを特徴とするめっき装置が
提供される。これにより、めっき処理された半導体ウェ
ハの端部めっき層厚さがウェハ中心側のめっき層厚さよ
り薄くなり、外周部を除くウェハの広い面積において均
一な厚さのめっき層が形成される。また、簡潔な構造の
めっき装置により均一な膜厚のめっき層が形成可能とな
る。Preferably, in an electroplating apparatus in which a conductive material formed on a semiconductor wafer is supplied from an outer peripheral portion of the semiconductor wafer to serve as a cathode electrode, a tubular plating tank filled with a plating solution; A cathode electrode and an anode electrode arranged oppositely above and below the plating tank,
There is provided a plating apparatus comprising one or a plurality of perforated current shield plates disposed in parallel with the cathode electrode and the anode electrode in contact with the inner wall of the plating tank. As a result, the thickness of the plating layer at the end of the plated semiconductor wafer becomes smaller than the thickness of the plating layer on the center side of the wafer, and a plating layer having a uniform thickness is formed over a wide area of the wafer excluding the outer peripheral portion. Further, a plating layer having a uniform thickness can be formed by a plating apparatus having a simple structure.
【００１７】好ましくは、上記めっき装置において、電
流遮蔽板がめっき槽の筒と中心軸を共有する円形の孔を
持つ円板であることを特徴とするめっき装置が提供され
る。これにより、めっき処理された半導体ウェハの端部
めっき層厚さがウェハ中心側のめっき層厚さより薄くな
り、外周部を除くウェハの広い面積において均一な厚さ
のめっき層が形成される。また、構造が単純で、かつメ
ンテナンスの負担が少なく、均一なめっき層を形成可能
なめっき装置が提供される。Preferably, in the above plating apparatus, there is provided a plating apparatus, wherein the current shielding plate is a circular plate having a circular hole sharing a central axis with the cylinder of the plating tank. As a result, the thickness of the plating layer at the end of the plated semiconductor wafer becomes smaller than the thickness of the plating layer on the center side of the wafer, and a plating layer having a uniform thickness is formed over a wide area of the wafer excluding the outer peripheral portion. Further, there is provided a plating apparatus which has a simple structure, requires less maintenance, and can form a uniform plating layer.
【００１８】好ましくは、上記めっき装置において、カ
ソード電極上〜カソード電極からカソード電極とアノー
ド電極の距離の８分の１の位置にカソード電極の径の
０.８〜１.０ 倍の口径の孔を持つ電流遮蔽板を配置す
ることを特徴とするめっき装置が提供される。これによ
り、ウェハ外周部の膜厚を外周部よりウェハ中心側の膜
厚より効率よく削減することができ、ウェハ外周部を除
くウェハの広い面積において均一な厚さのめっき層が形
成される。Preferably, in the above plating apparatus, a hole having a diameter of 0.8 to 1.0 times the diameter of the cathode electrode is provided at a position on the cathode electrode to one eighth of the distance between the cathode electrode and the anode electrode from the cathode electrode. And a plating apparatus characterized by disposing a current shielding plate having the following. As a result, the thickness of the outer peripheral portion of the wafer can be reduced more efficiently than the thickness of the central portion of the wafer from the outer peripheral portion, and a plating layer having a uniform thickness can be formed over a wide area of the wafer excluding the outer peripheral portion of the wafer.
【００１９】好ましくは、上記めっき装置において、上
記電流遮蔽板に加え、カソード電極からカソード電極と
アノード電極の距離の８分の１〜８分の６の位置にカソ
ード電極の径の０.７〜１.０倍の口径の孔を持つ電流遮
蔽板を配置することを特徴とするめっき装置が提供され
る。これによりウェハ外周部の膜厚を抑制し、かつウェ
ハ外周部を除いた部分の膜厚分布を均一化することがで
きる。Preferably, in the above plating apparatus, in addition to the current shielding plate, the cathode electrode has a diameter of 0.7 to 8 at a distance of 1/8 to 6/8 of the distance between the cathode and the anode from the cathode. There is provided a plating apparatus characterized by disposing a current shielding plate having a hole having a diameter of 1.0 times. This makes it possible to suppress the film thickness at the outer peripheral portion of the wafer and to make the film thickness distribution at a portion other than the outer peripheral portion of the wafer uniform.
【００２０】好ましくは、上記めっき装置において、請
求項７記載の電流遮蔽板に加え、カソード電極からカソ
ード電極とアノード電極の距離の８分の６の位置〜アノ
ード電極上にカソード電極の径の０.５〜１.０の口径の
孔を持つ電流遮蔽板を配置することを特徴とするめっき
装置が提供される。これにより、ウェハ外周部の膜厚を
抑制し、かつウェハ外周部を除いた部分の膜厚分布を均
一化することができる。Preferably, in the above plating apparatus, in addition to the current shielding plate according to claim 7, the distance between the cathode electrode and the cathode electrode and the distance between the cathode electrode and the anode electrode is 6/8 of the distance between the cathode electrode and the anode electrode. A plating apparatus is provided, wherein a current shielding plate having a hole having a diameter of 0.5 to 1.0 is arranged. This makes it possible to suppress the film thickness in the outer peripheral portion of the wafer and to make the film thickness distribution in the portion excluding the outer peripheral portion of the wafer uniform.
【００２１】好ましくは、上記めっき装置において、め
っき処理を実施する以前にカソード電極上の電流密度を
測定する手段と、前記測定手段により測定された電流密
度分布がカソード電極上で均一になるようカソード電極
とアノード電極の間の最適な位置に電流遮蔽板を設置す
る手段とを備えたことを特徴とするめっき装置が提供さ
れる。これにより、ウェハ上のめっき層厚さをより均一
化することができる。好ましくは、上記めっき方法およ
びめっき装置を用いた半導体ウェハの製造法において、
めっき処理後のウェハを化学機械研磨（ＣＭＰ）処理し
てウェハ上の平坦部および凸部の導電性薄膜を研磨しウ
ェハ凹部のみに導電性薄膜を残留させることを特徴とす
る半導体ウェハの製造法が提供される。これにより、ウ
ェハ上のめっき層の削れ残りおよび過剰研磨を抑制で
き、半導体チップ歩留まりの向上が可能となる。また、
過剰研磨を抑制できるために、素子の信頼性が向上す
る。これは、過剰研磨を防ぐことによって配線のコンタ
クト不良が抑制されることによる。さらに、ＣＭＰ処理
時間自体も外周部に平均膜厚より３０％以上膜厚の厚い
領域が存在する場合に比較して、約５０％程度に抑制で
きる。Preferably, in the plating apparatus, means for measuring a current density on the cathode electrode before performing a plating process, and a cathode so that the current density distribution measured by the measuring means is uniform on the cathode electrode. Means for installing a current shielding plate at an optimum position between the electrode and the anode electrode. Thereby, the thickness of the plating layer on the wafer can be made more uniform. Preferably, in the method of manufacturing a semiconductor wafer using the plating method and the plating apparatus,
A method of manufacturing a semiconductor wafer, wherein a wafer after plating is subjected to chemical mechanical polishing (CMP) processing to polish a conductive thin film on a flat portion and a convex portion on the wafer and to leave the conductive thin film only in a concave portion of the wafer. Is provided. As a result, it is possible to suppress the remaining of the plating layer on the wafer and the excessive polishing, and it is possible to improve the yield of semiconductor chips. Also,
Since the excessive polishing can be suppressed, the reliability of the element is improved. This is because the contact failure of the wiring is suppressed by preventing the excessive polishing. Further, the CMP processing time itself can be suppressed to about 50% as compared with a case where a region having a thickness of 30% or more than the average film thickness exists in the outer peripheral portion.
【００２２】[0022]
【発明の実施の形態】（実施例１）図１に本発明に係る
めっき装置の断面図を示す。めっき装置は、円筒型の絶
縁壁５に囲まれためっき槽７と、絶縁壁５の上口及び下
口に対向して取り付けられた円形の半導体ウェハ（以
下、ウェハと称する場合もある。)(これは、ウェハ上の
少なくとも一方の面の略全面を覆うように、スパッタ法
にて、膜厚１５０ｎｍ程度の種となる銅薄膜が形成さ
れ、カソード電極として機能する。以下同様である。）
２及びアノード電極１からなる。絶縁壁５は、長さ１２
０mm，内径１８２mmの大きさである。円形のアノード電
極１（銅電極）は直径１８２mmで、中心に直径３０mmの
めっき液入り口６１の円孔が設置されている。また、ウ
ェハ（カソード電極）２の直径は２００mmである。ウェ
ハ２はその外周面上の銅薄膜が、電極４と接し定電流源
８により給電される。めっき槽７中では、アノード電極
１とウェハ（カソード電極）２の間に電流が流れる。め
っき槽７はめっき液で満たされている。めっき液及び添
加剤等投入口１０より投入されためっきの平滑剤，光沢
剤はポンプ９によってめっき液入り口６１，めっき液出
口６２およびめっき槽７を循環し撹拌される。めっき液
はめっき液冷却器１１によって一定温度（２０℃）に保
たれる。電流遮蔽板３１〜３３はめっき作業毎に穴径の
異なる電流遮蔽板に付け替え可能で、かつ設置高さ（ウ
ェハ２面からの距離）を変化させることができる。電流
遮蔽板円孔は絶縁壁５と中心軸を共有しているため、付
け替え作業を容易に行うことが可能である。電流遮蔽板
３１は、ウェハ２面から３mm〜１５mmの間で移動可能で
ある。また、電流遮蔽板３２はウェハ２面から１５mm〜
９０mmの間で、電流遮蔽板３３はウェハ２面から９０mm
〜１２０mmの間で移動可能である。電流遮蔽板３１〜３
３がない場合、ウェハ２の給電部の電極４がウェハ２の
外周部にあるためにウェハ２の外周部膜厚が厚くなる。
電流遮蔽板３１はウェハ外周部（ウェハ中心からおよそ
８０mm〜の外側）の膜厚が小さくする効果を持つ。さら
に、電流遮蔽板３２，３３を取り付けることによって、
ウェハ中心部（ウェハ中心からおよそ８０mmの内側）の
平坦化が可能になる。こうして、ウェハ外周部の膜厚が
薄い領域は不使用部として除外し、平坦な中心部を使用
領域とすれば、ＣＭＰの際に不使用領域に研磨残りが生
じない。また、外周部でのめっき膜厚が抑制されている
ため、ウェハ２外周部と電極４の接触不均一性等に起因
したウェハ２の周方向不均一性を改善可能である。(Embodiment 1) FIG. 1 is a sectional view of a plating apparatus according to the present invention. The plating apparatus includes a plating tank 7 surrounded by a cylindrical insulating wall 5, and a circular semiconductor wafer (hereinafter, may be referred to as a wafer) mounted opposite to an upper opening and a lower opening of the insulating wall 5. (In this method, a seed copper thin film having a thickness of about 150 nm is formed by a sputtering method so as to cover at least substantially the entire surface of at least one surface of the wafer, and functions as a cathode electrode. The same applies hereinafter.)
2 and an anode electrode 1. The insulating wall 5 has a length of 12
It has a size of 0 mm and an inner diameter of 182 mm. The circular anode electrode 1 (copper electrode) has a diameter of 182 mm, and a circular hole of a plating solution inlet 61 having a diameter of 30 mm is provided at the center. The diameter of the wafer (cathode electrode) 2 is 200 mm. The copper thin film on the outer peripheral surface of the wafer 2 contacts the electrode 4 and is supplied with power by the constant current source 8. In the plating tank 7, a current flows between the anode electrode 1 and the wafer (cathode electrode) 2. The plating tank 7 is filled with a plating solution. The plating smoothing agent and brightening agent supplied from the inlet 10 for the plating solution and additives are circulated by the pump 9 through the plating solution inlet 61, the plating solution outlet 62 and the plating tank 7 and stirred. The plating solution is maintained at a constant temperature (20 ° C.) by the plating solution cooler 11. The current shielding plates 31 to 33 can be replaced with current shielding plates having different hole diameters for each plating operation, and the installation height (distance from the wafer 2 surface) can be changed. Since the current shield plate circular hole shares the central axis with the insulating wall 5, replacement work can be easily performed. The current shielding plate 31 is movable between 3 mm and 15 mm from the wafer 2 surface. The current shield plate 32 is 15 mm or more from the wafer 2 surface.
Between 90 mm, the current shielding plate 33 is 90 mm from the wafer 2 surface.
It can move between ~ 120mm. Current shielding plates 31 to 3
In the case where there is no 3, the outer peripheral film thickness of the wafer 2 is increased because the electrode 4 of the power supply portion of the wafer 2 is located on the outer peripheral portion of the wafer 2.
The current shielding plate 31 has the effect of reducing the film thickness at the outer peripheral portion of the wafer (outside of the wafer center from about 80 mm). Further, by attaching the current shielding plates 32 and 33,
It is possible to flatten the center of the wafer (about 80 mm inside the center of the wafer). In this manner, if the region where the film thickness at the outer peripheral portion of the wafer is thin is excluded as an unused portion and the flat central portion is used as a used region, no polishing residue is generated in the unused region during CMP. Further, since the plating film thickness at the outer peripheral portion is suppressed, it is possible to improve the non-uniformity in the circumferential direction of the wafer 2 due to the non-uniform contact between the outer peripheral portion of the wafer 2 and the electrode 4 and the like.
【００２３】次に、上記のような電流遮蔽板の効果を確
かめるため、０.１５μｍ の銅薄膜が表面に一様に付着
した半導体ウェハに銅めっきを施したときの計算機シミ
ュレーションを実施した。シミュレーションでは、アノ
ード及びカソード電極間に２.６Ａ の電流を流したとき
のウェハ面上の電流密度分布を計算し膜厚分布を求め
た。めっき液は硫酸銅水溶液であり電気伝導度は５０Ｓ
／ｍ、アノード・カソード電極上のめっき反応により生
じる過電圧は、アノード電極に対して0.0278Log（ｉ)
［Ｖ］、カソード電極に対して０.０５６５Log（ｉ）
［Ｖ］（ｉは電流密度［Ａ／ｍ2］)で与えられる。各々
の計算においては、電流遮蔽板３１〜３３の穴径及び設
置位置のみを様々に変化させた。図２に、電流遮蔽板３
２，３３を取り付け、３１を外した場合の膜厚分布の実
験結果および計算結果を示す。電流遮蔽板３３はウェハ
面から１１０mmに設置しかつ穴径１６０mmのもの、電流
遮蔽板３２は、ウェハ面から３８mmに設置しかつ穴径１
５０，１６０，１７０mmのものを使用しそれぞれ実験と
比較した。実験結果の縦軸は、シート抵抗の逆数を規格
化したのもので膜厚に比例する。計算結果はＣｕを平均
１.１μｍ 程度堆積させた後の膜厚分布である。図２よ
り、計算は実験結果をよく表すことができ、また電流遮
蔽板の上記効果を確認できた。以上のように、電流遮蔽
板３１〜３３の設置により膜厚分布を制御することがで
きる。Next, in order to confirm the effect of the above-described current shield plate, a computer simulation was performed when a semiconductor wafer having a 0.15 μm copper thin film uniformly adhered to the surface was plated with copper. In the simulation, a current density distribution on the wafer surface when a current of 2.6 A was passed between the anode and the cathode was calculated to obtain a film thickness distribution. The plating solution is an aqueous solution of copper sulfate and the electric conductivity is 50S
/ M, the overvoltage caused by the plating reaction on the anode / cathode electrode is 0.0278Log (i) with respect to the anode electrode.
[V], 0.0565 Log (i) with respect to the cathode electrode
[V] (i is the current density [A / m 2 ]). In each calculation, only the hole diameters and installation positions of the current shielding plates 31 to 33 were variously changed. FIG. 2 shows the current shield plate 3
The experimental and calculated results of the film thickness distribution when 2 and 33 are attached and 31 is removed are shown. The current shielding plate 33 is installed at 110 mm from the wafer surface and has a hole diameter of 160 mm. The current shielding plate 32 is installed at 38 mm from the wafer surface and has a hole diameter of 1 mm.
50 mm, 160 mm and 170 mm were used and compared with the experiments. The vertical axis of the experimental result is obtained by normalizing the reciprocal of the sheet resistance and is proportional to the film thickness. The calculation result is a film thickness distribution after Cu is deposited on average by about 1.1 μm. From FIG. 2, the calculation can well express the experimental result, and the above effect of the current shielding plate can be confirmed. As described above, the film thickness distribution can be controlled by providing the current shielding plates 31 to 33.
【００２４】（実施例２）上記実施例において、ウェハ
２面から５mm下に穴径１７０mmの電流遮蔽板３１を設置
し、電流遮蔽板３２，３３を取り付けない場合の膜厚分
布を計算した。ここでは、ウェハ２面の直下に設置した
電流遮蔽板３１がウェハ２面上の膜厚分布に及ぼす効果
について説明する。(Example 2) In the above example, the film thickness distribution was calculated when the current shielding plate 31 having a hole diameter of 170 mm was installed 5 mm below the surface of the wafer 2 and the current shielding plates 32 and 33 were not attached. Here, the effect of the current shielding plate 31 provided immediately below the wafer 2 surface on the film thickness distribution on the wafer 2 surface will be described.
【００２５】図３に、図１の装置における電流遮蔽板３
１〜３３がどれも設置されていない場合で、Ｃｕを平均
１.１μｍ ほど堆積させた後の膜厚分布シミュレーショ
ン結果を示す。電極４がウェハ２外周部で接しているた
め、Ｃｕ膜抵抗の効果でウェハ２外周部膜厚が盛り上が
ることが分かる。FIG. 3 shows the current shield plate 3 in the apparatus shown in FIG.
The results of a simulation of the film thickness distribution after Cu is deposited to an average of about 1.1 μm when none of the samples 1 to 33 are provided are shown. Since the electrode 4 is in contact with the outer peripheral portion of the wafer 2, it can be seen that the thickness of the outer peripheral portion of the wafer 2 rises due to the effect of the Cu film resistance.
【００２６】図４に、図１の装置において内径１７０mm
の電流遮蔽板３１をウェハ２面から５mmの位置に設置
し、電流遮蔽板３２，３３は取り付けないときの、Ｃｕ
を1.1μｍほど堆積させた後の膜厚分布シミュレーショ
ン結果を示す。図３，図４を比較すると、電流遮蔽板３
１によってウェハ２の中心からおよそ半径８０mm〜の外
側で膜厚が小さくなることが分かる。FIG. 4 shows that the apparatus shown in FIG.
When the current shielding plate 31 is set at a position 5 mm from the surface of the wafer 2 and the current shielding plates 32 and 33 are not attached, Cu
Shows the results of a film thickness distribution simulation after depositing about 1.1 μm. 3 and 4, the current shielding plate 3
1 indicates that the film thickness becomes smaller outside the radius of about 80 mm from the center of the wafer 2.
【００２７】以上のように、電流遮蔽板３１のようなウ
ェハ２に近い距離に電流遮蔽板を設置すると、ウェハ２
の外周部で膜厚が薄くなる効果がある。上記条件のもと
で、様々に電流遮蔽板３１の穴径を変化させシミュレー
ションしたところ、穴径170mmのものがウェハ２外周部
の膜厚の落ち込みが鋭くなる事が判明した。As described above, when the current shielding plate such as the current shielding plate 31 is installed at a distance close to the wafer 2, the wafer 2
The effect is that the film thickness becomes thinner at the outer peripheral portion. Under the above conditions, simulation was performed by changing the hole diameter of the current shielding plate 31 variously. As a result, it was found that the one having a hole diameter of 170 mm had a sharp drop in the film thickness at the outer peripheral portion of the wafer 2.
【００２８】（実施例３）上記実施例において、更に電
流遮蔽板を追加した場合のシミュレーション結果につい
て説明する。ここでは、ウェハ２中心部からおよそ半径
８０mm以内の領域の膜厚を平坦化する。本実施例では、
実施例２で用いた電流遮蔽板３１（ウェハ２面から５m
m，穴径１７０mm）に加え、ウェハ２面から３８mm下に
電流遮蔽板３２を更に付け加える。(Embodiment 3) A simulation result in a case where a current shield plate is further added in the above embodiment will be described. Here, the film thickness in a region within a radius of about 80 mm from the center of the wafer 2 is flattened. In this embodiment,
The current shielding plate 31 used in Example 2 (5 m from the wafer 2 surface)
m, hole diameter 170 mm) and a current shielding plate 32 38 mm below the wafer 2 surface.
【００２９】図５は上記条件で、電流遮蔽板３２の穴径
を１５０mm及び１６０mmにした場合それぞれについて、
Ｃｕを１.１μｍ ほど堆積させた場合のウェハ２の膜厚
分布を示す。図４と比較して半径８０mm以内の領域でよ
り平坦化していることが分かる。また、電流遮蔽板３２
の内径を小さくすると中央部が盛り上がる効果があるこ
とが分かる。FIG. 5 shows the results obtained when the hole diameter of the current shielding plate 32 is set to 150 mm and 160 mm under the above conditions.
The thickness distribution of the wafer 2 when Cu is deposited to a thickness of about 1.1 μm is shown. It can be seen that the surface is flattened in a region within a radius of 80 mm as compared with FIG. In addition, the current shielding plate 32
It can be seen that the smaller the inner diameter of, there is an effect of raising the central portion.
【００３０】以上のように、電流遮蔽板３２により中心
部の膜厚平坦化を行うことができる。上記条件の下で、
電流遮蔽板３２の穴径を変化させたところ、穴径１６０
mmのものが最も中心部の平坦性が改善されることがわか
る。As described above, the central portion can be made flat by the current shielding plate 32. Under the above conditions,
When the hole diameter of the current shielding plate 32 was changed, the hole diameter 160
It can be seen that the flatness of the center part is most improved in the case of mm.
【００３１】（実施例４）上記実施例において、更に電
流遮蔽板を加えたものも同様の効果を奏する。図１にお
いて、実施例３で用いた電流遮蔽板３１（ウェハ２面か
ら５mm，穴径170mm）及び電流遮蔽板３２（ウェハ２面
から３８mm，穴径１５０mm）に加え、ウェハ２面から１
１０mm下に電流遮蔽板３３をさらに付け加えた例につい
て説明する。(Embodiment 4) In the above embodiment, the same effect can be obtained by further adding a current shielding plate. In FIG. 1, in addition to the current shielding plate 31 (5 mm from the wafer 2 surface, hole diameter 170 mm) and the current shielding plate 32 (38 mm from the wafer 2 surface, hole diameter 150 mm) used in the third embodiment, and 1 mm from the wafer 2 surface.
An example in which the current shielding plate 33 is further added 10 mm below will be described.
【００３２】図６に、上記条件で、電流遮蔽板３３の内
径を１２０mm及び１６０mmにした場合それぞれについ
て、Ｃｕを１.１μｍ ほど堆積させた場合のウェハ２面
の膜厚分布シミュレーション結果を示す。図５と比較し
て特に半径４０mm以内の領域でより盛り上がり、また、
電流遮蔽板３３の内径を小さくすると中央部が盛り上が
ることが分かる。FIG. 6 shows a simulation result of the film thickness distribution on the surface of the wafer 2 when Cu is deposited to a thickness of about 1.1 μm under the above conditions when the inner diameter of the current shielding plate 33 is set to 120 mm and 160 mm, respectively. Compared to FIG. 5, especially in the area within a radius of 40 mm, swells more,
It can be seen that the central portion rises when the inner diameter of the current shielding plate 33 is reduced.
【００３３】以上のように、電流遮蔽板３２，３３を用
いて、より中心部の膜厚平坦化を行うことができる。上
記の条件のもとで、様々に電流遮蔽板３２，３３の穴径
を変化させたところ、電流遮蔽板３２が１６０mm、電流
遮蔽板３３が１４０の時に最も中心部の平坦性が改善さ
れることが判明した。As described above, the thickness of the central portion can be further flattened by using the current shielding plates 32 and 33. Under the above conditions, when the hole diameters of the current shielding plates 32 and 33 are variously changed, the flatness of the center portion is most improved when the current shielding plate 32 is 160 mm and the current shielding plate 33 is 140. It has been found.
【００３４】（実施例５）ここでは、実施例１における
電流遮蔽板３１を上下に平行移動可能にした場合の効果
について説明する。実施例１同様、電流遮蔽板３２（ウ
ェハ２面から３８mm）及び電流遮蔽板３３（ウェハ２面
から１１０mm）も設置する。(Embodiment 5) Here, the effect when the current shielding plate 31 in Embodiment 1 can be moved up and down in parallel will be described. As in the first embodiment, a current shielding plate 32 (38 mm from the wafer 2 surface) and a current shielding plate 33 (110 mm from the wafer 2 surface) are also installed.
【００３５】図７に、上記条件で電流遮蔽板３１を上下
に平行移動を行い（ウェハ２面から３mm，１０mm）、Ｃ
ｕを１.１μｍ ほど堆積させた場合のウェハ２面の膜厚
分布シミュレーション結果を示す。この際、電流遮蔽板
３１，３２，３３を中心部の平坦性がよくなるように穴
径を調節した。電流遮蔽板３１をウェハ２に近づける
と、落ち込みの起こる変局点は外側に変化することが分
かる。FIG. 7 shows that the current shielding plate 31 is moved up and down in parallel under the above conditions (3 mm and 10 mm from the wafer 2 surface).
The results of a film thickness distribution simulation on the surface of the wafer 2 when u is deposited to about 1.1 μm are shown. At this time, the hole diameters of the current shielding plates 31, 32, and 33 were adjusted so as to improve the flatness of the central portion. When the current shielding plate 31 is brought closer to the wafer 2, the inflection point at which the drop occurs changes outward.
【００３６】以上のように、電流遮蔽板３１の設置位置
を変化させると、外周部の面積が変化する。上記条件の
もとで、電流遮蔽板３１をウェハ２面から３mm〜１５mm
の間で変化させ、電流遮蔽板３１，３２，３３の穴径を
様々に変化させたところ、中心部が広くかつ平坦性のよ
い組み合わせは電流遮蔽板３１がウェハ２面から３mmの
距離で穴径が１７０mm、電流遮蔽板３２の穴径が１６０
mm、電流遮蔽板３３の穴径が１４０mmであることが分か
った。As described above, when the installation position of the current shielding plate 31 is changed, the area of the outer peripheral portion changes. Under the above conditions, the current shielding plate 31 is 3 mm to 15 mm from the wafer 2 surface.
And the hole diameters of the current shielding plates 31, 32, and 33 were variously changed, the combination having a wide central portion and good flatness is such that the current shielding plate 31 has a hole at a distance of 3 mm from the wafer 2 surface. The diameter is 170 mm and the hole diameter of the current shielding plate 32 is 160
mm, and the hole diameter of the current shielding plate 33 was found to be 140 mm.
【００３７】（実施例６）ここでは、上記条件と比較し
て、めっき前のウェハ２上のＣｕ膜厚分布に不均一性が
存在する場合にも電流遮蔽板３１〜３３を用いて対処で
きることを説明する。(Embodiment 6) Here, compared with the above conditions, even when there is non-uniformity in the Cu film thickness distribution on the wafer 2 before plating, it is possible to cope with the current shielding plates 31 to 33. Will be described.
【００３８】図８に、めっき前のウェハ上Ｃｕ膜厚分布
に傾斜があり、中心が０.１５μｍ、ウェハ２エッジが
０.２５μｍ となるような傾斜が存在する場合につい
て、電流遮蔽板３１〜３３を取り付けない条件で、めっ
きによりＣｕを１.１μｍ 程度堆積させた場合の膜厚分
布シミュレーション結果を示す。この場合、ウェハ２外
周部の抵抗が小さくなり、外周部により電流の集中が起
こるため、図２と比較して、より外周部の膜厚が大きく
なる。FIG. 8 shows the current shielding plates 31 to 31 in the case where the distribution of the Cu film thickness on the wafer before plating has an inclination such that the center is 0.15 μm and the edge of the wafer 2 is 0.25 μm. The results of a film thickness distribution simulation in the case where Cu is deposited to a thickness of about 1.1 μm by plating under the condition that no 33 is attached. In this case, the resistance at the outer peripheral portion of the wafer 2 becomes smaller, and current concentrates at the outer peripheral portion, so that the film thickness at the outer peripheral portion becomes larger than that in FIG.
【００３９】図９は、上記条件の下で電流遮蔽板３１〜
３３を用いて、Ｃｕを１.１μｍ 程度堆積させた後の膜
厚分布シミュレーション結果である。電流遮蔽板３１〜
３３の穴径及び設置位置を外周部の膜厚を小さくして、
中心部が平坦となるように設定した。電流遮蔽板３１は
設置位置がウェハ２面から３mm、穴径が１７０mmであ
る。電流遮蔽板３２は、設置位置がウェハ２面から３８
mm、穴径が１５０mm、電流遮蔽板３３は設置位置がウェ
ハ２面から１１０mm、穴径が１００mmである。FIG. 9 shows the current shielding plates 31 to 31 under the above conditions.
33 is a film thickness distribution simulation result after depositing Cu of about 1.1 μm using No. 33. Current shield plate 31-
The hole diameter of 33 and the installation position are reduced by reducing the thickness of the outer peripheral portion,
The center was set to be flat. The current shielding plate 31 is installed at a position 3 mm from the surface of the wafer 2 and has a hole diameter of 170 mm. The current shielding plate 32 is set at a position 38 from the wafer 2 surface.
mm, the hole diameter is 150 mm, and the installation position of the current shielding plate 33 is 110 mm from the surface of the wafer 2 and the hole diameter is 100 mm.
【００４０】以上のように、めっき前の条件が異なって
いる場合でも、電流遮蔽板３１〜３３の設置位置，穴径
を調整することにより膜厚分布を制御可能であることが
分かる。As described above, it can be seen that the film thickness distribution can be controlled by adjusting the installation positions and the hole diameters of the current shielding plates 31 to 33 even when the conditions before plating are different.
【００４１】通常の方法（遮蔽板を導入しない場合）で
外周部より給電を行った場合、図８のようにウェハ外周
部の膜厚が厚くなりウェハ中心に向かってゆるやかに減
少していくため、化学機械研磨（ＣＭＰ）処理時に広い
範囲で削れ残りもしくは過剰研磨領域が発生する。しか
し、図９のように外周部が薄く中心が平坦な膜厚分布を
した半導体ウェハにおいては、ＣＭＰ処理時において、
ウェハ外周部のみを不使用領域とすれば削れ残りおよび
過剰研磨を抑制できる。When power is supplied from the outer peripheral portion by a normal method (when the shielding plate is not introduced), the film thickness at the outer peripheral portion of the wafer increases as shown in FIG. 8 and gradually decreases toward the center of the wafer. In addition, during the chemical mechanical polishing (CMP) process, uncut or excessively polished regions occur in a wide range. However, in a semiconductor wafer having a film thickness distribution in which the outer peripheral portion is thin and the center is flat as shown in FIG.
If only the outer peripheral portion of the wafer is set as the non-use area, the uncut portion and excessive polishing can be suppressed.
【００４２】（実施例７）上記実施例に述べためっき方
法およびめっき装置を用いることにより、半導体ウェハ
上でのめっき層厚さをウェハ外周部で薄く、それより内
側の領域で均一としたウェハを製造可能である。このウ
ェハの表面に形成された銅薄膜を化学機械研磨処理（Ｃ
ＭＰ）するプロセスについて図１０を用いて以下に説明
する。(Embodiment 7) By using the plating method and the plating apparatus described in the above embodiment, the thickness of the plating layer on the semiconductor wafer is made thinner at the outer peripheral portion of the wafer, and is made uniform in the region inside the wafer. Can be manufactured. The copper thin film formed on the surface of this wafer is subjected to chemical mechanical polishing (C
MP) will be described below with reference to FIG.
【００４３】図１０における半導体処理装置は、化学機
械研磨（ＣＭＰ）処理系１００，信号伝達系２０１，２
０２，制御系３０１，膜厚測定系４０１およびウェハ搬
送系５０１から構成される。また、ＣＭＰ処理系１００
は研磨パッド１０２，パッド駆動モータ１０１，処理液
供給装置５０１から構成され、ＣＭＰ処理系１００内に
は処理対象となるウェハ２がセットされる。膜厚測定系
４０１にはめっき処理されたウェハ２１がセットされ
る。The semiconductor processing apparatus shown in FIG. 10 includes a chemical mechanical polishing (CMP) processing system 100, a signal transmission system 201,
02, a control system 301, a film thickness measurement system 401, and a wafer transfer system 501. Also, the CMP processing system 100
Is composed of a polishing pad 102, a pad driving motor 101, and a processing liquid supply device 501, and a wafer 2 to be processed is set in the CMP processing system 100. The plated wafer 21 is set in the film thickness measurement system 401.
【００４４】図１０の半導体処理装置の動作について以
下に説明する。The operation of the semiconductor processing apparatus shown in FIG. 10 will be described below.
【００４５】めっき処理されたウェハ２１は、ウェハ面
内の膜厚分布を膜厚測定系４０１によって測定された
後、搬送系６０１によってＣＭＰ処理系１００に運ばれ
る。膜厚分布のデータは、信号伝達系２０１によって制
御系３０１に伝えられ膜厚分布が最も均一になるようパ
ッド駆動モータ１０１を制御する。The plated wafer 21 is transferred to the CMP processing system 100 by the transfer system 601 after the thickness distribution in the wafer surface is measured by the film thickness measurement system 401. The data of the film thickness distribution is transmitted to the control system 301 by the signal transmission system 201, and controls the pad driving motor 101 so that the film thickness distribution becomes the most uniform.
【００４６】ここで、ウェハ表面のめっき層の状態につ
いて述べる。めっき処理した直後のウェハ２１は、銅が
ウェハの全面にコーティングされた状態となっている。
めっきの目的は、ウェハ上に配線を形成することである
から、配線を形成するべく設けたウェハ上の微細な溝
（幅１.０μｍ以下）および孔（直径１.０μｍ以下）以
外の場所の銅を除去する必要がある。このため、図１０
のＣＭＰ装置により銅を研磨する。研磨の際、ウェハ径
方向での研磨速度分布はある程度(±１０％程度)制御可
能であるが、めっき層の膜厚分布にそれ以上の大きな変
位が存在する場合、研磨残りが生じる。そこで、ウェハ
上のめっき層厚さはできるだけ均一にすることが求めら
れる。しかし、通常、ウェハ外周部から給電した場合に
は、ウェハ外周部の膜厚が厚くなり、その膜厚分布がウ
ェハ中心に向かってゆるやかに減少していくため、ＣＭ
Ｐ処理時に広い範囲で削れ残りもしくは過剰研磨領域が
発生する。本発明により、めっき処理を実施した場合で
は、ウェハ外周部で膜厚が減少する領域があり、それよ
り内側では膜厚分布はほぼ一定である。したがって、ウ
ェハ外周部のみを不使用領域とすれば削れ残りおよび過
剰研磨を抑制できる。これにより、半導体チップ歩留ま
りの大幅な向上が可能となる。また、本発明におけるめ
っき処理およびＣＭＰ処理した場合、過剰研磨を抑制で
きるために、素子の信頼性が向上する。これは、過剰研
磨を防ぐことによって配線のコンタクト不良が抑制され
ることによる。さらに、ＣＭＰ処理時間自体も外周部に
平均膜厚より３０％以上膜厚の厚い領域が存在する場合
に比較して、約５０％程度に抑制できると考えられる。Here, the state of the plating layer on the wafer surface will be described. The wafer 21 immediately after the plating process is in a state where copper is coated on the entire surface of the wafer.
Since the purpose of plating is to form wiring on the wafer, a portion of the wafer other than the fine grooves (width of 1.0 μm or less) and holes (diameter of 1.0 μm or less) provided on the wafer for forming the wiring is formed. Copper must be removed. Therefore, FIG.
Is polished by a CMP apparatus. At the time of polishing, the polishing rate distribution in the wafer diameter direction can be controlled to some extent (about ± 10%). However, if there is a larger displacement in the thickness distribution of the plating layer, polishing residue occurs. Therefore, it is required that the thickness of the plating layer on the wafer be as uniform as possible. However, in general, when power is supplied from the outer peripheral portion of the wafer, the thickness of the outer peripheral portion of the wafer increases, and the thickness distribution gradually decreases toward the center of the wafer.
During the P treatment, a large area is left uncut or excessively polished. When the plating process is performed according to the present invention, there is a region where the film thickness decreases at the outer peripheral portion of the wafer, and the film thickness distribution is substantially constant inside the region. Therefore, if only the outer peripheral portion of the wafer is set as the non-use area, the uncut portion and excessive polishing can be suppressed. As a result, the yield of semiconductor chips can be significantly improved. Further, in the case of performing the plating treatment and the CMP treatment in the present invention, since the excessive polishing can be suppressed, the reliability of the element is improved. This is because the contact failure of the wiring is suppressed by preventing the excessive polishing. Further, it is considered that the CMP processing time itself can be suppressed to about 50% as compared with the case where a region having a thickness of 30% or more than the average film thickness exists in the outer peripheral portion.
【００４７】以上によれば、簡潔な構造のめっき装置に
より、ウェハ外周部めっき層厚さがウェハ内側のめっき
層厚さより薄く、かつ半導体ウェハ上の外周部を除く広
い面積において均一な厚さのめっき層を形成可能であ
る。As described above, the plating apparatus having a simple structure allows the thickness of the plating layer on the outer peripheral portion of the wafer to be smaller than the thickness of the plating layer on the inner side of the wafer and the uniform thickness over a wide area excluding the outer peripheral portion on the semiconductor wafer. A plating layer can be formed.
【００４８】[0048]
【発明の効果】本発明によれば、簡潔な構造のめっき装
置により、良好なめっき層を形成可能なめっき装置およ
びめっき方法を提供できる。According to the present invention, it is possible to provide a plating apparatus and a plating method capable of forming a good plating layer with a plating apparatus having a simple structure.
【００４９】また、本発明によれば、均一な厚さのめっ
き層を有する半導体ウェハおよびその製造法を提供でき
る。Further, according to the present invention, it is possible to provide a semiconductor wafer having a plating layer having a uniform thickness and a method for manufacturing the same.
【図１】本発明の実施例のめっき装置概略断面図。FIG. 1 is a schematic sectional view of a plating apparatus according to an embodiment of the present invention.
【図２】本発明の実施例において、電流遮蔽板を取り付
けた場合の膜厚分布を示す図。FIG. 2 is a diagram showing a film thickness distribution when a current shielding plate is attached in the embodiment of the present invention.
【図３】本発明の実施例において、電流遮蔽板を取り付
けない条件での膜厚分布を示す図。FIG. 3 is a view showing a film thickness distribution under a condition where a current shielding plate is not attached in the embodiment of the present invention.
【図４】本発明の実施例において、電流遮蔽板を取り付
けたときの膜厚分布を示す図。FIG. 4 is a view showing a film thickness distribution when a current shielding plate is attached in the embodiment of the present invention.
【図５】本発明の実施例において、電流遮蔽板を取り付
けたときの膜厚分布を示す図。FIG. 5 is a diagram showing a film thickness distribution when a current shielding plate is attached in the embodiment of the present invention.
【図６】本発明の実施例において、電流遮蔽板を取り付
けたときの膜厚分布を示す図。FIG. 6 is a view showing a film thickness distribution when a current shielding plate is attached in the embodiment of the present invention.
【図７】本発明の実施例において、電流遮蔽板を取り付
けたときの膜厚分布を示す図。FIG. 7 is a view showing a film thickness distribution when a current shielding plate is attached in the embodiment of the present invention.
【図８】本発明の実施例において、電流遮蔽板を取り付
けない条件での膜厚分布を示す図。FIG. 8 is a view showing a film thickness distribution under a condition where a current shielding plate is not attached in the embodiment of the present invention.
【図９】本発明の実施例において、電流遮蔽板を取り付
けたときの膜厚分布を示す図。FIG. 9 is a view showing a film thickness distribution when a current shielding plate is attached in the embodiment of the present invention.
【図１０】本発明の実施例の半導体処理装置を示す図。FIG. 10 is a diagram showing a semiconductor processing apparatus according to an embodiment of the present invention.
１…アノード電極、２…ウェハ（カソード電極）、４…
電極、５…絶縁壁、７…めっき槽、８…定電流電源、９
…ポンプ、１０…添加剤等投入口、１１…めっき液冷却
器、３１，３２，３３…電流遮蔽板、６１…めっき液入
り口、６２…めっき液出口。1 ... Anode electrode, 2 ... Wafer (cathode electrode), 4 ...
Electrode, 5: insulating wall, 7: plating tank, 8: constant current power supply, 9
... Pump, 10 ... Addition of additives etc., 11 ... Plating solution cooler, 31, 32, 33 ... Current shielding plate, 61 ... Plating solution inlet, 62 ... Plating solution outlet.
フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 21/3205 Ｈ０１Ｌ 21/88 Ｋ (72)発明者 小林 金也 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 深田 晋一 東京都青梅市新町六丁目16番地の３ 株式 会社日立製作所デバイス開発センタ内 Ｆターム(参考） 4K023 AA19 BA06 4K024 AA09 BB12 CB01 CB21 GA02 4M104 BB04 DD37 DD52 HH20 5F033 HH11 MM01 PP15 PP27 QQ48 XX35 Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat II (Reference) H01L 21/3205 H01L 21/88 K (72) Inventor Kinya Kobayashi 7-1-1, Omikacho, Hitachi City, Hitachi, Ibaraki, Japan Hitachi, Ltd. Hitachi Research Laboratories (72) Inventor Shinichi Fukada 3-16-1, Shinmachi, Ome-shi, Tokyo F-term in Hitachi Device Development Center Co., Ltd. 4K023 AA19 BA06 4K024 AA09 BB12 CB01 CB21 GA02 4M104 BB04 DD37 DD52 HH20 5F033 HH11 MM01 PP15 PP27 QQ48 XX35
Claims (9)
半導体ウェハ外周部から給電してカソード電極とする電
気めっき法において、 めっき処理された半導体ウェハの外周部めっき層厚さが
ウェハ内側のめっき層厚さより薄くなるようにめっきす
ることを特徴とするめっき方法。In an electroplating method in which a conductive thin film formed on a semiconductor wafer is supplied with power from an outer peripheral portion of the semiconductor wafer to serve as a cathode electrode, a thickness of a plating layer on an outer peripheral portion of the plated semiconductor wafer is reduced. A plating method characterized by performing plating so as to be thinner than a plating layer thickness.
に、半導体ウェハ外周部から給電してカソード電極とす
る電気めっき装置において、 めっき液が満たされた筒状のめっき槽と、 前記筒状のめっき槽の上下に対向させて配置したカソー
ド電極およびアノード電極と、前記めっき槽の内壁に接
しカソード電極とアノード電極の間に両者に平行に配置
された有孔の１つもしくは複数の電流遮蔽板とからなる
ことを特徴とするめっき装置。2. An electroplating apparatus in which a conductive material formed on a semiconductor wafer is supplied from a peripheral portion of the semiconductor wafer to serve as a cathode electrode, wherein: a tubular plating tank filled with a plating solution; One or a plurality of perforated current shields having a cathode electrode and an anode electrode arranged above and below the plating tank facing each other, and a perforated hole in contact with the inner wall of the plating tank and arranged in parallel between the cathode electrode and the anode electrode; A plating apparatus comprising a plate.
遮蔽板がめっき槽の筒と中心軸を共有する円形の孔を持
つ円板であることを特徴とするめっき装置。3. The plating apparatus according to claim 2, wherein the current shielding plate is a circular plate having a circular hole sharing a central axis with the cylinder of the plating tank.
ード電極上からカソード電極とアノード電極の距離の８
分の１以内の位置にカソード電極の径の０.８〜１.０倍
の口径の孔を持つ電流遮蔽板を配置することを特徴とす
るめっき装置。4. The plating apparatus according to claim 3, wherein the distance between the cathode electrode and the anode electrode from above the cathode electrode is eight.
A plating apparatus, comprising: a current shielding plate having a hole having a diameter of 0.8 to 1.0 times the diameter of the cathode electrode at a position within one-half.
項４記載の電流遮蔽板に加え、カソード電極からカソー
ド電極とアノード電極の距離の８分の１〜８分の６の位
置にカソード電極の径の０.７〜１.０倍の口径の孔を持
つ電流遮蔽板を配置することを特徴とするめっき装置。5. The plating apparatus according to claim 4, wherein the cathode electrode is provided at a position of 1/8 to 6/8 of the distance between the cathode electrode and the anode electrode from the cathode electrode in addition to the current shielding plate according to claim 4. A current shield plate having a hole having a diameter of 0.7 to 1.0 times the diameter of the plating device.
項５記載の電流遮蔽板に加え、カソード電極からカソー
ド電極とアノード電極の距離の８分の６の位置からアノ
ード電極までの間にカソード電極の径の０.５〜１.０倍
の口径の孔を持つ電流遮蔽板を配置することを特徴とす
るめっき装置。6. A plating apparatus according to claim 5, further comprising, in addition to the current shielding plate according to claim 5, a cathode between a position of six-eighths of a distance between the cathode electrode and the anode electrode from the cathode electrode to an anode electrode. A plating apparatus comprising a current shielding plate having a hole having a diameter of 0.5 to 1.0 times the diameter of an electrode.
めっき処理を実施する以前にカソード電極上の電流密度
を測定する手段と、前記測定手段により測定された電流
密度分布がカソード電極上で均一になるようカソード電
極とアノード電極の間の最適な位置に電流遮蔽板を設置
する手段とを備えたことを特徴とするめっき装置。7. The plating apparatus according to claim 3, wherein
Means for measuring the current density on the cathode electrode before performing the plating process, and at an optimal position between the cathode electrode and the anode electrode so that the current density distribution measured by the measuring means is uniform on the cathode electrode. A means for installing a current shielding plate.
き装置を用いた半導体ウェハの製造法において、めっき
処理後のウェハを化学機械研磨処理してウェハ上の平坦
部および凸部の導電性薄膜を研磨しウェハ凹部のみに導
電性薄膜を残留させることを特徴とする半導体ウェハの
製造法。8. A plating method and a method of manufacturing a semiconductor wafer using a plating apparatus according to claim 1, wherein the wafer after plating is subjected to chemical mechanical polishing treatment to conduct conductivity of flat portions and projections on the wafer. A method of manufacturing a semiconductor wafer, comprising polishing a thin film and leaving a conductive thin film only in a concave portion of the wafer.
体ウェハにおいて、 めっき処理された半導体ウェハの外周部めっき層厚さが
ウェハ内側のめっき層厚さより薄いことを特徴とする半
導体ウェハ。9. A semiconductor wafer having a plating layer formed on a semiconductor wafer, wherein the thickness of the plating layer on the outer peripheral portion of the plated semiconductor wafer is smaller than the thickness of the plating layer on the inside of the wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10372817A JP2000195823A (en) | 1998-12-28 | 1998-12-28 | Plating method and plating apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10372817A JP2000195823A (en) | 1998-12-28 | 1998-12-28 | Plating method and plating apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000195823A true JP2000195823A (en) | 2000-07-14 |
Family
ID=18501095
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10372817A Pending JP2000195823A (en) | 1998-12-28 | 1998-12-28 | Plating method and plating apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000195823A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003010365A1 (en) * | 2001-07-25 | 2003-02-06 | Sharp Kabushiki Kaisha | Plating method and plating apparatus |
| JP2006339665A (en) * | 2000-10-12 | 2006-12-14 | Ebara Corp | Apparatus for manufacturing semiconductor substrate |
| CN100350078C (en) * | 2004-03-05 | 2007-11-21 | 日本梅克特隆株式会社 | Method for copperizing continuously |
| KR20140067948A (en) * | 2012-11-27 | 2014-06-05 | 램 리써치 코포레이션 | Method and apparatus for dynamic current distribution control during electroplating |
| JP2017137519A (en) * | 2016-02-01 | 2017-08-10 | 株式会社荏原製作所 | Plating device |
| US10017869B2 (en) | 2008-11-07 | 2018-07-10 | Novellus Systems, Inc. | Electroplating apparatus for tailored uniformity profile |
| JP6999070B1 (en) * | 2021-03-05 | 2022-02-10 | 株式会社荏原製作所 | How to adjust the plating module |
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1998
- 1998-12-28 JP JP10372817A patent/JP2000195823A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006339665A (en) * | 2000-10-12 | 2006-12-14 | Ebara Corp | Apparatus for manufacturing semiconductor substrate |
| WO2003010365A1 (en) * | 2001-07-25 | 2003-02-06 | Sharp Kabushiki Kaisha | Plating method and plating apparatus |
| CN100350078C (en) * | 2004-03-05 | 2007-11-21 | 日本梅克特隆株式会社 | Method for copperizing continuously |
| US10017869B2 (en) | 2008-11-07 | 2018-07-10 | Novellus Systems, Inc. | Electroplating apparatus for tailored uniformity profile |
| US11549192B2 (en) | 2008-11-07 | 2023-01-10 | Novellus Systems, Inc. | Electroplating apparatus for tailored uniformity profile |
| US10920335B2 (en) | 2008-11-07 | 2021-02-16 | Novellus Systems, Inc. | Electroplating apparatus for tailored uniformity profile |
| KR102109207B1 (en) | 2012-11-27 | 2020-05-12 | 램 리써치 코포레이션 | Method and apparatus for dynamic current distribution control during electroplating |
| US9909228B2 (en) | 2012-11-27 | 2018-03-06 | Lam Research Corporation | Method and apparatus for dynamic current distribution control during electroplating |
| JP2014111831A (en) * | 2012-11-27 | 2014-06-19 | Lam Research Corporation | Method and apparatus for dynamic current distribution control during electroplating |
| KR20140067948A (en) * | 2012-11-27 | 2014-06-05 | 램 리써치 코포레이션 | Method and apparatus for dynamic current distribution control during electroplating |
| JP2017137519A (en) * | 2016-02-01 | 2017-08-10 | 株式会社荏原製作所 | Plating device |
| JP6999070B1 (en) * | 2021-03-05 | 2022-02-10 | 株式会社荏原製作所 | How to adjust the plating module |
| CN114787428A (en) * | 2021-03-05 | 2022-07-22 | 株式会社荏原制作所 | Method for adjusting a coating module |
| WO2022185523A1 (en) * | 2021-03-05 | 2022-09-09 | 株式会社荏原製作所 | Method for adjusting plating module |
| KR20220125734A (en) * | 2021-03-05 | 2022-09-14 | 가부시키가이샤 에바라 세이사꾸쇼 | How to adjust the plating module |
| KR102447745B1 (en) * | 2021-03-05 | 2022-09-28 | 가부시키가이샤 에바라 세이사꾸쇼 | How to adjust the plating module |
| CN114787428B (en) * | 2021-03-05 | 2023-04-14 | 株式会社荏原制作所 | Method for adjusting a coating module |
| JP7329268B2 (en) | 2022-01-24 | 2023-08-18 | アスカコーポレーション株式会社 | Jet plating equipment |
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