JP2000183092A - Mounting structure and mounting method for electronic component fitted with bump - Google Patents

Mounting structure and mounting method for electronic component fitted with bump

Info

Publication number
JP2000183092A
JP2000183092A JP35753098A JP35753098A JP2000183092A JP 2000183092 A JP2000183092 A JP 2000183092A JP 35753098 A JP35753098 A JP 35753098A JP 35753098 A JP35753098 A JP 35753098A JP 2000183092 A JP2000183092 A JP 2000183092A
Authority
JP
Japan
Prior art keywords
electronic component
mounting
conductive pattern
bump
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP35753098A
Other languages
Japanese (ja)
Inventor
Hideki Nagafuku
秀喜 永福
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP35753098A priority Critical patent/JP2000183092A/en
Publication of JP2000183092A publication Critical patent/JP2000183092A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a mounting structure and mounting method for an electronic component fitted with bumps which can raise the reliability after mounting. SOLUTION: In a mounting method for an electronic component fitted with bumps which joints the electronic component 5, where bumps 6 are made in a board 1 by an adhesive 4 and making a bump 6 electrically continuous to a conductive pattern 2, the electronic component 5 is mounted on the board 1 by supplying the adhesive 4 onto the abutting section of the board 1 after etching off the surface of the abutting section between the conductive pattern and the bump, thereby thinning it more that other section. Hereby, the dimension of the space between the electronic component 5 and the board 1 is reduced, and the displacement due to the heat of the adhesive is reduced, and nonconformities due to separation is reduced, whereby the reliability after mounting can be improved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、バンプが形成され
た電子部品を基板に実装して成るバンプ付電子部品の実
装構造および実装方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure and a mounting method for an electronic component with bumps, which is formed by mounting an electronic component with bumps formed on a substrate.

【０００２】[0002]

【従来の技術】フリップチップなどのバンプ付電子部品
の実装方法として、接着剤を用いてバンプ付電子部品を
基板に接合する方法が知られている。この方法は基板上
の実装位置に予めエポキシ樹脂などの接着剤を供給して
おき、圧着ツールによってバンプ付電子部品のバンプを
基板に形成された導電パターン表面に押圧しながら加熱
することにより、接着剤を硬化させるものである。これ
により電子部品は基板に固着され、実装後にもバンプが
導電パターン表面に押圧された状態が保たれバンプと導
電パターンとの導通が確保される。2. Description of the Related Art As a mounting method of an electronic component with a bump such as a flip chip, a method of bonding the electronic component with a bump to a substrate using an adhesive is known. In this method, an adhesive such as epoxy resin is supplied in advance to the mounting position on the board, and the bumps of the electronic component with bumps are heated while pressing the bumps on the conductive pattern surface formed on the board with a pressure bonding tool. It cures the agent. As a result, the electronic component is fixed to the substrate, and the state in which the bumps are pressed against the surface of the conductive pattern is maintained even after mounting, so that conduction between the bump and the conductive pattern is ensured.

【０００３】[0003]

【発明が解決しようとする課題】上述の実装方法で用い
られる接着剤は、実装後に温度変化によって膨張・収縮
する。この膨張・収縮による変位は接着剤の厚さが大き
い程、すなわち電子部品と基板との間の隙間が大きい程
大きくなる。この温度変化による変位は接合部の破断な
どの原因となって接合の信頼性を損なうため極力小さく
抑えることが望ましい。このため、実装時の隙間を出来
るだけ小さくする目的で、実装時に電子部品を基板に高
荷重で押圧してバンプの当接部を押し込んで変形させ、
この状態で接着剤を硬化させることが行われていた。し
かしながらこの方法では、基板が押圧荷重によって押し
込まれた部分には実装後も応力が残留して電子部品の剥
離の原因となる場合があり、実装後の信頼性を低下させ
るという問題点があった。The adhesive used in the above mounting method expands and contracts due to a change in temperature after mounting. The displacement due to the expansion and contraction increases as the thickness of the adhesive increases, that is, as the gap between the electronic component and the substrate increases. It is desirable that the displacement due to the temperature change be as small as possible because it causes breakage of the joint and impairs the reliability of the joint. For this reason, in order to make the gap at the time of mounting as small as possible, at the time of mounting, the electronic component is pressed against the board with a high load, and the contact portion of the bump is pressed and deformed.
In this state, the adhesive was cured. However, in this method, there is a case where stress remains in a portion where the substrate is pressed by the pressing load even after mounting, which may cause detachment of the electronic component, and thus has a problem of lowering reliability after mounting. .

【０００４】そこで本発明は、実装後の信頼性を向上さ
せることができるバンプ付電子部品の実装構造および実
装方法を提供することを目的とする。Accordingly, an object of the present invention is to provide a mounting structure and a mounting method for an electronic component with bumps, which can improve the reliability after mounting.

【０００５】[0005]

【課題を解決するための手段】請求項１記載のバンプ付
電子部品の実装構造は、バンプが形成された電子部品を
導電パターンが形成された基板に接着剤により接合して
前記バンプを導電パターンに導通させて成るバンプ付電
子部品の実装構造であって、前記導電パターンの前記バ
ンプとの当接部位の厚みがこの導電パターンの他の部分
よりも薄いようにした。According to a first aspect of the present invention, there is provided a mounting structure of an electronic component with bumps, wherein the electronic component on which the bumps are formed is bonded to a substrate on which the conductive pattern is formed with an adhesive to bond the bumps to the conductive pattern. Wherein the thickness of a portion of the conductive pattern in contact with the bump is smaller than other portions of the conductive pattern.

【０００６】請求項２記載のバンプ付電子部品の実装方
法は、バンプが形成された電子部品を導電パターンが形
成された基板に接着剤により接合して前記バンプを導電
パターンに導通させるバンプ付電子部品の実装方法であ
って、前記導電パターンの前記バンプとの当接部位の表
面を除去してこの導電パターンの他の部位よりも薄くす
る表面除去工程と、前記基板の前記導電パターンの当接
部位上に接着剤を供給する工程と、前記バンプ付電子部
品のバンプを導電パターンに位置合わせして基板に搭載
する工程と、前記接着剤を硬化させる工程とを含む。According to a second aspect of the present invention, there is provided a method of mounting an electronic component with a bump, wherein the electronic component with the bump is bonded to a substrate on which the conductive pattern is formed with an adhesive, and the bump is electrically connected to the conductive pattern. A method of mounting a component, comprising: a surface removing step of removing a surface of a contact portion of the conductive pattern with the bump so as to be thinner than another portion of the conductive pattern; The method includes a step of supplying an adhesive on a portion, a step of positioning the bumps of the electronic component with bumps on a conductive pattern and mounting the same on a substrate, and a step of curing the adhesive.

【０００７】請求項３記載のバンプ付電子部品の実装方
法は、請求項２記載のバンプ付電子部品の実装方法であ
って、前記導電パターン表面は前記当接部位を除いて保
護膜で覆われており、前記表面除去工程においてエッチ
ングにより当接部位の導電パターン表面を除去するよう
にした。According to a third aspect of the present invention, there is provided a method of mounting an electronic component with bumps according to the second aspect, wherein the surface of the conductive pattern is covered with a protective film except for the contact portion. In the surface removing step, the surface of the conductive pattern at the contact portion is removed by etching.

【０００８】請求項４記載のバンプ付電子部品の実装方
法は、請求項２記載のバンプ付電子部品の実装方法であ
って、前記導電パターン表面は前記当接部位を除いて保
護膜で覆われており、前記表面除去工程において前記当
接部位に半田の無電解メッキを行うことにより導電パタ
ーン表面を除去するようにした。According to a fourth aspect of the present invention, there is provided a method of mounting an electronic component with a bump according to the second aspect, wherein the surface of the conductive pattern is covered with a protective film except for the contact portion. In the surface removing step, the surface of the conductive pattern is removed by performing electroless plating of solder on the contact portion.

【０００９】本発明によれば、導電パターンのバンプと
の当接部の厚みを他の部分よりも薄くすることにより、
電子部品と基板との間の実装隙間を小さくして接着剤の
熱による変位を減少させることができる。According to the present invention, the thickness of the contact portion of the conductive pattern with the bump is made smaller than that of the other portions,
The mounting gap between the electronic component and the substrate can be reduced to reduce the displacement of the adhesive due to heat.

【００１０】[0010]

【発明の実施の形態】（実施の形態１）図１（ａ），
（ｂ），（ｃ），（ｄ），（ｅ）は本発明の実施の形態
１のバンプ付電子部品の実装方法の工程説明図である。
図１（ａ）において、基板１上には導電パターン２が形
成されている。導電パターン２は銅などの良導体を材質
としており、厚さｔ１は約５０μｍ程度となっている。
基板１上の電子部品実装部位の所定範囲Ａは基板１表面
が露呈されており、導電パターン２の表面は電子部品の
バンプ当接部位の範囲Ｂを除いて保護膜であるソルダー
レジスト３が形成されている。(Embodiment 1) FIG. 1 (a),
(B), (c), (d), and (e) are process explanatory views of the mounting method of the electronic component with bumps according to the first embodiment of the present invention.
In FIG. 1A, a conductive pattern 2 is formed on a substrate 1. The conductive pattern 2 is made of a good conductor such as copper, and has a thickness t1 of about 50 μm.
A predetermined area A of the electronic component mounting portion on the substrate 1 has the surface of the substrate 1 exposed, and a surface of the conductive pattern 2 is formed with a solder resist 3 as a protective film except for a range B of the electronic component's bump contact area. Have been.

【００１１】次に基板１はエッチング工程に送られる。
このエッチング工程では、ケミカルエッチングにより導
電パターン２の表面が部分的に除去され、図１（ｂ）に
示すようにソルダーレジスト３が存在しない範囲Ｂのバ
ンプとの当接部位のみの導電パターン２の表面が除去さ
れ、導電パターンの他の部分よりも薄い薄電極部２ａが
形成される。このエッチング工程では、導電パターン２
の表面は約３０μｍ程度除去され、薄電極部２ａの厚さ
ｔ２は約２０μｍ程度となる。Next, the substrate 1 is sent to an etching step.
In this etching step, the surface of the conductive pattern 2 is partially removed by chemical etching, and as shown in FIG. The surface is removed, and a thin electrode portion 2a thinner than other portions of the conductive pattern is formed. In this etching step, the conductive pattern 2
Is removed by about 30 μm, and the thickness t2 of the thin electrode portion 2a becomes about 20 μm.

【００１２】次に図１（ｃ）に示すように、薄電極部２
ａを含む電子部品実装部位にエポキシ樹脂などの熱硬化
性樹脂よりなる接着剤４が供給される。次いで図１
（ｄ）に示すように、電子部品５を圧着ツール７により
保持して基板１の実装部位に搭載する。電子部品５には
金属バンプ６が形成されており、搭載に際しては、金属
バンプ６を薄電極部２ａに位置合わせして圧着ツール７
により基板１に対して電子部品５を押圧する。これによ
り、薄電極部２ａは押圧荷重により変形し、金属バンプ
６によって約１０μｍ程度押し込まれる。Next, as shown in FIG.
The adhesive 4 made of a thermosetting resin such as an epoxy resin is supplied to the electronic component mounting site including the component a. Then Figure 1
As shown in (d), the electronic component 5 is held by the crimping tool 7 and mounted on the mounting portion of the substrate 1. A metal bump 6 is formed on the electronic component 5, and when mounting, the metal bump 6 is aligned with the thin electrode portion 2 a and a crimping tool 7 is mounted.
Presses the electronic component 5 against the substrate 1. As a result, the thin electrode portion 2a is deformed by the pressing load and is pushed by the metal bump 6 by about 10 μm.

【００１３】この状態を保ちながら圧着ツール７に備え
られた加熱手段によって電子部品５を加熱することによ
り、接着剤４は熱硬化する。そして熱硬化後には電子部
品５は基板１に固着され、金属バンプ６が薄電極部２ａ
を押圧した状態が保たれて、金属バンプ６と導電パター
ン２との電気的導通が確保される。By heating the electronic component 5 by a heating means provided on the crimping tool 7 while maintaining this state, the adhesive 4 is thermally cured. After the thermosetting, the electronic component 5 is fixed to the substrate 1, and the metal bump 6 is fixed to the thin electrode portion 2a.
Is kept pressed, and electrical continuity between the metal bump 6 and the conductive pattern 2 is ensured.

【００１４】上記説明した実装方法によるバンプ付電子
部品の実装構造において、薄電極部２ａはエッチングに
より約３０μｍ程度薄くなっており、また図１（ｄ）に
示す搭載工程において約１０μｍ程度押し込まれている
ため、通常の実装方法による実装構造と比較して、電子
部品５の下面と基板１との隙間寸法ｈは約４０μｍ程度
低くなっている。一般的な電子部品の実装後の隙間寸法
は数十μｍのオーダーであることから、この４０μｍの
隙間削減は、隙間寸法が大幅に削減され実装後の接着剤
４の厚さが格段に減少することを意味している。したが
って、実装後の接着剤４の熱膨張・収縮時の変位を抑え
て、電子部品５の剥離による不具合を減少させることが
できる。In the mounting structure of the electronic component with bumps according to the mounting method described above, the thin electrode portion 2a is thinned by about 30 μm by etching, and is pressed down by about 10 μm in the mounting step shown in FIG. Therefore, the gap dimension h between the lower surface of the electronic component 5 and the substrate 1 is reduced by about 40 μm as compared with a mounting structure by a normal mounting method. Since the gap size after mounting of a general electronic component is on the order of several tens of μm, the reduction of the gap of 40 μm significantly reduces the gap size and significantly reduces the thickness of the adhesive 4 after mounting. Means that. Therefore, the displacement of the adhesive 4 after mounting during thermal expansion and contraction can be suppressed, and problems caused by peeling of the electronic component 5 can be reduced.

【００１５】（実施の形態２）図２（ａ），（ｂ），
（ｃ）、図３（ａ），（ｂ），（ｃ）は本発明の実施の
形態２のバンプ付電子部品の実装方法の工程説明図であ
る。図２（ａ），（ｂ），（ｃ）、図３（ａ），
（ｂ），（ｃ）は上記実装方法を工程順に示すものであ
る。図２（ａ）は、実施の形態１の図１（ａ）に示すも
のと同様である。この後基板１は無電解メッキによる半
田メッキ工程に送られる。これにより、図２（ｂ）に示
すように導電パターン２のソルダーレジスト３以外の範
囲Ｂのバンプ当接部位には、半田のメッキ膜８が形成さ
れるとともに無電解メッキによるエッチング作用により
範囲Ｂの導電パターン２の表面が除去され、実施の形態
１と同様に薄電極部２ａが形成される。そしてこの後基
板１を半田融点温度以上に加熱することにより、図２
（ｃ）に示すように半田のメッキ膜８が溶融して薄電極
部２ａ上には半田バンプ８ａが形成される。(Embodiment 2) FIGS. 2 (a), (b),
FIGS. 3 (c), 3 (a), 3 (b) and 3 (c) are process explanatory views of a method for mounting an electronic component with bumps according to Embodiment 2 of the present invention. 2 (a), (b), (c), FIG. 3 (a),
(B) and (c) show the mounting method in the order of steps. FIG. 2A is the same as that shown in FIG. 1A of the first embodiment. Thereafter, the substrate 1 is sent to a solder plating process using electroless plating. As a result, as shown in FIG. 2 (b), a solder plating film 8 is formed on the bump abutting portion of the conductive pattern 2 other than the solder resist 3 in the range B, and the range B is formed by the etching action of the electroless plating. The surface of the conductive pattern 2 is removed, and a thin electrode portion 2a is formed as in the first embodiment. Thereafter, the substrate 1 is heated to a temperature equal to or higher than the melting point of the solder, whereby
As shown in (c), the solder plating film 8 is melted, and a solder bump 8a is formed on the thin electrode portion 2a.

【００１６】次に、図３（ａ）に示すように基板１の半
田バンプ８ａを含む実装部位に実施の形態１と同様に接
着剤４が供給される。そして圧着ツール７により実施の
形態１と同様に電子部品５が搭載される。このとき、圧
着ツール７によって電子部品５を基板１に対して押圧す
ることにより、金属バンプ６は軟い半田バンプ８ａに埋
入し、薄電極部２ａの表面に当接した状態で薄電極部２
ａを基板１に対して押し込む。Next, as shown in FIG. 3A, the adhesive 4 is supplied to the mounting portion including the solder bumps 8a of the substrate 1 as in the first embodiment. Then, the electronic component 5 is mounted by the crimping tool 7 as in the first embodiment. At this time, when the electronic component 5 is pressed against the substrate 1 by the crimping tool 7, the metal bumps 6 are embedded in the soft solder bumps 8a, and are brought into contact with the surface of the thin electrode portion 2a. 2
a is pushed into the substrate 1.

【００１７】この後図３（ｃ）に示すように、実施の形
態１と同様の加熱が行われる。これにより、金属バンプ
６が薄電極部２ａに押圧された状態で電子部品５が基板
１に固定され、実装が完了する。このとき、無電解メッ
キ時のエッチング作用による電極厚さの減少、および搭
載時の押し込みにより、実装後の電子部品５と基板１と
の隙間寸法ｈが減少することおよびこれによる効果につ
いては実施の形態１と同様である。Thereafter, as shown in FIG. 3C, the same heating as in the first embodiment is performed. As a result, the electronic component 5 is fixed to the substrate 1 with the metal bump 6 pressed against the thin electrode portion 2a, and the mounting is completed. At this time, the gap dimension h between the electronic component 5 and the substrate 1 after mounting is reduced by the reduction of the electrode thickness due to the etching action at the time of electroless plating and the press-down at the time of mounting. Same as in the first embodiment.

【００１８】[0018]

【発明の効果】本発明によれば、導電パターンのバンプ
との当接部の厚みを他の部分よりも薄くするようにした
ので、実装後の電子部品と基板との間の隙間寸法を小さ
くして、接着剤の熱による変位を減少させ、実装後の剥
離を防止して不具合を減少させることができる。According to the present invention, the thickness of the contact portion between the conductive pattern and the bump is made smaller than that of the other portions, so that the size of the gap between the mounted electronic component and the substrate is reduced. As a result, the displacement of the adhesive due to heat can be reduced, peeling after mounting can be prevented, and defects can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】（ａ）本発明の実施の形態１のバンプ付電子部
品の実装方法の工程説明図 （ｂ）本発明の実施の形態１のバンプ付電子部品の実装
方法の工程説明図 （ｃ）本発明の実施の形態１のバンプ付電子部品の実装
方法の工程説明図 （ｄ）本発明の実施の形態１のバンプ付電子部品の実装
方法の工程説明図 （ｅ）本発明の実施の形態１のバンプ付電子部品の実装
方法の工程説明図FIG. 1A is a process explanatory view of a method for mounting an electronic component with bumps according to a first embodiment of the present invention. FIG. 1B is a process explanatory view of a method for mounting an electronic component with bumps according to a first embodiment of the present invention. (D) Process explanatory diagram of the mounting method of the electronic component with bump according to the first embodiment of the present invention (d) Process explanatory diagram of the mounting method of the electronic component with the bump according to the first embodiment of the present invention (e) Implementation of the present invention Process explanatory view of the mounting method of the electronic component with bumps of mode 1

【図２】（ａ）本発明の実施の形態２のバンプ付電子部
品の実装方法の工程説明図 （ｂ）本発明の実施の形態２のバンプ付電子部品の実装
方法の工程説明図 （ｃ）本発明の実施の形態２のバンプ付電子部品の実装
方法の工程説明図FIG. 2A is a process explanatory view of a method for mounting an electronic component with bumps according to a second embodiment of the present invention. FIG. 2B is a process explanatory view of a method for mounting an electronic component with bumps according to a second embodiment of the present invention. 4) Process explanatory diagram of the mounting method of the electronic component with bumps according to Embodiment 2 of the present invention.

【図３】（ａ）本発明の実施の形態２のバンプ付電子部
品の実装方法の工程説明図 （ｂ）本発明の実施の形態２のバンプ付電子部品の実装
方法の工程説明図 （ｃ）本発明の実施の形態２のバンプ付電子部品の実装
方法の工程説明図FIG. 3A is a process explanatory view of a method for mounting an electronic component with bumps according to a second embodiment of the present invention. FIG. 3B is a process explanatory view of a method for mounting an electronic component with bumps according to a second embodiment of the present invention. 4) Process explanatory diagram of the mounting method of the electronic component with bumps according to Embodiment 2 of the present invention.

【符号の説明】[Explanation of symbols]

１ 基板 ２ 導電パターン ２ａ 薄電極部（当接部位） ３ ソルダーレジスト ４ 接着剤 ５ 電子部品 ６ バンプ DESCRIPTION OF SYMBOLS 1 Substrate 2 Conductive pattern 2a Thin electrode part (contact part) 3 Solder resist 4 Adhesive 5 Electronic component 6 Bump

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】バンプが形成された電子部品を導電パター
ンが形成された基板に接着剤により接合して前記バンプ
を導電パターンに導通させて成るバンプ付電子部品の実
装構造であって、前記導電パターンの前記バンプとの当
接部位の厚みがこの導電パターンの他の部分よりも薄い
ことを特徴とするバンプ付電子部品の実装構造。1. A mounting structure of an electronic component with bumps, wherein an electronic component on which a bump is formed is bonded to a substrate on which a conductive pattern is formed by an adhesive, and the bump is electrically connected to the conductive pattern. A mounting structure for an electronic component with bumps, wherein a thickness of a portion of the pattern in contact with the bump is smaller than other portions of the conductive pattern. 【請求項２】バンプが形成された電子部品を導電パター
ンが形成された基板に接着剤により接合して前記バンプ
を導電パターンに導通させるバンプ付電子部品の実装方
法であって、前記導電パターンの前記バンプとの当接部
位の表面を除去してこの導電パターンの他の部位よりも
薄くする表面除去工程と、前記基板の前記導電パターン
の当接部位上に接着剤を供給する工程と、前記バンプ付
電子部品のバンプを導電パターンに位置合わせして基板
に搭載する工程と、前記接着剤を硬化させる工程とを含
むことを特徴とするバンプ付電子部品の実装方法。2. A method for mounting an electronic component with bumps, wherein the electronic component on which bumps are formed is bonded to a substrate on which a conductive pattern is formed by an adhesive, and the bumps are electrically connected to the conductive pattern. A surface removing step of removing the surface of the contact portion with the bump to make it thinner than the other portion of the conductive pattern, and supplying an adhesive on the contact portion of the conductive pattern of the substrate, A method for mounting an electronic component with a bump, comprising: a step of aligning a bump of the electronic component with a bump with a conductive pattern and mounting the electronic component on a substrate; and a step of curing the adhesive. 【請求項３】前記導電パターン表面は前記当接部位を除
いて保護膜で覆われており、前記表面除去工程において
エッチングにより当接部位の導電パターン表面を除去す
ることを特徴とする請求項２記載のバンプ付電子部品の
実装方法。3. The conductive pattern surface is covered with a protective film except for the contact portion, and the conductive pattern surface at the contact portion is removed by etching in the surface removing step. The mounting method of the electronic component with bump described in the above. 【請求項４】前記導電パターン表面は前記当接部位を除
いて保護膜で覆われており、前記表面除去工程において
前記当接部位に半田の無電解メッキを行うことにより導
電パターン表面を除去することを特徴とする請求項２記
載のバンプ付電子部品の実装方法。4. The surface of the conductive pattern is covered with a protective film except for the contact portion, and the surface of the conductive pattern is removed by performing electroless plating of solder on the contact portion in the surface removing step. 3. The method for mounting an electronic component with bumps according to claim 2, wherein:
JP35753098A 1998-12-16 1998-12-16 Mounting structure and mounting method for electronic component fitted with bump Pending JP2000183092A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP35753098A JP2000183092A (en) 1998-12-16 1998-12-16 Mounting structure and mounting method for electronic component fitted with bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35753098A JP2000183092A (en) 1998-12-16 1998-12-16 Mounting structure and mounting method for electronic component fitted with bump

Publications (1)

Publication Number Publication Date
JP2000183092A true JP2000183092A (en) 2000-06-30

Family

ID=18454606

Family Applications (1)

Application Number Title Priority Date Filing Date
JP35753098A Pending JP2000183092A (en) 1998-12-16 1998-12-16 Mounting structure and mounting method for electronic component fitted with bump

Country Status (1)

Country Link
JP (1) JP2000183092A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021534596A (en) * 2018-08-22 2021-12-09 リキッド ワイヤ インコーポレイテッドLiquid Wire Inc. Structure with deformable conductor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021534596A (en) * 2018-08-22 2021-12-09 リキッド ワイヤ インコーポレイテッドLiquid Wire Inc. Structure with deformable conductor
US11594480B2 (en) 2018-08-22 2023-02-28 Liquid Wire Inc. Structures with deformable conductors
JP7269347B2 (en) 2018-08-22 2023-05-08 リキッド ワイヤ インコーポレイテッド Structures with deformable conductors
US11955420B2 (en) 2018-08-22 2024-04-09 Liquid Wire Inc. Structures with deformable conductors

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