JP2000180569A - Time counting synchronization method and time counting synchronization circuit - Google Patents
Time counting synchronization method and time counting synchronization circuitInfo
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- JP2000180569A JP2000180569A JP35351598A JP35351598A JP2000180569A JP 2000180569 A JP2000180569 A JP 2000180569A JP 35351598 A JP35351598 A JP 35351598A JP 35351598 A JP35351598 A JP 35351598A JP 2000180569 A JP2000180569 A JP 2000180569A
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、刻時同期に関し、
特にデルタシグマ型Ａ／Ｄ変換器等を用いた海底地震計
に好適な刻時同期方法及び刻時同期回路に関する。TECHNICAL FIELD The present invention relates to clock synchronization.
In particular, the present invention relates to a clock synchronization method and a clock synchronization circuit suitable for a seafloor seismometer using a delta-sigma A / D converter or the like.
【０００２】[0002]
【従来の技術】海底地震観測における観測装置の内部時
計としては、１０ミリ秒以下の高い刻時精度が必要であ
り、またＡ／Ｄ変換器として微小な地震波を観測するた
めにダイナミックレンジの広いデルタシグマ型Ａ／Ｄ変
換器が使用されている。2. Description of the Related Art An internal clock of an observation device for ocean bottom seismic observation requires a high clock accuracy of 10 milliseconds or less, and a wide dynamic range for observing minute seismic waves as an A / D converter. A delta-sigma A / D converter is used.
【０００３】一般に、高精度時計には、ＧＰＳ受信機か
ら得られる絶対時刻に同期した１秒パルス（１Ｈｚのパ
ルス）信号が良く使用されており、海底地震計では、こ
のようなＧＰＳ受信機から得られる１秒パルスを用いて
内部時計の校正を定期的に行ったり、設置前に内部時計
を校正し観測データ収集後に時刻の補正を行うことによ
り必要とする刻時精度を得ている。In general, high-precision timepieces often use a one-second pulse (1 Hz pulse) signal synchronized with an absolute time obtained from a GPS receiver, and a submarine seismometer uses such a GPS receiver. The required clock accuracy is obtained by calibrating the internal clock periodically using the obtained one-second pulse, or by calibrating the internal clock before installation and correcting the time after collecting observation data.
【０００４】[0004]
【発明が解決しようとする課題】従来、ＧＰＳ受信機を
利用した観測装置等のような内部時計には、絶対時刻と
内部時計とが同期していないため、絶対時刻と内部時計
との差が時間と共に大きくなり、内部時計の校正や観測
データ収集後の時刻補正作業が必要となるという問題が
ある。Conventionally, in an internal clock such as an observation device using a GPS receiver, since the absolute time and the internal clock are not synchronized, the difference between the absolute time and the internal clock is different. There is a problem that it becomes larger with time, and it is necessary to calibrate the internal clock and correct the time after collecting observation data.
【０００５】また、海底地震計においては使用されるデ
ルタシグマ型Ａ／Ｄ変換器等のように必要とするクロッ
ク信号が数百ｋＨｚから数ＭＨｚときわめて高いが、外
部基準信号には、例えば、ＧＰＳ受信機から得られる１
秒パルス信号を使用し、これに同期をとる必要がある場
合には、ＰＬＬ回路が安定するのに非常に長い時間を要
するから、観測装置の設置後直ちに観測を開始すること
ができないという問題がある。In a submarine seismometer, a required clock signal such as a delta-sigma A / D converter used is extremely high, from several hundred kHz to several MHz. 1 obtained from GPS receiver
When it is necessary to use a second pulse signal and synchronize it, it takes a very long time for the PLL circuit to stabilize, so that the observation cannot be started immediately after the installation of the observation device. is there.
【０００６】（発明の目的）本発明の目的は、きわめて
低い外部基準信号に対して短時間に同期がとれるＰＬＬ
回路を使用した刻時同期方法及び刻時同期回路を提供す
ることにある。(Object of the Invention) An object of the present invention is to provide a PLL capable of synchronizing with a very low external reference signal in a short time.
An object of the present invention is to provide a clock synchronization method and a clock synchronization circuit using a circuit.
【０００７】本発明の他の目的は、ＧＰＳ受信機から得
られるきわめて低い周波数の信号にも短時間で同期をと
ることができ、海底地震計等に適用して正確な観測時刻
を得ることが可能な刻時同期方法及び刻時同期回路を提
供することにある。Another object of the present invention is to be able to synchronize a very low frequency signal obtained from a GPS receiver in a short time, and to obtain an accurate observation time by applying to a seafloor seismometer or the like. It is an object of the present invention to provide a possible clock synchronization method and a clock synchronization circuit.
【０００８】[0008]
【課題を解決するための手段】本発明の刻時同期方法
は、外部基準信号と電圧制御発振器の出力を分周する分
周回路の出力信号との位相差により前記電圧制御発振器
を制御するようにしたＰＬＬ回路によりクロック信号を
出力する刻時同期方法において、前記外部基準信号（図
１、高精度時計１）と前記分周回路（図１、分周器２
４、分周器２５、セレクタ２０４、分周器２６）の出力
信号との時間差を検出し、前記時間差が一定時間を越え
たときに、前記分周回路の分周率を所定期間大きくする
ように制御することを特徴とする。また、前記外部基準
信号はＧＰＳ受信機により得られる低周波数の刻時信号
であり、前記分周率の制御により短時間に前記低周波数
の刻時信号に同期することを特徴とする海底地震計のク
ロック信号を生成する刻時同期方法。According to a clock synchronization method of the present invention, the voltage controlled oscillator is controlled by a phase difference between an external reference signal and an output signal of a frequency dividing circuit for dividing the output of the voltage controlled oscillator. In the clock synchronization method of outputting a clock signal by a PLL circuit, the external reference signal (FIG. 1, high-precision clock 1) and the frequency dividing circuit (FIG. 1, frequency divider 2)
4, a frequency difference from the output signal of the frequency divider 25, the selector 204, and the frequency divider 26) is detected, and when the time difference exceeds a predetermined time, the frequency division ratio of the frequency dividing circuit is increased for a predetermined period. Is controlled. In addition, the external reference signal is a low-frequency clock signal obtained by a GPS receiver, and is synchronized with the low-frequency clock signal in a short time by controlling the frequency division ratio. Clock synchronization method for generating a clock signal.
【０００９】本発明の刻時同期回路は、電圧制御発振器
（図１、電圧制御形水晶発振器２３）の出力を分周する
分周率が可変の分周回路（分周器２４、分周器２５、セ
レクタ２０４、分周器２６）と、外部基準信号でトリガ
され第１のパルス幅の信号を出力する第１のパルス発生
器（図１、単パルス発振器２０２）と、前記分周回路の
出力信号でトリガされ第２のパルス幅の信号を出力する
第２のパルス発生器（単パルス発振器２０１）と、前記
第１のパルス幅の信号による前記第２のパルス幅の信号
の禁止信号を出力し前記分周回路の分周率を制御する論
理回路（図１、ＡＮＤ回路２０３）とを有することを特
徴とする。前記分周回路は、分周率の大きい第１の分周
出力と前記分周率より小さい第２の分周出力とを出力す
る第１の分周回路と、前記第１及び第２の分周出力を切
り替えて出力するセレクタと、前記セレクタの出力を分
周する第２の分周回路とを有することを特徴とする。外
部基準信号は、ＧＰＳ受信機により得られる１Ｈｚのパ
ルス信号であり、また、海底地震計の刻時同期回路とし
て使用されることを特徴とする。The clock synchronization circuit according to the present invention comprises a frequency dividing circuit (frequency divider 24, frequency divider) having a variable frequency dividing ratio for dividing the output of a voltage controlled oscillator (FIG. 1, voltage controlled crystal oscillator 23). 25, a selector 204, a frequency divider 26), a first pulse generator (FIG. 1, single pulse oscillator 202) which is triggered by an external reference signal and outputs a signal of a first pulse width, and A second pulse generator (single-pulse oscillator 201) which is triggered by an output signal and outputs a signal of a second pulse width, and a prohibition signal of the signal of the second pulse width by the signal of the first pulse width. A logic circuit (FIG. 1, AND circuit 203) for outputting and controlling the frequency division ratio of the frequency dividing circuit. The frequency dividing circuit includes a first frequency dividing circuit that outputs a first frequency divided output having a large frequency dividing ratio and a second frequency divided output smaller than the frequency dividing ratio, and the first and second frequency dividing circuits. A selector for switching and outputting a frequency output and a second frequency dividing circuit for dividing the output of the selector are provided. The external reference signal is a pulse signal of 1 Hz obtained by a GPS receiver, and is used as a clock synchronization circuit of an ocean bottom seismometer.
【００１０】（作用）外部基準信号と分周回路の出力信
号との時間差が一定時間を越えたときに、分周回路の分
周率を所定期間大きくするように制御することにより、
外部基準信号と分周回路の出力信号との位相差を高速に
縮小する。外部基準信号がきわめて低い周波数の信号で
あっても短時間に同期がとれるので、例えば、海底地震
計のデルタシグマ型Ａ／Ｄ変換器等に必要なきわめて高
いクロック信号を、ＧＰＳ受信機から得られる１Ｈｚの
パルス信号から短時間に生成することが可能となり、刻
時精度の高い海底地震観測を可能となる。(Operation) When the time difference between the external reference signal and the output signal of the frequency dividing circuit exceeds a predetermined time, the frequency dividing ratio of the frequency dividing circuit is controlled so as to be increased for a predetermined period.
The phase difference between the external reference signal and the output signal of the frequency divider is reduced at high speed. Even if the external reference signal is of a very low frequency, synchronization can be achieved in a short time. For example, a very high clock signal required for a delta-sigma A / D converter of a seafloor seismometer can be obtained from a GPS receiver. It is possible to generate a pulse signal of 1 Hz in a short time, and it is possible to perform ocean bottom earthquake observation with high clock accuracy.
【００１１】[0011]
【発明の実施の形態】（構成の説明）次に、本発明の海
底地震計の刻時同期法の一実施の形態について図面を参
照して詳細に説明する。図１は、本発明の実施の形態の
ブロックを示す図である。本実施の形態は、ＰＬＬ回路
２およびデルタシグマ型Ａ／Ｄ変換器３を有する海底地
震計と、例えばＧＰＳ受信機を有する高精度時計１とか
ら構成される。高精度時計１から得られる低い周波数の
出力信号、例えばＧＰＳ受信機から得られる絶対時刻に
同期した１秒パルスをＰＬＬ回路２に入力し、ＰＬＬ回
路２の分周率を制御することにより短時間に同期をと
り、高精度時計１の出力信号に同期した数百ｋＨｚから
数ＭＨｚの周波数のクロック信号をデルタシグマ型Ａ／
Ｄ変換器３に入力することにより高い刻時精度を得る。DESCRIPTION OF THE PREFERRED EMBODIMENTS (Description of Configuration) Next, an embodiment of the clock synchronization method for a seafloor seismometer according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing blocks according to an embodiment of the present invention. This embodiment includes a submarine seismometer having a PLL circuit 2 and a delta-sigma A / D converter 3, and a high-precision clock 1 having, for example, a GPS receiver. By inputting a low-frequency output signal obtained from the high-precision timepiece 1, for example, a one-second pulse synchronized with an absolute time obtained from a GPS receiver to the PLL circuit 2, and controlling the frequency division ratio of the PLL circuit 2, a short time is obtained. And a clock signal having a frequency of several hundred kHz to several MHz synchronized with the output signal of the high-precision timepiece 1 is converted into a delta-sigma A /
High clock accuracy is obtained by inputting to the D converter 3.
【００１２】本実施の形態のＰＬＬ回路２の基本ブロッ
クは、分周率制御器２０、位相比較器２１、ローパスフ
ィルタ２２、電圧制御形水晶発振器２３、および１個以
上の分周器２４，２５，２６から構成される。また、分
周率制御器２０は、単パルス発振器２０１，２０２、Ａ
ＮＤ回路２０３およびセレクタ２０４から構成される。The basic blocks of the PLL circuit 2 of the present embodiment include a frequency division ratio controller 20, a phase comparator 21, a low-pass filter 22, a voltage-controlled crystal oscillator 23, and one or more frequency dividers 24 and 25. , 26. Further, the frequency division ratio controller 20 includes single pulse oscillators 201 and 202, A
It comprises an ND circuit 203 and a selector 204.
【００１３】電圧制御形水晶発振器２３の出力を分周器
２４，２５、セレクタ２０４及び分周器２６により分周
した信号と、高精度時計１からの出力信号と位相比較器
２１に入力し、前記２信号の位相差に応じた信号をロー
パスフィルタ２２に入力し、該ローパスフィルタ２２の
出力により電圧制御形水晶発振器２３に入力し、前記２
信号が位相差を０に近づくように負帰還制御を行う。A signal obtained by dividing the output of the voltage controlled crystal oscillator 23 by frequency dividers 24 and 25, a selector 204 and a frequency divider 26, an output signal from the high-precision timepiece 1 and a phase comparator 21 are inputted. A signal corresponding to the phase difference between the two signals is input to a low-pass filter 22, and the output of the low-pass filter 22 is input to a voltage-controlled crystal oscillator 23,
Negative feedback control is performed so that the phase difference of the signal approaches zero.
【００１４】分周率制御器２０は、分周器２５から出力
される分周率の異なる２つの周波数ｆ１，ｆ２（ｆ２＞
ｆ１）の信号をセレクタ２０４において選択的に出力す
る。単パルス発振器２０１は、分周器２６の出力パルス
をトリガーとし、一定幅のパルスを出力する。単パルス
発振器２０２は、高精度時計１からの出力信号をトリガ
ーとし、反転した一定幅のパルスを出力する。単パルス
発振器２０１と単パルス発振器２０２の出力をＡＮＤ回
路２０３に入力し、ＡＮＤ回路２０３から出力されるセ
レクト信号をセレクタ２０４に入力することにより、セ
レクタ２０４は、分周器２５から入力される２つの信号
のいずれか１方を選択し出力する。セレクタ２０４は、
ＰＬＬ回路の同期がとれている場合は常に周波数ｆ１の
信号が選択出力され、同期がとれていない場合は周波数
ｆ２の信号が選択出力される。The frequency division ratio controller 20 outputs two frequencies f1 and f2 (f2>) having different frequency division ratios output from the frequency divider 25.
The signal of f1) is selectively output by the selector 204. The single-pulse oscillator 201 outputs a pulse having a constant width by using an output pulse of the frequency divider 26 as a trigger. The single-pulse oscillator 202 outputs an inverted constant-width pulse by using an output signal from the high-precision timepiece 1 as a trigger. By inputting the outputs of the single-pulse oscillator 201 and the single-pulse oscillator 202 to the AND circuit 203 and inputting the select signal output from the AND circuit 203 to the selector 204, the selector 204 One of the two signals is selected and output. The selector 204 is
When the PLL circuit is synchronized, the signal of the frequency f1 is always selected and output. When the PLL circuit is not synchronized, the signal of the frequency f2 is selectively output.
【００１５】つまり、高精度時計１の出力信号と分周器
２６の出力信号の位相差が大きい場合は、セレクタ２０
４の出力には通常より高い周波数ｆ２の信号が出力さ
れ、ＰＬＬ回路２の追従速度を速め、位相差が小さくな
るとセレクタ２０４の出力は周波数ｆ１の信号に固定さ
れ、ＰＬＬ回路２が同期状態となる。That is, when the phase difference between the output signal of the high-precision timepiece 1 and the output signal of the frequency divider 26 is large, the selector 20
4 outputs a signal having a frequency f2 higher than usual, increases the following speed of the PLL circuit 2, and when the phase difference becomes small, the output of the selector 204 is fixed to the signal of the frequency f1. Become.
【００１６】このように、ＰＬＬ回路２の分周率制御器
２０により分周率の異なる２つの周波数を選択して制御
することにより、同期に必要な時間を短縮することがで
き、高精度時計１と同期した高い刻時精度を得る。As described above, by selecting and controlling two frequencies having different division ratios by the division ratio controller 20 of the PLL circuit 2, the time required for synchronization can be reduced, and a high-precision clock can be obtained. High clock accuracy synchronized with 1.
【００１７】（動作の説明）次に、本実施の形態の刻時
同期法について、図２のタイムチャートを参照して説明
する。高精度時計１の出力（１）は海底地震計内に設け
られたＰＬＬ回路２の位相比較器２１および単パルス発
振器２０２に入力される。位相比較器２１は、高精度時
計１の出力（１）と分周器２６の出力（２）との位相を
比較し、位相差に応じた信号を出力する。位相比較器２
１の出力はローパスフィルタ２２を通して電圧制御形水
晶発振器２３に入力される。電圧制御形水晶発振器２３
は、入力された信号に応じて発信周波数が制御される。
電圧制御形水晶発振器２３から出力された信号は分周器
２４に入力され、分周器２４により分周された信号はデ
ルタシグマ型Ａ／Ｄ変換器３にクロック信号として入力
される。また、分周器２４により分周された信号は分周
器２５により分周され、分周率の異なる２つの周波数ｆ
１，ｆ２（ｆ２＞ｆ１）の信号がセレクタ２０４に出力
される。セレクタ２０４からは、ＡＮＤ回路２０３の出
力信号（５）がハイレベル（Ｈ）か、又はローレベル
（Ｌ）かに応じてそれぞれ周波数ｆ２の信号又は周波数
ｆ１の信号が選択して出力される。(Explanation of Operation) Next, the clock synchronization method of the present embodiment will be described with reference to the time chart of FIG. The output (1) of the high-precision timepiece 1 is input to the phase comparator 21 and the single-pulse oscillator 202 of the PLL circuit 2 provided in the ocean bottom seismometer. The phase comparator 21 compares the phase of the output (1) of the high-precision timepiece 1 with the phase of the output (2) of the frequency divider 26, and outputs a signal corresponding to the phase difference. Phase comparator 2
The output of 1 is input to the voltage-controlled crystal oscillator 23 through the low-pass filter 22. Voltage controlled crystal oscillator 23
The transmission frequency is controlled according to the input signal.
The signal output from the voltage controlled crystal oscillator 23 is input to a frequency divider 24, and the signal divided by the frequency divider 24 is input to the delta-sigma A / D converter 3 as a clock signal. The signal divided by the frequency divider 24 is frequency-divided by the frequency divider 25, and the two frequencies f having different division rates are used.
Signals of 1, f2 (f2> f1) are output to the selector 204. The selector 204 selects and outputs the signal of the frequency f2 or the signal of the frequency f1 depending on whether the output signal (5) of the AND circuit 203 is high level (H) or low level (L).
【００１８】単パルス発振器２０１は、分周器２６の出
力信号（２）の前縁をトリガーとし、数十ミリ秒程度の
幅（ハイレベル）をもつパルス信号（３）を出力する。
単パルス発振器２０２は、高精度時計１の出力信号
（１）の前縁をトリガーとし、数百ミリ秒の幅（ローレ
ベル）をもつ反転したパルス信号（４）を出力する。単
パルス発振器２０１，２０２の出力をＡＮＤ回路２０３
に入力し、ＡＮＤ回路２０３より出力するセレクト信号
（５）をセレクタ２０４に出力し、セレクタ２０４はＰ
ＬＬ回路２の分周率を制御する。The single-pulse oscillator 201 outputs a pulse signal (3) having a width (high level) of about several tens of milliseconds by using the leading edge of the output signal (2) of the frequency divider 26 as a trigger.
The single-pulse oscillator 202 outputs an inverted pulse signal (4) having a width (low level) of several hundred milliseconds by using a leading edge of the output signal (1) of the high-precision timepiece 1 as a trigger. The outputs of the single pulse oscillators 201 and 202 are connected to an AND circuit 203
And outputs a select signal (5) output from the AND circuit 203 to the selector 204.
The frequency division ratio of the LL circuit 2 is controlled.
【００１９】図２（ａ）は、高精度時計１の出力（１）
と分周器２６の出力信号（２）の位相差が大きい場合の
ＰＬＬ回路の動作を示す図である。同図（ａ）に示すよ
うに、高精度時計１の出力（１）と分周器２６の出力
（２）の位相差が大きい場合、セレクタ２０４に入力さ
れるＡＮＤ回路２０３からのセレクト信号（５）は、単
パルス発振器２０１の出力（３）のパルス幅の期間ハイ
レベル（Ｈ）となり、セレクタ２０４はその期間だけ周
波数ｆ２の信号（６）を出力する。周波数ｆ２は周波数
ｆ１より大きいので分周器２６の出力位相が進みＰＬＬ
回路２の高精度時計１の出力への追従速度を速める。FIG. 2A shows the output (1) of the high-precision timepiece 1.
FIG. 10 is a diagram illustrating an operation of the PLL circuit when the phase difference between the output signal of the frequency divider and the frequency divider is large. As shown in FIG. 3A, when the phase difference between the output (1) of the high-precision timepiece 1 and the output (2) of the frequency divider 26 is large, the select signal (input from the AND circuit 203 to the selector 204) is input. 5) is at the high level (H) during the pulse width of the output (3) of the single pulse oscillator 201, and the selector 204 outputs the signal (6) of the frequency f2 only during that period. Since the frequency f2 is higher than the frequency f1, the output phase of the frequency divider 26 advances and the PLL
The speed at which the circuit 2 follows the output of the high-precision timepiece 1 is increased.
【００２０】図２（ｂ）は、高精度時計１の出力（１）
と分周器２６の出力信号（２）の位相差が小さい場合の
ＰＬＬ回路の動作を示す図である。同図（ｂ）に示すよ
うに、高精度時計１の出力（１）と分周器２６の出力
（２）の位相差が小さくなり、単パルス発振器２０１の
出力パルス（３）が単パルス発振器２０２の出力パルス
（４）のパルス幅内に入ると、ＡＮＤ回路２０３からの
出力は常にローレベル（Ｌ）となり、セレクタ２０４の
出力は周波数ｆ１に固定され、ＰＬＬ回路２は高精度時
計１の出力に位相同期する動作が行われる。FIG. 2B shows the output (1) of the high-precision timepiece 1.
FIG. 9 is a diagram illustrating an operation of the PLL circuit when the phase difference between the output signal of the frequency divider and the frequency divider is small. As shown in FIG. 2B, the phase difference between the output (1) of the high-precision timepiece 1 and the output (2) of the frequency divider 26 becomes small, and the output pulse (3) of the single-pulse oscillator 201 becomes a single-pulse oscillator. When the pulse width of the output pulse (4) of the output 202 is within the pulse width, the output from the AND circuit 203 is always at the low level (L), the output of the selector 204 is fixed to the frequency f1, and the PLL circuit 2 An operation for phase synchronization with the output is performed.
【００２１】このようにして、高精度時計１の出力と分
周器２６の出力の位相差に応じてＰＬＬ回路２の分周率
を制御し、位相差がある一定の差以内に小さくなるまで
ＰＬＬ回路の追従速度を速め、同期に必要な時間を短縮
し同期をとる。In this manner, the frequency division ratio of the PLL circuit 2 is controlled in accordance with the phase difference between the output of the high-precision timepiece 1 and the output of the frequency divider 26 until the phase difference becomes smaller within a certain difference. The tracking speed of the PLL circuit is increased, and the time required for synchronization is reduced to achieve synchronization.
【００２２】本実施の形態では、単パルス発振器２０１
の出力パルス幅は、大きいほど高精度時計の出力と分周
器２６の出力の位相差の縮小速度を速める効果があり、
また、単パルス発振器２０２の出力パルス幅は、狭いほ
ど前記位相誤差の縮小幅を小さくする効果がある。In this embodiment, the single-pulse oscillator 201
Has an effect of increasing the reduction speed of the phase difference between the output of the high-precision clock and the output of the frequency divider 26 as the output pulse width becomes larger.
Further, the narrower the output pulse width of the single pulse oscillator 202 is, the smaller the effect of reducing the phase error is.
【００２３】以上説明した実施の形態においては、外部
基準信号としての高精度時計の出力と分周回路の出力と
の位相差が大きい状態の検出とその時の小さい分周率へ
の制御に、高精度時計と分周回路の出力からそれぞれ所
定パルス幅のパルス信号を出力し論理操作により前記分
周率の制御信号を生成しているが、前記位相差が一定値
以上に達したか否かは両出力の期間に動作するカウンタ
等により計測でき、一定値以上の位相差の生じた時点で
分周率を制御する所定幅の制御信号を出力することによ
っても本発明は実現可能であり制御信号の発生方法は適
宜変更することができる。In the embodiment described above, the detection of the state where the phase difference between the output of the high-precision timepiece as the external reference signal and the output of the frequency dividing circuit is large and the control to the small frequency dividing ratio at that time are performed with high precision. A pulse signal having a predetermined pulse width is output from the output of the precision clock and the frequency divider circuit, and the control signal of the frequency division ratio is generated by a logical operation, but whether or not the phase difference has reached a certain value or more is determined. The present invention can also be realized by outputting a control signal having a predetermined width for controlling the frequency division ratio when a phase difference equal to or more than a certain value can be measured by a counter or the like that operates during the period of both outputs. Can be changed as appropriate.
【００２４】[0024]
【発明の効果】本発明の刻時同期によれば、高精度時計
等の外部基準信号に高速に同期させるための分周率を制
御する回路をＰＬＬ回路に付加しているので、低周波の
外部基準信号に対しても同期速度を短縮することがで
き、高精度な刻時信号を生成することが可能である。According to the clock synchronization of the present invention, since a circuit for controlling the frequency division ratio for synchronizing at high speed to an external reference signal such as a high-precision clock is added to the PLL circuit, The synchronization speed can be reduced even for an external reference signal, and a highly accurate clock signal can be generated.
【００２５】また、本発明の刻時同期によれば、ＧＰＳ
システム等からの基準信号に同期させる海底地震計の内
部時計として利用することにより、地震計の設置直後か
ら計測可能であり内部時計の校正や観測データ収集後の
時刻補正等が必要でない海底地震計を実現することが可
能である。つまり、デルタシグマ型Ａ／Ｄ変換器に出力
するクロック信号のように、数百ｋＨｚから数ＭＨｚと
高い周波数の信号を生成する必要があり、一方で、例え
ば、ＧＰＳ受信機から得られる１Ｈｚのパルス信号に同
期をとる必要があるような場合においても、ＰＬＬ回路
が安定するのに長い時間を要することがなくなり、観測
装置の設置後直ちに観測を開始することが可能である。According to the clock synchronization of the present invention, the GPS
By using it as an internal clock of a seafloor seismometer synchronized with a reference signal from a system, etc., it can be measured immediately after the seismometer is installed, and there is no need to calibrate the internal clock or correct the time after collecting observation data. Can be realized. That is, it is necessary to generate a signal of a high frequency of several hundred kHz to several MHz like a clock signal output to a delta-sigma A / D converter, while, for example, a 1 Hz signal obtained from a GPS receiver is required. Even in the case where it is necessary to synchronize with the pulse signal, it is not necessary to take a long time for the PLL circuit to stabilize, and the observation can be started immediately after the installation of the observation device.
【図１】本発明の一実施の形態を示す構成例を示す図で
ある。FIG. 1 is a diagram showing a configuration example showing an embodiment of the present invention.
【図２】本発明の一実施の形態の動作を示すタイムチャ
ート図である。FIG. 2 is a time chart showing the operation of the embodiment of the present invention.
１ 高精度時計 ２ ＰＬＬ回路 ３ デルタシグマ型Ａ／Ｄ変換器 ２０ 分周率制御器 ２１ 位相比較器 ２２ ローパスフィルタ（ＬＰＦ） ２３ 電圧制御形水晶発振器（ＶＣＸＯ） ２４、２５、２６ 分周器 ２０１、２０２ 単パルス発振器 ２０３ ＡＮＤ回路 ２０４ セレクタ DESCRIPTION OF SYMBOLS 1 High precision clock 2 PLL circuit 3 Delta-sigma type A / D converter 20 Division ratio controller 21 Phase comparator 22 Low-pass filter (LPF) 23 Voltage control type crystal oscillator (VCXO) 24, 25, 26 Divider 201 , 202 Single pulse oscillator 203 AND circuit 204 Selector
Claims (6)
分周する分周回路の出力信号との位相差により前記電圧
制御発振器を制御するようにしたＰＬＬ回路によりクロ
ック信号を出力する刻時同期方法において、 前記外部基準信号と前記分周回路の出力信号との時間差
を検出し、前記時間差が一定時間を越えたときに、前記
分周回路の分周率を所定期間大きくするように制御する
ことを特徴とする刻時同期方法。1. A clock circuit for outputting a clock signal by a PLL circuit which controls the voltage controlled oscillator based on a phase difference between an external reference signal and an output signal of a frequency dividing circuit for dividing the output of the voltage controlled oscillator. In the method, a time difference between the external reference signal and an output signal of the frequency dividing circuit is detected, and when the time difference exceeds a predetermined time, control is performed so as to increase a frequency dividing ratio of the frequency dividing circuit for a predetermined period. A clock synchronization method, characterized in that:
時同期方法であって、前記外部基準信号はＧＰＳ受信機
により得られる低周波数の刻時信号であり、前記分周率
の制御により短時間に前記低周波数の刻時信号に同期す
ることを特徴とする請求項１記載の刻時同期方法。2. A clock synchronization method for generating a clock signal of an ocean bottom seismometer, wherein the external reference signal is a low-frequency clock signal obtained by a GPS receiver, and is controlled by controlling the frequency division ratio. 2. The clock synchronization method according to claim 1, wherein the clock is synchronized with the low-frequency clock signal in time.
が可変の分周回路と、外部基準信号でトリガされ第１の
パルス幅の信号を出力する第１のパルス発生器と、前記
分周回路の出力信号でトリガされ第２のパルス幅の信号
を出力する第２のパルス発生器と、前記第１のパルス幅
の信号による前記第２のパルス幅の信号の禁止信号を出
力し前記分周回路の分周率を制御する論理回路とを有す
ることを特徴とする刻時同期回路。3. A frequency dividing circuit for dividing the output of the voltage controlled oscillator, the frequency dividing ratio being variable, a first pulse generator triggered by an external reference signal and outputting a signal having a first pulse width, A second pulse generator which is triggered by an output signal of the frequency dividing circuit and outputs a signal of a second pulse width; and outputs a prohibition signal of the signal of the second pulse width by the signal of the first pulse width. A logic circuit for controlling a frequency division ratio of the frequency dividing circuit.
分周出力と前記分周率より小さい第２の分周出力とを出
力する第１の分周回路と、前記第１及び第２の分周出力
を切り替えて出力するセレクタと、前記セレクタの出力
を分周する第２の分周回路とを有することを特徴とする
請求項３記載の刻時同期回路。4. The frequency dividing circuit outputs a first frequency divided output having a large frequency dividing ratio and a second frequency divided output smaller than the frequency dividing ratio; 4. The clock synchronization circuit according to claim 3, further comprising: a selector for switching and outputting a second frequency-divided output; and a second frequency divider for frequency-dividing the output of the selector.
られる１Ｈｚのパルス信号であることを特徴とする請求
項３又は４記載の刻時同期回路。5. The clock synchronization circuit according to claim 3, wherein the external reference signal is a 1 Hz pulse signal obtained by a GPS receiver.
れることを特徴とする請求項５記載の刻時同期回路。6. The clock synchronization circuit according to claim 5, wherein the clock synchronization circuit is used as a clock synchronization circuit of an ocean bottom seismometer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35351598A JP3246459B2 (en) | 1998-12-11 | 1998-12-11 | Clock synchronization method and clock synchronization circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35351598A JP3246459B2 (en) | 1998-12-11 | 1998-12-11 | Clock synchronization method and clock synchronization circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000180569A true JP2000180569A (en) | 2000-06-30 |
| JP3246459B2 JP3246459B2 (en) | 2002-01-15 |
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|---|---|---|---|
| JP35351598A Expired - Fee Related JP3246459B2 (en) | 1998-12-11 | 1998-12-11 | Clock synchronization method and clock synchronization circuit |
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|---|---|---|---|---|
| CN110908272A (en) * | 2019-12-20 | 2020-03-24 | 昆明理工大学 | 1pps pulse signal timing method |
| CN110908272B (en) * | 2019-12-20 | 2021-04-13 | 昆明理工大学 | 1pps pulse signal timing method |
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| Publication number | Publication date |
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