JP2000124396A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2000124396A
JP2000124396A JP31395998A JP31395998A JP2000124396A JP 2000124396 A JP2000124396 A JP 2000124396A JP 31395998 A JP31395998 A JP 31395998A JP 31395998 A JP31395998 A JP 31395998A JP 2000124396 A JP2000124396 A JP 2000124396A
Authority
JP
Japan
Prior art keywords
pad
semiconductor device
thickness
semiconductor chip
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31395998A
Other languages
Japanese (ja)
Inventor
Kanta Nokita
寛太 野北
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP31395998A priority Critical patent/JP2000124396A/en
Publication of JP2000124396A publication Critical patent/JP2000124396A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which semiconductor chips are mounted on both faces, which can be provided with high integration and multifuctionality, which can be made thin and whose damage-resistant property and mounting property are good. SOLUTION: Semiconductor chips 5 are mounted on a pad 1 whose thickness is made thin from both face sides in such a way that they creep into thin places. The semiconductor chips 5 and leads 2 which are installed around the pad 1 are connected by metal wires 7, Lead parts which includes connected places of the metal wires 7, the pad 1 and the semiconductor chips 5 are sealed with a resin 8. Thereby, this semiconductor device is constituted. In addition, depths which are formed by making the thickness of the pad 1 thin are made equal to or more than the semiconductor chips 5. Rear surfaces of the leads 2 which are derived from parts which are sealed with the resin 8 are situated to be equal to the resin-sealed rear surface or to be a little lower.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体チップをパッ
ドの両面に設けた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor chip provided on both sides of a pad.

【０００２】[0002]

【従来の技術】電子機器例えば携帯電話、電子手帳等が
軽薄短小化されてきている。これに伴ってこれら電子機
器に組み込まれる半導体装置は一層薄くすることを要請
されている。2. Description of the Related Art Electronic devices such as mobile phones and electronic organizers have been reduced in size and size. Accordingly, semiconductor devices incorporated in these electronic devices have been required to be thinner.

【０００３】また、半導体装置は多機能、多ピン、高集
積および高密度実装性が望まれ、パッドの両面に半導体
チップを搭載したものが提案されている。両面に半導体
チップを設けることで高集積化や、さらには機能の異な
る半導体チップを両面に搭載して多機能化が図れる等の
効果がある。Further, a semiconductor device is desired to have a multi-function, multi-pin, high-integration and high-density mounting properties, and a device having semiconductor chips mounted on both sides of a pad has been proposed. Providing semiconductor chips on both sides has the effect of increasing the degree of integration and achieving multifunctionality by mounting semiconductor chips having different functions on both sides.

【０００４】[0004]

【この発明が解決しようとする課題】しかし、従来の半
導体チップを両面に設けた半導体装置は前述のような効
果があるけれども薄手化に限度があり、例えば薄くても
パッケージ厚みが１ｍｍ以上あり要望とする薄さに出来
ず、薄くて、且つ、高集積、多機能の半導体装置に対す
るニ−ズに十分に対応できていない実状にある。However, the conventional semiconductor device provided with a semiconductor chip on both sides has the above-mentioned effect, but has a limitation in thinning. For example, even if it is thin, the package thickness is 1 mm or more. In reality, it is not possible to sufficiently meet the needs for thin, highly integrated, multifunctional semiconductor devices.

【０００５】半導体装置をより薄物とするには搭載する
半導体チップも薄いものを使用するのが有利となり、例
えば数十μｍと極薄の半導体チップが用いられる。かか
る極薄の半導体チップは半導体装置を製造する工程での
取扱いが難しく、薄手化した半導体装置を生産性よく得
ることが困難である。In order to make the semiconductor device thinner, it is advantageous to use a thin semiconductor chip, for example, an extremely thin semiconductor chip of several tens μm is used. Such an extremely thin semiconductor chip is difficult to handle in a process of manufacturing a semiconductor device, and it is difficult to obtain a thin semiconductor device with high productivity.

【０００６】また、半導体装置は外形が薄くとも予期せ
ぬ衝撃や外力等を受けても損傷しない耐損傷性を望まれ
るが、この点についても一層高める必要がある。[0006] In addition, although the semiconductor device is desired to have damage resistance which is not damaged by unexpected impact or external force even when the semiconductor device is thin, it is necessary to further enhance this point.

【０００７】本発明は半導体チップを両面に搭載し高集
積、多機能性を備えさせることが出来るとともに、薄手
化例えば０．５ｍｍ以下の薄い半導体装置でも生産性よ
く得られ、また耐損傷性、実装性もすぐれた半導体装置
を得ることを目的とする。According to the present invention, a semiconductor chip can be mounted on both sides to provide high integration and multi-functionality, and a thin semiconductor device, for example, a thin semiconductor device having a thickness of 0.5 mm or less can be obtained with high productivity. It is an object to obtain a semiconductor device having excellent mountability.

【０００８】[0008]

【課題を解決するための手段】本発明の要旨は、両面側
から厚みを薄くしたパッドに、半導体チップが前記薄く
した箇所に入り込んで搭載され、該半導体チップの端子
と前記パッドの周りに設けたリ−ドを金属線を介して電
気的に接続し、前記金属線の接続箇所を含むリ−ド部、
パッドおよび半導体チップを樹脂封止した半導体装置に
ある。他の要旨は、前記パッドの厚みを薄くした深さが
半導体チップの厚み以上あるいは同等で、該薄くした部
分に半導体チップが入り込んで搭載されている半導体装
置にある。また、他の要旨は、前記樹脂封止から出てい
る前記リ−ドの下面が樹脂封止下面と同等あるいは当該
リ−ドの厚み分以内前記樹脂封止の下面から下側に位置
している半導体装置にある。SUMMARY OF THE INVENTION The gist of the present invention is that a semiconductor chip is mounted on a pad whose thickness is reduced from both sides by penetrating the thinned portion, and is provided around terminals of the semiconductor chip and the pad. A lead portion electrically connected to the lead via a metal wire, and a lead portion including a connection portion of the metal wire;
A semiconductor device in which a pad and a semiconductor chip are resin-sealed. Another gist is a semiconductor device in which the thickness of the pad is reduced to be equal to or greater than the thickness of the semiconductor chip, and the semiconductor chip is mounted with the semiconductor chip inserted into the reduced portion. Further, another point is that the lower surface of the lead coming out of the resin sealing is positioned lower than the lower surface of the resin sealing as being equal to or less than the thickness of the lead. Semiconductor device.

【０００９】[0009]

【発明の実施の形態】本発明の１実施例について図面を
参照して説明する。図面において、１は半導体チップを
搭載するパッドで、該パッド１の外周にはリ−ド２が設
けられている。３は前記パッド１を支持しているサポ−
トバ−で、４は前記リ−ド２を連結するとともに封止樹
脂を堰き止めるタイバ−である。これらパタ−ンからな
るリードフレームは例えば０．１８〜０．１２５ｍｍ厚
みの金属板から製造されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to the drawings. In the drawings, reference numeral 1 denotes a pad on which a semiconductor chip is mounted, and a lead 2 is provided on the outer periphery of the pad 1. 3 is a support for supporting the pad 1.
Reference numeral 4 denotes a tie connecting the leads 2 and blocking the sealing resin. The lead frame made of these patterns is manufactured from a metal plate having a thickness of, for example, 0.18 to 0.125 mm.

【００１０】前記パッド１は表裏両面側からハ−フエッ
チング、電解研磨、研削等により厚みを減じられてい
る。該薄くした厚み深さは搭載する半導体チップ５の厚
み以上または同等で、該薄くした箇所に半導体チップ５
が入り込んで薄くする前のパッド上面から突出せず、接
着材６例えばポリイミド樹脂、エポキシ樹脂等を介して
搭載される。The thickness of the pad 1 is reduced by half etching, electrolytic polishing, grinding and the like from both sides. The thinned depth is equal to or greater than the thickness of the semiconductor chip 5 to be mounted.
Does not protrude from the upper surface of the pad before being thinned, and is mounted via an adhesive 6 such as a polyimide resin or an epoxy resin.

【００１１】前記厚みを薄くしたパッド１の両面に搭載
される半導体チップ５は厚みが例えば好ましくは数十μ
ｍ程度の極薄ものが用いられる。極薄の半導体チップ５
は半導体装置の製造工程における取扱いが難しいが、本
発明ではパッド１を薄くした箇所に入れ込み接着材６を
介して搭載するから取扱いが容易で製造し易く、またパ
ッド１に保護された形態になり不要な外力がかからず耐
損傷性が高まる。The semiconductor chips 5 mounted on both sides of the thinned pad 1 have a thickness of, for example, preferably several tens μm.
m is used. Ultra-thin semiconductor chip 5
Although it is difficult to handle in the manufacturing process of the semiconductor device, in the present invention, since the pad 1 is inserted into a thinned portion and mounted via the adhesive 6, it is easy to handle and easy to manufacture, and the pad 1 is protected. Unnecessary external force is not applied and damage resistance is increased.

【００１２】半導体チップ５は前記パッド１の外周に設
けられたリ−ド２と金属線例えばボンディングワイヤ−
７を介して電気的に接続され、タイバ−４の内側以内が
封止樹脂８でパッケージされる。The semiconductor chip 5 includes a lead 2 provided on the outer periphery of the pad 1 and a metal wire such as a bonding wire.
7, and the inside of the tie bar-4 is packaged with the sealing resin 8.

【００１３】その後、前記タイバ−４は切除され、封止
樹脂８から出ているリ−ド２部はパッケージ下面、即ち
前記封止樹脂８下面と同等または封止樹脂８下面より前
記リ−ド２の厚み分以内下方に端部下面が位置するよう
に成形される。また、封止樹脂８から側面側に出たリ−
ド２の長さは可及的に短くし、実装密度を高めることが
できる。Thereafter, the tie bar 4 is cut off, and a portion of the lead 2 protruding from the sealing resin 8 is formed on the lower surface of the package, that is, the same as or lower than the lower surface of the sealing resin 8. It is formed so that the lower surface of the end portion is located below by the thickness of 2. In addition, a land protruding from the sealing resin 8 to the side surface side.
The length of the node 2 can be made as short as possible, and the mounting density can be increased.

【００１４】このようにして得られた半導体装置９は半
導体チップ５をパッド１の両面に搭載していながら一層
の薄手化したもの例えば０．５ｍｍ以下のものが得られ
る。The semiconductor device 9 obtained in this way has a thinner thickness, for example, 0.5 mm or less, while the semiconductor chip 5 is mounted on both sides of the pad 1.

【００１５】この実施例でのパッド１は端部を残して中
央部の厚みを薄くしたものであるが、これに限らずパッ
ド１の全面を両面側から薄くしたものでも使用できる。In this embodiment, the pad 1 has a reduced thickness at the center portion while leaving the end portion. However, the present invention is not limited to this, and the pad 1 may have a thinner surface from both sides.

【００１６】[0016]

【発明の効果】本発明による半導体装置は、パッドが両
面側から薄くされ、該薄くした両面に半導体チップを埋
め込むように搭載し、該半導体チップの端子とパッドの
外周に設けたリードをボンディングワイヤ−等の接続体
で電気的に接続し、樹脂封止している。また、パッドを
薄くした深さが半導体チップの厚みと同等あるいはそれ
以上で、該薄くした部分に半導体チップが入り込んで搭
載されているので、高集積、多機能化ができて、且つ薄
くなる。さらに半導体チップはパッドに保護される形態
で搭載され、耐損傷性が高まる。In the semiconductor device according to the present invention, the pads are thinned from both sides, semiconductor chips are mounted on both sides of the thinned chips, and the terminals of the semiconductor chips and the leads provided on the outer periphery of the pads are bonded with bonding wires. -And the like, and are electrically sealed by resin. In addition, since the depth at which the pad is thinned is equal to or greater than the thickness of the semiconductor chip, and the semiconductor chip is inserted into the thinned portion and mounted, high integration, multifunctionalization and thinning can be achieved. Further, the semiconductor chip is mounted in a form protected by the pad, and the damage resistance is improved.

【００１７】また、本発明の半導体装置は封止樹脂から
出たリ−ドの下面が封止樹脂下面と同等または若干下方
の位置に成形され、この点からも薄手化がなされ、実装
性も高まる等の効果がある。Further, in the semiconductor device of the present invention, the lower surface of the lead protruding from the sealing resin is formed at a position equal to or slightly lower than the lower surface of the sealing resin. There are effects such as heightening.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の１実施例における半導体装置の側断面
を示す図。FIG. 1 is a diagram showing a side cross section of a semiconductor device according to one embodiment of the present invention.

【図２】本発明の１実施例における半導体装置の組立途
中の平面を示す図。FIG. 2 is a diagram showing a plane in the middle of assembling the semiconductor device according to one embodiment of the present invention;

【符号の説明】[Explanation of symbols]

１ パッド、 ２ リ−ド ３ サポ−トバ−、 ４ タイバ− ５ 半導体チップ、 ６ 接着材 ７ ボンディングワイヤ−、８ 封止樹脂 ９ 半導体装置 REFERENCE SIGNS LIST 1 pad, 2 lead 3 support bar, 4 tie bar 5 semiconductor chip, 6 adhesive 7 bonding wire, 8 sealing resin 9 semiconductor device

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 23/28 23/50 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 23/28 23/50

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 両面側から厚みを薄くしたパッドに、半
導体チップが前記薄くした箇所に入り込んで搭載され、
該半導体チップの端子と前記パッドの周りに設けたリ−
ドを金属線を介して電気的に接続し、前記金属線の接続
箇所を含むリ−ド部、パッド、半導体チップを樹脂封止
したことを特徴とする半導体装置。1. A semiconductor chip is mounted on a pad whose thickness is reduced from both sides, by penetrating into the thinned portion,
Terminals provided around the terminals of the semiconductor chip and the pads.
A semiconductor device, wherein leads are electrically connected via metal wires, and leads, pads, and semiconductor chips including connection portions of the metal wires are sealed with a resin. 【請求項２】 前記パッドの厚みを薄くした深さが半導
体チップの厚み以上または同等で、該薄くした箇所に半
導体チップが入り込んで搭載されていることを特徴とす
る請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the depth of the reduced thickness of the pad is equal to or greater than the thickness of the semiconductor chip, and the semiconductor chip is mounted so as to enter the reduced thickness. . 【請求項３】 前記樹脂封止から出ている前記リ−ドの
下面は樹脂封止の下面と同等あるいは当該リ−ドの厚み
分以内下側に位置していることを特徴とする請求項１ま
たは請求項２記載の半導体装置。3. The lower surface of the lead protruding from the resin encapsulation is located at a position equal to or lower than the lower surface of the resin encapsulation by the thickness of the lead. The semiconductor device according to claim 1.
JP31395998A 1998-10-16 1998-10-16 Semiconductor device Pending JP2000124396A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31395998A JP2000124396A (en) 1998-10-16 1998-10-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31395998A JP2000124396A (en) 1998-10-16 1998-10-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2000124396A true JP2000124396A (en) 2000-04-28

Family

ID=18047556

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Cited By (3)

* Cited by examiner, † Cited by third party
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JP2002353403A (en) * 2001-03-05 2002-12-06 Samsung Electronics Co Ltd Ultra-thin semiconductor package and manufacturing method therefor
JP2003031752A (en) * 2001-07-11 2003-01-31 Sony Corp Lead frame, semiconductor device and manufacturing method therefor
KR100445071B1 (en) * 2001-03-05 2004-08-21 삼성전자주식회사 Ultra-thin semiconductor package device having different thickness of die pad and leads, and method for manufacturing the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002353403A (en) * 2001-03-05 2002-12-06 Samsung Electronics Co Ltd Ultra-thin semiconductor package and manufacturing method therefor
KR100445071B1 (en) * 2001-03-05 2004-08-21 삼성전자주식회사 Ultra-thin semiconductor package device having different thickness of die pad and leads, and method for manufacturing the same
US7012325B2 (en) 2001-03-05 2006-03-14 Samsung Electronics Co., Ltd. Ultra-thin semiconductor package device and method for manufacturing the same
US7253026B2 (en) 2001-03-05 2007-08-07 Samsung Electronics Co., Ltd. Ultra-thin semiconductor package device and method for manufacturing the same
JP4549608B2 (en) * 2001-03-05 2010-09-22 三星電子株式会社 Ultra-thin semiconductor package and manufacturing method thereof
JP2003031752A (en) * 2001-07-11 2003-01-31 Sony Corp Lead frame, semiconductor device and manufacturing method therefor

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