JP2000106428A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2000106428A
JP2000106428A JP10273292A JP27329298A JP2000106428A JP 2000106428 A JP2000106428 A JP 2000106428A JP 10273292 A JP10273292 A JP 10273292A JP 27329298 A JP27329298 A JP 27329298A JP 2000106428 A JP2000106428 A JP 2000106428A
Authority
JP
Japan
Prior art keywords
insulating film
conductivity type
film
layer
silicon carbide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10273292A
Other languages
Japanese (ja)
Inventor
Seiji Imai
聖支 今井
Takashi Shinohe
孝 四戸
Setsuko Kobayashi
節子 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP10273292A priority Critical patent/JP2000106428A/en
Publication of JP2000106428A publication Critical patent/JP2000106428A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To realize an SiC vertical FET, which brings out fully the material characteristics of an SiC and can be stably operated. SOLUTION: A semiconductor device is constituted into a structure, wherein the device has a first conductivity type low-resistance silicon carbide substrate 1, a first conductivity type high-resistance drift layer 2, which is formed on the substrate 1 by an epitaxial growth method and consists of a silicon carbide layer, second conductivity type base regions 7 formed in each one part of the surface layer of the layer 2, first conductivity type source regions 8 formed within the regions 7, a gate insulating film 10 formed selectively on one part of the surface of the layer 2, a surface protective film and a gate electrode 9 formed on the film 10, the film 10 consists of at least a two-layer insulating film formed in the order of a first insulating film 3 and a second insulating film 4, the dielectric constant of the film 3 is set higher than that of a silicon oxide film and a band gap in the film 4 is set longer than that in the film 3.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は高耐圧且つ低電流損
失な半導体装置に関する。The present invention relates to a semiconductor device having a high breakdown voltage and a low current loss.

【０００２】[0002]

【従来の技術】高耐圧、低損失のパワーデバイス用半導
体として、従来のＳｉに換わるＳｉＣが期待されてい
る。それはＳｉＣがＳｉと比較してバンドギャップが２
〜３倍、絶縁破壊強度が約１０倍、飽和電子ドリフト速
度が約２倍と大きくそのため同半導体をパワーデバイス
に応用した場合、デバイスの高耐圧化、高温動作及び高
周波動作が可能となるからである。特にＳｉＣを縦形Ｆ
ＥＴに応用した場合、Ｓｉと比較し１ＫＶ以上の阻止電
圧においてオン抵抗をほぼ２桁と大きく低減できること
が示されている（これについては、Ｂ．Ｊ．Ｂａｌｉｇ
ａ、゛Ｔｒｅｎｄｓｉｎ Ｐｏｗｅｒ Ｓｅｍｉｃｏｎ
ｄｕｃｔｏｒ Ｄｅｖｉｃｅｓ゜ＩＥＥＥＴｒａｎｓ．
Ｅｌｅｃｔｒｏｎ Ｄｅｖｉｃｅｓ、ｖｏｌ．４３ ｐ
ｐ１７１７〜１７３１、１９９６に詳しく記載されてい
る。）。2. Description of the Related Art As a semiconductor for a power device having a high breakdown voltage and a low loss, SiC is expected to replace conventional Si. This is because SiC has a band gap of 2 compared to Si.
Up to 3 times, the breakdown strength is about 10 times, and the saturation electron drift speed is about 2 times, so that when the same semiconductor is applied to a power device, it becomes possible to increase the breakdown voltage of the device, operate at high temperature and operate at high frequency. is there. In particular, use SiC for vertical F
It has been shown that when applied to ET, the on-resistance can be significantly reduced by almost two orders of magnitude at a blocking voltage of 1 KV or more as compared with Si (this is described in BJ Balig).
a, @ Trendsin Power Semiconductor
duct Devices @ IEEETrans.
Electron Devices, vol. 43 p
pp. 1717-1731, 1996. ).

【０００３】しかし、ＳｉＣ縦形ＦＥＴについては以下
の様な問題がある。一般に縦形ＦＥＴでは、表面保護膜
及びゲート絶縁膜に酸化シリコン膜が用いられている。
この様な層構造においてＳｉＣの優れた物性を引き出す
ためにＳｉＣに臨界近くの電界を印可した場合、相対的
に誘電率の小さな酸化シリコン膜に大きな電界が印可さ
れることになる。ここで印可された電界は酸化シリコン
膜の絶縁破壊強度とほぼ同レベルにまで達し、その結果
ＳｉＣ縦形ＦＥＴの安定動作を確保することが困難とな
る。そこで絶縁膜に酸化シリコンより誘電率の大きな材
料を用いて同膜に印可される電界を低減することが考え
られるが、ここにもまた新たな問題が発生する。すなわ
ち酸化シリコンより誘電率の大きな絶縁材料が、必ずし
もＳｉＣより十分に大きなバンドギャップを持つとは限
らないということである。そのためこのような材料を絶
縁膜に用いた場合、ＳｉＣとの界面で十分にバリアハイ
トを取ることができない。結果として酸化シリコンとＳ
ｉＣとからなる構造と比較して上記の層構造ではトンネ
ルリーク電流が無視できない程大きくなり、デバイスの
信頼性が低下してしまう。従ってＳｉＣ縦形ＦＥＴにお
いてＳｉＣの材料特性を十分に引き出し且つ安定動作さ
せるには、絶縁膜に印可される電界を低減することと、
さらに絶縁膜とＳｉＣとの層構造におけるトンネルリー
ク電流を低減することの２つの問題を同時に解決しなけ
ればならない。しかしこれまでにこれら２つの問題に対
して、その解決に向けて十分な検討がなされていなかっ
たのが現状である。However, there are the following problems with the SiC vertical FET. Generally, in a vertical FET, a silicon oxide film is used for a surface protection film and a gate insulating film.
When a near-critical electric field is applied to SiC in order to bring out the excellent physical properties of SiC in such a layer structure, a large electric field is applied to a silicon oxide film having a relatively small dielectric constant. The electric field applied here reaches almost the same level as the dielectric breakdown strength of the silicon oxide film. As a result, it is difficult to ensure stable operation of the SiC vertical FET. Therefore, it is conceivable to reduce the electric field applied to the insulating film by using a material having a higher dielectric constant than silicon oxide, but this also causes a new problem. That is, an insulating material having a higher dielectric constant than silicon oxide does not always have a band gap sufficiently larger than SiC. Therefore, when such a material is used for the insulating film, a sufficient barrier height cannot be obtained at the interface with SiC. As a result, silicon oxide and S
Compared with the structure composed of iC, the above-described layer structure has a tunnel leakage current that is not negligibly large, and lowers the reliability of the device. Therefore, in order to sufficiently draw out the material characteristics of SiC and perform stable operation in the SiC vertical FET, it is necessary to reduce the electric field applied to the insulating film;
Further, two problems of reducing the tunnel leak current in the layer structure of the insulating film and SiC must be solved at the same time. However, at present, these two problems have not been sufficiently studied to solve them.

【０００４】[0004]

【発明が解決しようとする課題】以上のように従来のＳ
ｉＣ縦形ＦＥＴでは、絶縁膜に印可される電界を低減す
ることと、さらに絶縁膜とＳｉＣとの層構造におけるト
ンネルリーク電流を低減することの２つの問題を同時に
解決しなければならない。しかし、これまでこれらの問
題に対してその解決に向けて十分な考慮がなされていな
かった。本発明は上記の点に鑑みてなされたものであ
り、その目的はＳｉＣの材料特性を十分に引き出し、且
つ安定動作可能なＳｉＣ縦形ＦＥＴの実現に寄与する半
導体装置を提供することにある。As described above, the conventional S
In the iC vertical FET, two problems of reducing the electric field applied to the insulating film and reducing the tunnel leak current in the layered structure of the insulating film and SiC must be simultaneously solved. However, these problems have not been sufficiently considered to solve them. The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device that sufficiently draws out the material characteristics of SiC and contributes to the realization of a SiC vertical FET that can operate stably.

【０００５】[0005]

【課題を解決するための手段】上記課題を解決するため
に本発明は、次のような構成を採用している。In order to solve the above problems, the present invention employs the following configuration.

【０００６】即ち、本発明（請求項１）は、第一導電型
の低抵抗炭化珪素基板と、前記炭化珪素基板上にエピタ
キシャル成長法等により形成された炭化珪素の第一導電
型高抵抗ドリフト層と、前記第一導電型高抵抗ドリフト
層の表面層の一部に形成された第二導電型ベース領域
と、前記第二導電型ベース領域内に形成された第一導電
型ソース領域と、前記第一導電型高抵抗ドリフト層の表
面の一部に選択的に形成されたゲート絶縁膜及び、表面
保護膜と、前記ゲート絶縁膜上に形成されたゲート電極
を有する半導体装置であって、前記ゲート絶縁膜が第一
の絶縁膜及び、第二の絶縁膜の順に形成された少なくと
も２層の絶縁膜からなり、第一の絶縁膜の誘電率は酸化
シリコンの誘電率より大きく、第二の絶縁膜のバンドギ
ャップは第一の絶縁膜のバンドギャップより大きいこと
を特徴とする。That is, the present invention (claim 1) provides a first conductivity type low resistance silicon carbide substrate and a first conductivity type high resistance drift layer of silicon carbide formed on the silicon carbide substrate by an epitaxial growth method or the like. And a second conductivity type base region formed in a part of the surface layer of the first conductivity type high resistance drift layer, a first conductivity type source region formed in the second conductivity type base region, A semiconductor device having a gate insulating film selectively formed on a part of the surface of the first conductivity type high-resistance drift layer and a surface protective film, and a gate electrode formed on the gate insulating film, The gate insulating film includes a first insulating film and at least two layers of insulating films formed in the order of the second insulating film. The dielectric constant of the first insulating film is larger than the dielectric constant of silicon oxide. The band gap of the insulation film is the first insulation Characterized in that the larger than the band gap.

【０００７】また、本発明（請求項２）は、第一導電型
の低抵抗炭化珪素基板と、前記炭化珪素基板上にエピタ
キシャル成長法等により順に形成された炭化珪素の第一
導電型高抵抗ドリフト層と炭化珪素の第二導電型ベース
層と、前記第二導電型ベース層内に形成された第一導電
型ソース領域と、前記第一導電型ソース領域から前記第
一導電型高抵抗ドリフト層に達するトレンチと、前記第
二導電型ベース層の表面の一部に選択的に形成された表
面保護膜と、前記トレンチ内にゲート絶縁膜を介して電
圧を印可するゲート電極を有する半導体装置であって、
前記ゲート絶縁膜が第一の絶縁膜及び、第二の絶縁膜の
順に形成された少なくとも２層の絶縁膜からなり、第一
の絶縁膜の誘電率は酸化シリコンの誘電率より大きく、
第二の絶縁膜のバンドギャップは第一の絶縁膜のバンド
ギャップより大きいことを特徴とする。Further, the present invention (claim 2) provides a first conductive type low resistance silicon carbide substrate and a first conductive type high resistance drift of silicon carbide formed sequentially on the silicon carbide substrate by an epitaxial growth method or the like. Layer and a second conductivity type base layer of silicon carbide, a first conductivity type source region formed in the second conductivity type base layer, and a first conductivity type high resistance drift layer from the first conductivity type source region. And a surface protection film selectively formed on a part of the surface of the second conductivity type base layer, and a gate electrode for applying a voltage via a gate insulating film in the trench. So,
The gate insulating film includes a first insulating film and at least two layers of insulating films formed in the order of the second insulating film, and a dielectric constant of the first insulating film is larger than a dielectric constant of silicon oxide;
The band gap of the second insulating film is larger than the band gap of the first insulating film.

【０００８】また、本発明（請求項３）は、請求項１又
は２に記載の半導体装置において前記表面保護膜が、第
一の絶縁膜及び、第二の絶縁膜の順に形成された少なく
とも２層の絶縁膜からなり、第一の絶縁膜の誘電率は酸
化シリコンの誘電率より大きく、第二の絶縁膜のバンド
ギャップは第一の絶縁膜のバンドギャップより大きいこ
とを特徴とする。According to the present invention (claim 3), in the semiconductor device according to claim 1 or 2, the surface protective film is formed by forming at least two of a first insulating film and a second insulating film in this order. The first insulating film has a dielectric constant larger than that of silicon oxide, and a band gap of the second insulating film is larger than a band gap of the first insulating film.

【０００９】また、本発明（請求項４）は、請求項１〜
３のいずれか１項に記載の半導体装置において前記第一
の絶縁膜と前記第二の絶縁膜が、それぞれＡｌＮ，Ｂ
Ｎ，Ｓｉ３Ｎ４，Ｔａ２Ｏ５，ＴｉＯ２，Ａｌ２Ｏ３，
ＢａＴｉＯ３の一群と、ＳｉＯ２、Ａｌ２Ｏ３，Ｂ２Ｏ
３，ダイヤモンド，ダイヤモンド・ライク炭素の一群よ
り選択された１種類あるいは複数種類から形成されてい
ることを特徴とする。Further, the present invention (claim 4) provides claims 1 to
3. The semiconductor device according to claim 3, wherein the first insulating film and the second insulating film are made of AlN, B, respectively.
N, Si3N4, Ta2O5, TiO2, Al2O3
A group of BaTiO3, SiO2, Al2O3, B2O
3, characterized by being formed from one or more kinds selected from the group consisting of diamond and diamond-like carbon.

【００１０】また、本発明（請求項５）は、請求項１〜
４のいずれか１項に記載の半導体装置において前記炭化
珪素基板が、六方晶系炭化珪素よりなることを特徴とす
る。The present invention (Claim 5) provides Claims 1 to
5. The semiconductor device according to claim 4, wherein the silicon carbide substrate is made of hexagonal silicon carbide.

【００１１】（作用）本発明によれば、ゲート絶縁膜、
あるいはまた表面保護膜が酸化シリコンより誘電率の大
きい第一の絶縁膜と、第一の絶縁膜よりバンドギャップ
の大きい第二の絶縁膜の少なくとも二層から形成されて
いることにより、ＳｉＣ縦形ＦＥＴの高耐圧化と低電流
損失化を同時に図ることができる。すなわち、上記絶縁
膜として酸化シリコンを用いた場合と比較して、まず高
誘電率な第一の絶縁膜により同膜に印可される電界を効
果的に軽減してゲート領域及びソース・ドレイン間の高
耐圧化を図るとともに、一方で第一の絶縁膜上にバンド
ギャップのより大きい第二の絶縁膜を形成した層構造を
用いてＳｉＣとの界面でバリアハイトを十分に大きく取
り、これによりトンネルリーク電流を低減して低電流損
失化を図ることができる。従って上記のような少なくと
も二層以上の積層された絶縁膜を用いることにより、Ｓ
ｉＣの材料特性を十分に引き出し、且つ安定動作可能な
ＳｉＣ縦形ＦＥＴを実現することができるのである。(Operation) According to the present invention, a gate insulating film,
Alternatively, since the surface protective film is formed of at least two layers of a first insulating film having a larger dielectric constant than silicon oxide and a second insulating film having a larger band gap than the first insulating film, the SiC vertical FET , A high withstand voltage and a low current loss can be simultaneously achieved. That is, compared to the case where silicon oxide is used as the insulating film, first, the electric field applied to the first insulating film having a high dielectric constant is effectively reduced to reduce the electric field applied between the gate region and the source / drain. Along with increasing the withstand voltage, the barrier height at the interface with SiC is made sufficiently large by using a layer structure in which a second insulating film having a larger band gap is formed on the first insulating film, thereby improving tunnel leakage. The current can be reduced to reduce the current loss. Therefore, by using at least two or more laminated insulating films as described above, S
It is possible to realize a SiC vertical FET that can sufficiently draw out the material characteristics of iC and can operate stably.

【００１２】[0012]

【発明の実施の形態】以下、本発明の詳細を図示の実施
形態によって説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments.

【００１３】（第一の実施形態）図１は本発明による第
一の実施例のＳｉＣ縦形ＦＥＴの断面図である。本実施
例において第一導電型としてｎ型を、また第二導電型と
してｐ型を用いた。ｎ型低抵抗ＳｉＣ基板１上にエピタ
キシャル法によりｎ型高抵抗ドリフト層２を形成する。
そのｎ型高抵抗ドリフト層２上にスパッタ法あるいはＣ
ＶＤ法等により酸化シリコンより誘電率の大きい第一の
絶縁膜３と第一の絶縁膜３よりバンドギャップの大きい
第二の絶縁膜４を順に形成する。FIG. 1 is a sectional view of a SiC vertical FET according to a first embodiment of the present invention. In this example, n-type was used as the first conductivity type and p-type was used as the second conductivity type. An n-type high-resistance drift layer 2 is formed on an n-type low-resistance SiC substrate 1 by an epitaxial method.
A sputtering method or C
A first insulating film 3 having a larger dielectric constant than silicon oxide and a second insulating film 4 having a larger band gap than the first insulating film 3 are sequentially formed by a VD method or the like.

【００１４】次に第二の絶縁膜４上にＣＶＤ法等により
ｎ型低抵抗のポリＳｉ膜５を形成する。ここでポリＳｉ
膜５の代りに、ポリＳｉＣ膜、ポリＳｉＧｅ膜のいずれ
かあるいはポリＳｉ膜を含めたそれらの複合膜を用いて
もよい。その後ポリＳｉ膜５上にＣＶＤ法によりＳｉＯ
２膜（不図示。）を全面に形成する。次にウェットエッ
チングあるいはドライエッチング法等により選択的にＳ
ｉＯ２膜、ポリＳｉ膜５、第二の絶縁膜４、第一の絶縁
膜３の順にエッチングしゲート領域６を形成する。ここ
で、ゲート領域６以外で第一の絶縁膜３の一部あるいは
全部をエッチングせずに残し、後に述べるイオン注入工
程のシャドウマスクとして用いても良い。また、このと
きｎ型高抵抗ドリフト層２上の少なくとも一部に選択的
に第一の絶縁膜３と第二の絶縁膜４からなる表面保護膜
（不図示。例えば、半導体基板上に形成された複数の素
子のうち隣接する素子を電気的に分離するための素子分
離絶縁膜等である。後述する表面保護膜でも同様であ
る。）を形成しておく。Next, an n-type low-resistance poly-Si film 5 is formed on the second insulating film 4 by a CVD method or the like. Where poly Si
Instead of the film 5, any one of a poly-SiC film and a poly-SiGe film or a composite film thereof including a poly-Si film may be used. Thereafter, the SiO 2 film is formed on the poly-Si film 5 by CVD.
Two films (not shown) are formed on the entire surface. Next, S is selectively formed by wet etching or dry etching.
The gate region 6 is formed by etching the iO2 film, the poly-Si film 5, the second insulating film 4, and the first insulating film 3 in this order. Here, a part or the whole of the first insulating film 3 other than the gate region 6 may be left without being etched, and may be used as a shadow mask in an ion implantation process described later. At this time, a surface protection film (not shown, for example, formed on a semiconductor substrate) composed of the first insulating film 3 and the second insulating film 4 is selectively formed on at least a part of the n-type high-resistance drift layer 2. Out of a plurality of elements, an element isolation insulating film or the like for electrically isolating adjacent elements. The same applies to a surface protection film described later.

【００１５】次にゲート領域６と表面保護膜（不図示）
をマスクとしてｎ型高抵抗ドリフト層２内にアルミニウ
ムあるいはボロン等のｐ型のイオン注入とその後の活性
化熱処理により選択的にｐベース領域７を形成する。次
にｐベース領域７内に窒素等のｎ型のイオン注入とその
後の活性化熱処理により選択的にｎ+ ソース領域８を形
成する。次にゲート領域のＳｉＯ２膜をウェットエッチ
ング等により除去した後、ポリＳｉ膜５上にゲート電極
層９を選択的に形成する。次にゲート電極層９の上面に
絶縁膜１０を形成する。次に絶縁膜１０上を含むｎ+ ソ
ース領域８とｐベース領域７の上に、ソース電極層１１
を形成する。又、ｎ型低抵抗ＳｉＣ基板１の表面に、ド
レイン電極層１２を形成して、ＳｉＣ縦形ＦＥＴを完成
する。Next, the gate region 6 and a surface protection film (not shown)
Is used as a mask to selectively form a p base region 7 in the n-type high resistance drift layer 2 by implanting a p-type ion such as aluminum or boron and then performing an activation heat treatment. Next, an n + source region 8 is selectively formed in the p base region 7 by implanting n-type ions such as nitrogen and a subsequent activation heat treatment. Next, after removing the SiO 2 film in the gate region by wet etching or the like, a gate electrode layer 9 is selectively formed on the poly-Si film 5. Next, an insulating film 10 is formed on the upper surface of the gate electrode layer 9. Next, the source electrode layer 11 is formed on the n + source region 8 and the p base region 7 including on the insulating film 10.
To form Further, a drain electrode layer 12 is formed on the surface of the n-type low-resistance SiC substrate 1 to complete a SiC vertical FET.

【００１６】このように本実施の形態では、ゲート絶縁
膜、あるいはまた表面保護膜が酸化シリコンより誘電率
の大きい第一の絶縁膜と、第一の絶縁膜よりバンドギャ
ップの大きい第二の絶縁膜の少なくとも二層から形成さ
れていることにより、ＳｉＣ縦形ＦＥＴの高耐圧化と低
電流損失化を同時に図ることができる。すなわち、上記
絶縁膜として酸化シリコンを用いた場合と比較して、ま
ず高誘電率な第一の絶縁膜により同膜に印可される電界
を効果的に軽減してゲート領域及びソース・ドレイン間
の高耐圧化を図るとともに、一方で第一の絶縁膜上にバ
ンドギャップのより大きい第二の絶縁膜を形成した層構
造を用いてＳｉＣとの界面でバリアハイトを十分に大き
く取り、これによりトンネルリーク電流を低減して低電
流損失化を図ることができる。又、ここで述べてきたよ
うに結果として絶縁膜への電界負荷が軽減できることか
らゲート絶縁膜及び表面保護膜の寿命を大幅に長くする
ことができる。As described above, in this embodiment, the gate insulating film or the surface protective film has a first insulating film having a larger dielectric constant than silicon oxide, and a second insulating film having a larger band gap than the first insulating film. By forming the film from at least two layers, it is possible to simultaneously increase the breakdown voltage and reduce the current loss of the SiC vertical FET. That is, compared to the case where silicon oxide is used as the insulating film, first, the electric field applied to the first insulating film having a high dielectric constant is effectively reduced to reduce the electric field applied between the gate region and the source / drain. Along with increasing the withstand voltage, the barrier height at the interface with SiC is made sufficiently large by using a layer structure in which a second insulating film having a larger band gap is formed on the first insulating film, thereby improving tunnel leakage. The current can be reduced to reduce the current loss. Further, as described herein, as a result, the electric field load on the insulating film can be reduced, so that the lifespan of the gate insulating film and the surface protective film can be greatly extended.

【００１７】また、上記の積層絶縁膜を用いてＳｉＣの
材料特性を最大限に引き出すためには、第一の絶縁膜は
以下の条件式（不等式）を満足することが望ましい。そ
の条件式の導出過程を以下に説明する。まず第一の絶縁
膜とＳｉＣとの層構造において、ガウスの法則により以
下の等式が成立する。ここで、εｉ、Ｅｉ、εＳｉＣ、
ＥＳｉＣはそれぞれ順に第一の絶縁膜の誘電率及びそれ
に印可される電界強度、とＳｉＣの誘電率及びそれに印
可される電界強度である。In order to maximize the material characteristics of SiC using the above-mentioned laminated insulating film, it is desirable that the first insulating film satisfies the following conditional expression (inequality). The process of deriving the conditional expression will be described below. First, in the layer structure of the first insulating film and SiC, the following equation is established by Gauss' law. Where εi, Ei, εSiC,
ESiC is the dielectric constant of the first insulating film and the electric field strength applied thereto, and the dielectric constant of SiC and the electric field strength applied thereto, respectively.

【００１８】 εｉ＊Ｅｉ＝εＳｉＣ＊ＥＳｉＣ （１） 従って第一の絶縁膜に印可される電界強度Ｅｉは（１）
式より Ｅｉ＝（εＳｉＣ／εｉ）＊ＥＳｉＣ （２） となる。ここで電界強度Ｅｉは、第一の絶縁膜の絶縁破
壊を防ぐためにその臨界破壊電界強度Ｅｃ（ｉ）より小
さくなければならない。従って（２）式より Ｅｉ＝（εＳｉＣ／εｉ）＊ＥＳｉＣ＜Ｅｃ（ｉ） （３） となる。ここで、さらにＳｉＣの材料特性を最大限に引
き出すためにＳｉＣにその臨界破壊電界強度Ｅｃ（Ｓｉ
Ｃ）を印可した場合には、（３）式より （εＳｉＣ／εｉ）＊Ｅｃ（ＳｉＣ）＜Ｅｃ（ｉ） （４） となる。従ってＳｉＣの材料特性を最大限に引き出し、
且つデバイスを安定動作させるために、第一の絶縁膜と
してはその臨界破壊電界強度Ｅｃ（ｉ）とその誘電率ε
ｉとの関係が上記の不等式（４）を満足するように選択
されることがより望ましい。Εi * Ei = εSiC * ESiC (1) Therefore, the electric field strength Ei applied to the first insulating film is (1)
From the equation, Ei = (εSiC / εi) * ESiC (2) Here, the electric field strength Ei must be smaller than the critical breakdown electric field strength Ec (i) in order to prevent dielectric breakdown of the first insulating film. Therefore, from equation (2), Ei = (εSiC / εi) * ESiC <Ec (i) (3) Here, in order to further maximize the material properties of SiC, the critical breakdown electric field strength Ec (Si
When (C) is applied, from equation (3), (εSiC / εi) * Ec (SiC) <Ec (i) (4) Therefore, the material properties of SiC are maximized,
In addition, in order to stably operate the device, the first insulating film has its critical breakdown electric field strength Ec (i) and its dielectric constant ε
More preferably, the relationship with i is selected so as to satisfy the above inequality (4).

【００１９】従ってゲート絶縁膜あるいはまた表面保護
膜に上記のような積層絶縁膜を用いることにより、Ｓｉ
Ｃの材料特性を十分に引き出し、且つ安定動作可能なＳ
ｉＣ縦形ＦＥＴを実現することができる。Therefore, by using the laminated insulating film as described above for the gate insulating film or the surface protective film,
S that can fully extract the material properties of C and can operate stably
An iC vertical FET can be realized.

【００２０】なお本実施の形態では、基本的な構造を説
明するために図１に示したような半導体装置を用いた
が、実際に電力用半導体装置として使用する場合は、図
１に示したようなユニットセルが数百個から数万個並列
接続されるものである。In this embodiment, the semiconductor device as shown in FIG. 1 is used to explain the basic structure. However, when the semiconductor device is actually used as a power semiconductor device, it is shown in FIG. Hundreds to tens of thousands of such unit cells are connected in parallel.

【００２１】（第二の実施形態）図２は本発明による第
二の実施例のＳｉＣトレンチゲート縦形ＦＥＴの断面図
である。本実施例において第一導電型としてｎ型を、ま
た第二導電型としてｐ型を用いた。ｎ型低抵抗ＳｉＣ基
板１０１上にエピタキシャル法によりｎ型高抵抗ドリフ
ト層１０２とｐ型ベース層１０３を順に形成する。その
ｐ型ベース層１０３の表面層に窒素等のｎ型のイオン注
入とその後の活性化熱処理により選択的にｎ+ ソース領
域１０４を形成する。さらにｐ型ベース層１０３の表面
層の別の所定領域にアルミニウムあるいはボロン等のｐ
型のイオン注入とその後の活性化熱処理によりｐ+ 領域
１０５を形成する。次にドライエッチング法（ＲＩＥ
法）によりｎ+ ソース領域１０４の表面からｎ+ ソース
領域１０４およびｐ型ベース層１０３を貫通してｎ型高
抵抗ドリフト層１０２に達するトレンチ１０６を形成す
る。ここで、トレンチ１０６の内壁表面にエピタキシャ
ル法によりｐ型薄膜層（不図示）を形成することが望ま
しい。それはｐ型薄膜層がトレンチ形成時に生じた表面
凹凸を低減しながら形成され、チャネル形成面を極めて
平坦とするからである。その結果チャネル移動度が飛躍
的に向上し、ソース・ドレイン間のオン抵抗を低減する
ことができる。この時ｐ型薄膜層の結晶型はｐ型ベース
層１０３の結晶型と同じとなり、又同薄膜層の不純物濃
度はｐ型ベース層１０３の不純物濃度より低く設定する
ことが望ましい。(Second Embodiment) FIG. 2 is a sectional view of a SiC trench gate vertical FET according to a second embodiment of the present invention. In this example, n-type was used as the first conductivity type and p-type was used as the second conductivity type. An n-type high-resistance drift layer 102 and a p-type base layer 103 are sequentially formed on an n-type low-resistance SiC substrate 101 by an epitaxial method. An n + source region 104 is selectively formed in the surface layer of the p-type base layer 103 by implanting n-type ions such as nitrogen and a subsequent activation heat treatment. Further, another predetermined region of the surface layer of the p-type base layer 103 is formed of p-type material such as aluminum or boron.
A p + region 105 is formed by ion implantation of a type and a subsequent activation heat treatment. Next, dry etching (RIE
Law) by forming the n + trench 106 from the surface of the source region 104 through the n + source region 104 and the p-type base layer 103 reaches the n-type high-resistance drift layer 102. Here, it is desirable to form a p-type thin film layer (not shown) on the inner wall surface of the trench 106 by an epitaxial method. This is because the p-type thin film layer is formed while reducing the surface irregularities generated during the formation of the trench, and makes the channel formation surface extremely flat. As a result, the channel mobility is dramatically improved, and the on-resistance between the source and the drain can be reduced. At this time, the crystal type of the p-type thin film layer is the same as the crystal type of the p-type base layer 103, and the impurity concentration of the thin film layer is desirably set lower than that of the p-type base layer 103.

【００２２】次にｎ+ ソース領域１０４の表面の一部と
トレンチ１０６内にスパッタ法あるいはＣＶＤ法等によ
り第一の絶縁膜１０７と第二の絶縁膜１０８を順に選択
的に形成する。また、このときｐ型ベース層１０３上の
少なくとも一部に選択的に第一の絶縁膜１０７と第二の
絶縁膜１０８からなる表面保護膜（不図示）を形成して
おくことが望ましい。そしてトレンチ１０６内の第二の
絶縁膜１０８の表面とトレンチ１０６の開口部の周囲に
ゲート電極層１０９を形成する。次にゲート電極層１０
９の上面に絶縁膜１１０を選択的に形成する。その後絶
縁膜１１０上を含むｎ+ ソース領域１０４とｐ+ 領域１
０５の上に、ソース電極層１１１を形成する。又、ｎ型
低抵抗ＳｉＣ基板１０１の表面に、ドレイン電極層１１
２を形成して、ＳｉＣトレンチゲート縦形ＦＥＴを完成
する。Next, a first insulating film 107 and a second insulating film 108 are selectively formed in order on the part of the surface of the n + source region 104 and the trench 106 by sputtering or CVD. At this time, it is desirable that a surface protection film (not shown) composed of the first insulating film 107 and the second insulating film 108 is selectively formed on at least a part of the p-type base layer 103. Then, a gate electrode layer 109 is formed on the surface of the second insulating film 108 in the trench 106 and around the opening of the trench 106. Next, the gate electrode layer 10
9, an insulating film 110 is selectively formed. Then, the n + source region 104 and the p + region 1 including on the insulating film 110 are formed.
The source electrode layer 111 is formed on the layer 05. Further, the drain electrode layer 11 is formed on the surface of the n-type low-resistance SiC substrate 101.
2 to complete the SiC trench gate vertical FET.

【００２３】本実施の形態でも第一の実施形態と同じ
く、ゲート絶縁膜、あるいはまた表面保護膜が酸化シリ
コンより誘電率の大きい第一の絶縁膜と、第一の絶縁膜
よりバンドギャップの大きい第二の絶縁膜の少なくとも
二層から形成されていることによりＳｉＣトレンチゲー
ト縦形ＦＥＴの高耐圧化と低電流損失化を同時に図るこ
とができる。また特にトレンチゲート縦形ＦＥＴではゲ
ート電圧印可時にトレンチコーナー部に局所的な電界集
中が起こりやすく安定動作を確保することが難しいが、
上記のような積層絶縁膜を用いれば電界集中を効果的に
緩和しデバイス動作の信頼性を飛躍的に高めることがで
きる。また、結果として絶縁膜への電界負荷を軽減でき
ることからゲート絶縁膜及び表面保護膜の寿命を大幅に
長くすることができる。また、本実施の形態でも第一の
実施形態と同様にＳｉＣの材料特性を最大限に引き出し
且つデバイスを安定動作させるために、第一の絶縁膜は
不等式（４）を満足するように選択されることがより望
ましい。In the present embodiment, as in the first embodiment, the gate insulating film or the surface protective film has a first insulating film having a larger dielectric constant than silicon oxide, and a band gap larger than the first insulating film. By being formed of at least two layers of the second insulating film, it is possible to simultaneously increase the breakdown voltage and reduce the current loss of the SiC trench gate vertical FET. In particular, in a trench gate vertical FET, local electric field concentration is likely to occur at a trench corner when a gate voltage is applied, and it is difficult to secure a stable operation.
The use of the laminated insulating film as described above can effectively reduce the electric field concentration and dramatically improve the reliability of device operation. In addition, since the electric field load on the insulating film can be reduced as a result, the life of the gate insulating film and the surface protective film can be significantly extended. Also in this embodiment, as in the first embodiment, the first insulating film is selected so as to satisfy the inequality (4) in order to maximize the material characteristics of SiC and stably operate the device. Is more desirable.

【００２４】従ってゲート絶縁膜あるいはまた表面保護
膜に上記のような積層絶縁膜を用いることにより、Ｓｉ
Ｃの材料特性を十分に引き出し、且つ安定動作可能なＳ
ｉＣ縦形ＦＥＴを実現することができる。Therefore, by using the laminated insulating film as described above for the gate insulating film or the surface protective film,
S that can fully extract the material properties of C and can operate stably
An iC vertical FET can be realized.

【００２５】なお本実施の形態でも、実際に電力用半導
体装置として使用する場合は、図２に示したようなユニ
ットセルが数百個から数万個並列接続されるものであ
る。Also in this embodiment, when actually used as a power semiconductor device, hundreds to tens of thousands of unit cells as shown in FIG. 2 are connected in parallel.

【００２６】また、本実施の形態ではトレンチ側面に成
長させる薄膜層はｐ型としているがこれに限定されるも
のではなく、ｎ型であっても良い。In the present embodiment, the thin film layer grown on the side surface of the trench is of p-type, but is not limited to this, and may be of n-type.

【００２７】また、本実施の形態で示したトレンチの構
造もそれだけに限られることはなく、Ｕ字型トレンチ
溝、Ｖ字型トレンチ溝等にしてもよい。さらにトレンチ
の側面は直線的に延びていなくてもよく、滑らかな曲面
でもよい。なおトレンチ側面と基板表面のなす角度は、
チャネル移動度が大きくなるように設計することによ
り、より良い効果が得られる。Further, the structure of the trench shown in this embodiment is not limited to this, but may be a U-shaped trench, a V-shaped trench or the like. Further, the side surfaces of the trench need not extend linearly and may have a smooth curved surface. The angle between the trench side and the substrate surface is
A better effect can be obtained by designing such that the channel mobility is increased.

【００２８】また以上の第一及び第二の実施形態ではｎ
チャネル型の縦形ＦＥＴのみについて説明したが、導電
型のｎとｐを入れ替えたｐチャネル型の縦形ＦＥＴにお
いても同じ効果を得ることができる。また上述の実施形
態において、第一の絶縁膜と第二の絶縁膜はそれぞれＡ
ｌＮ，ＢＮ，Ｓｉ３Ｎ４，Ｔａ２Ｏ５，ＴｉＯ２，Ａｌ
２Ｏ３，ＢａＴｉＯ３の一群と、ＳｉＯ２、Ａｌ２Ｏ
３，Ｂ２Ｏ３，ダイヤモンド，ダイヤモンド・ライク炭
素の一群より選択された１種類あるいは複数種類から形
成されていることが望ましい。それはこれらの材料の構
成に従えば第一及び第二の絶縁膜の条件を各々十分に満
足し、その結果ＳｉＣ縦形ＦＥＴの特性を十分に引き出
すことができるからである。In the first and second embodiments, n
Although only the channel type vertical FET has been described, the same effect can be obtained in a p-channel type vertical FET in which n and p are replaced. Further, in the above embodiment, the first insulating film and the second insulating film
1N, BN, Si3N4, Ta2O5, TiO2, Al
A group of 2O3, BaTiO3, SiO2, Al2O
3, B2O3, diamond, and diamond-like carbon. This is because, according to the configuration of these materials, the conditions of the first and second insulating films can be sufficiently satisfied, and as a result, the characteristics of the SiC vertical FET can be sufficiently brought out.

【００２９】また、上述の実施形態ではゲート絶縁膜と
表面保護膜とを同じ組み合わせの二層からなる積層絶縁
膜を用いたが、各々異なる組み合わせの少なくとも二層
からなる積層絶縁膜を用いても同様な効果が得られるこ
とはいうまでもない。また、ＳｉＣ基板１及び１０１に
用いるＳｉＣ（炭化珪素）単結晶はその最大電界強度の
大きい６Ｈ−ＳｉＣ、４Ｈ−ＳｉＣ，２Ｈ−ＳｉＣのい
ずれかを用いるのがよい。また本発明は縦形ＦＥＴに限
られたわけではなく、他の縦形パワーデバイスにも応用
できるものである。その他、本発明の要旨を逸脱しない
範囲で、種々変形して実施することができる。In the above-described embodiment, the laminated insulating film composed of two layers of the same combination of the gate insulating film and the surface protective film is used. However, the laminated insulating film composed of at least two layers of different combinations may be used. It goes without saying that a similar effect can be obtained. Further, as the SiC (silicon carbide) single crystal used for the SiC substrates 1 and 101, it is preferable to use any one of 6H-SiC, 4H-SiC, and 2H-SiC having a large maximum electric field strength. The present invention is not limited to a vertical FET, but can be applied to other vertical power devices. In addition, various modifications can be made without departing from the scope of the present invention.

【００３０】[0030]

【発明の効果】以上説明したように本発明によれば、ゲ
ート絶縁膜及び表面保護膜に積層された絶縁膜を用いる
ことにより、ＳｉＣの材料特性を十分に引き出し且つ安
定動作可能なＳｉＣ縦形ＦＥＴを実現することができ
る。As described above, according to the present invention, by using an insulating film laminated on a gate insulating film and a surface protection film, a SiC vertical FET capable of sufficiently extracting the material characteristics of SiC and operating stably. Can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第一の実施形態に係わるＳｉＣ縦形Ｆ
ＥＴの断面構造模式図。FIG. 1 shows a vertical SiC F according to a first embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view of the ET.

【図２】本発明の第二の実施形態に係わるＳｉＣトレン
チゲート縦形ＦＥＴの断面構造模式図。FIG. 2 is a schematic sectional view of a SiC trench gate vertical FET according to a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１…ｎ型低抵抗ＳｉＣ基板 ２…ｎ型高抵抗ドリフト層 ３…第一の絶縁膜 ４…第二の絶縁膜 ５…ポリＳｉ膜 ６…ゲート領域 ７…ｐベース領域 ８…ｎ+ ソース領域 ９…ゲート電極層 １０…絶縁膜 １１…ソース電極層 １２…ドレイン電極層 １０１…ｎ型低抵抗ＳｉＣ基板 １０２…ｎ型高抵抗ドリフト層 １０３…ｐ型ベース層 １０４…ｎ+ ソース領域 １０５…ｐ+ 領域 １０６…トレンチ １０７…第一の絶縁膜 １０８…第二の絶縁膜 １０９…ゲート電極層 １１０…絶縁膜 １１１…ソース電極層 １１２…ドレイン電極層DESCRIPTION OF SYMBOLS 1 ... n-type low resistance SiC substrate 2 ... n-type high resistance drift layer 3 ... 1st insulating film 4 ... 2nd insulating film 5 ... polySi film 6 ... gate region 7 ... p base region 8 ... n + source region Reference Signs List 9 gate electrode layer 10 insulating film 11 source electrode layer 12 drain electrode layer 101 n-type low resistance SiC substrate 102 n-type high resistance drift layer 103 p-type base layer 104 n + source region 105 p + Region 106 trench 107 first insulating film 108 second insulating film 109 gate electrode layer 110 insulating film 111 source electrode layer 112 drain electrode layer

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 第一導電型の低抵抗炭化珪素基板と、前
記炭化珪素基板上に形成された炭化珪素の第一導電型高
抵抗ドリフト層と、前記第一導電型高抵抗ドリフト層の
表面層の一部に形成された第二導電型ベース領域と、前
記第二導電型ベース領域内に形成された第一導電型ソー
ス領域と、前記第一導電型高抵抗ドリフト層の表面の一
部に選択的に形成されたゲート絶縁膜及び、表面保護膜
と、前記ゲート絶縁膜上に形成されたゲート電極を有す
る半導体装置であって、前記ゲート絶縁膜が第一の絶縁
膜及び、第二の絶縁膜の順に形成された少なくとも２層
の絶縁膜からなり、第一の絶縁膜の誘電率は酸化シリコ
ンの誘電率より大きく、第二の絶縁膜のバンドギャップ
は第一の絶縁膜のバンドギャップより大きいことを特徴
とする半導体装置。1. A low resistance silicon carbide substrate of a first conductivity type, a first conductivity type high resistance drift layer of silicon carbide formed on the silicon carbide substrate, and a surface of the first conductivity type high resistance drift layer A second conductivity type base region formed in part of the layer, a first conductivity type source region formed in the second conductivity type base region, and a part of the surface of the first conductivity type high resistance drift layer A semiconductor device having a gate insulating film selectively formed on the substrate, a surface protective film, and a gate electrode formed on the gate insulating film, wherein the gate insulating film has a first insulating film and a second insulating film. , The dielectric constant of the first insulating film is larger than the dielectric constant of silicon oxide, and the band gap of the second insulating film is the band gap of the first insulating film. A semiconductor device characterized by being larger than a gap. 【請求項２】 第一導電型の低抵抗炭化珪素基板と、前
記炭化珪素基板上に順に形成された炭化珪素の第一導電
型高抵抗ドリフト層と炭化珪素の第二導電型ベース層
と、前記第二導電型ベース層内に形成された第一導電型
ソース領域と、前記第一導電型ソース領域から前記第一
導電型高抵抗ドリフト層に達するトレンチと、前記第二
導電型ベース層の表面の一部に選択的に形成された表面
保護膜と、前記トレンチ内にゲート絶縁膜を介して電圧
を印可するゲート電極を有する半導体装置であって、前
記ゲート絶縁膜が第一の絶縁膜及び、第二の絶縁膜の順
に形成された少なくとも２層の絶縁膜からなり、第一の
絶縁膜の誘電率は酸化シリコンの誘電率より大きく、第
二の絶縁膜のバンドギャップは第一の絶縁膜のバンドギ
ャップより大きいことを特徴とする半導体装置。2. A low resistance silicon carbide substrate of a first conductivity type, a first conductivity type high resistance drift layer of silicon carbide and a second conductivity type base layer of silicon carbide formed sequentially on the silicon carbide substrate, A first conductivity type source region formed in the second conductivity type base layer, a trench reaching the first conductivity type high resistance drift layer from the first conductivity type source region, and a second conductivity type base layer. A semiconductor device having a surface protective film selectively formed on a part of a surface and a gate electrode for applying a voltage via a gate insulating film in the trench, wherein the gate insulating film is a first insulating film. And at least two layers of insulating films formed in the order of the second insulating film, the dielectric constant of the first insulating film is larger than the dielectric constant of silicon oxide, and the band gap of the second insulating film is Be larger than the band gap of the insulating film A semiconductor device characterized by the above-mentioned. 【請求項３】 前記表面保護膜が、第一の絶縁膜及び、
第二の絶縁膜の順に形成された少なくとも２層の絶縁膜
からなり、第一の絶縁膜の誘電率は酸化シリコンの誘電
率より大きく、第二の絶縁膜のバンドギャップは第一の
絶縁膜のバンドギャップより大きいことを特徴とする請
求項１又は２に記載の半導体装置。3. The method according to claim 1, wherein the surface protection film comprises: a first insulating film;
It is composed of at least two layers of insulating films formed in the order of the second insulating film, the dielectric constant of the first insulating film is larger than the dielectric constant of silicon oxide, and the band gap of the second insulating film is the first insulating film. 3. The semiconductor device according to claim 1, wherein the band gap is larger than the band gap. 【請求項４】 前記第一の絶縁膜と前記第二の絶縁膜
が、それぞれＡｌＮ，ＢＮ，Ｓｉ３Ｎ４，Ｔａ２Ｏ５，
ＴｉＯ２，Ａｌ２Ｏ３，ＢａＴｉＯ３の一群と、ＳｉＯ
２，Ａｌ２Ｏ３，Ｂ２Ｏ３，ダイヤモンド，ダイヤモン
ド・ライク炭素の一群より選択された１種類あるいは複
数種類から形成されていることを特徴とする請求項１〜
３のいずれか１項に記載の半導体装置。4. The method according to claim 1, wherein the first insulating film and the second insulating film are made of AlN, BN, Si3N4, Ta2O5,
A group of TiO2, Al2O3, BaTiO3 and SiO2
2, Al2O3, B2O3, diamond, diamond-like carbon, and one or more selected from the group.
4. The semiconductor device according to any one of 3. 【請求項５】 前記炭化珪素基板が、六方晶系炭化珪素
よりなることを特徴とする請求項１〜４のいずれか１項
に記載の半導体装置。5. The semiconductor device according to claim 1, wherein said silicon carbide substrate is made of hexagonal silicon carbide.
JP10273292A 1998-09-28 1998-09-28 Semiconductor device Pending JP2000106428A (en)

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