JP2000101101A - Sic schottky diode - Google Patents
Sic schottky diodeInfo
- Publication number
- JP2000101101A JP2000101101A JP10284780A JP28478098A JP2000101101A JP 2000101101 A JP2000101101 A JP 2000101101A JP 10284780 A JP10284780 A JP 10284780A JP 28478098 A JP28478098 A JP 28478098A JP 2000101101 A JP2000101101 A JP 2000101101A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- conductivity
- type
- sic
- schottky
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 230000004888 barrier function Effects 0.000 claims abstract description 28
- 230000002829 reductive effect Effects 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims description 22
- 230000015556 catabolic process Effects 0.000 claims description 9
- 230000002441 reversible effect Effects 0.000 abstract description 40
- 239000010410 layer Substances 0.000 description 83
- 230000005684 electric field Effects 0.000 description 12
- 230000000903 blocking effect Effects 0.000 description 8
- 238000002513 implantation Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 241001354791 Baliga Species 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000001994 activation Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＳｉＣショットキ
ーダイオードに係り、特に、高耐圧、大電流を制御する
ＳｉＣショットキーダイオードに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a SiC Schottky diode, and more particularly, to a SiC Schottky diode for controlling a high breakdown voltage and a large current.
【０００２】[0002]
【従来の技術】インバータ等の電力変換機器の動作周波
数の高周波化に伴って、半導体スイッチング素子の高速
化とともに、スイッチング素子に並列接続される還流ダ
イオードやフリーホイルダイオードの高速化が強く求め
られている。これらのダイオードには、高電圧かつ大電
流を低損失で整流する機能が要求されるので、一般には
ｐｎ接合ダイオードが広く適用されている。しかし、ｐ
ｎ接合ダイオードは、電流通電時に半導体内部に蓄積さ
れる少数キャリアによってターンオフ過渡時には大きな
逆電流が流れる性質があるため、スイッチング素子のタ
ーンオン時に過大な損失を発生させるだけでなく、過大
なノイズの発生源となっており、電力変換装置の動作の
高周波化を阻害する主要な要因になっている。このた
め、リカバリー特性の改善したｐｎ接合ダイオードが種
々開発されいるが、少数キャリアの注入を伴うこの種の
ダイオードには、リカバリー時の逆電流の低減に本質的
な限界がある。このような要求に応える整流ダイオード
としてショットキーダイオードがある。ショットキーダ
イオードでは、半導体内部で電流を運ぶ担体が多数キャ
リアのみであり、電流通電時においても少数キャリアの
注入や蓄積がないので、ターンオフ時の逆電流を極めて
小さくすることができる。しかし、シリコンを基材とす
る従来のショットキーダイオードは、電流導通時のオン
抵抗が高く、発生損失が著しく大きくなり、高電圧、大
電流の電力変換装置に適用できない、という問題があ
る。ＳｉＣを基材とすれば、この問題を解消できる。し
かしながら、ＳｉＣのショットキーダイオードでも逆電
圧を印加した時の漏れ電流が大きくなる性質がある。特
に、高温で耐電圧近くの高い電圧が印加されると、漏れ
電流が増加するので、逆電圧阻止状態における発生損失
が増大する。これがダイオード素子内の局所的な場所で
起こり、部分的な熱暴走によって素子が破壊し易い、と
いう欠点がある。2. Description of the Related Art As the operating frequency of power conversion devices such as inverters becomes higher, the speed of semiconductor switching elements and the speed of freewheeling diodes and freewheel diodes connected in parallel to switching elements are strongly required. I have. Since these diodes are required to have a function of rectifying a high voltage and a large current with low loss, a pn junction diode is generally widely used. But p
Since the n-junction diode has a property that a large reverse current flows during a turn-off transition due to minority carriers accumulated inside the semiconductor when a current flows, not only an excessive loss occurs when the switching element is turned on, but also an excessive noise occurs. It is a major factor that hinders the operation of the power converter from having a higher frequency. For this reason, various pn junction diodes with improved recovery characteristics have been developed, but this type of diode with minority carrier injection has an inherent limitation in reducing the reverse current during recovery. There is a Schottky diode as a rectifier diode meeting such a demand. In the Schottky diode, the carrier that carries the current inside the semiconductor is only the majority carrier, and the minority carrier is not injected or accumulated even when the current is supplied, so that the reverse current at the time of turn-off can be extremely reduced. However, the conventional Schottky diode using silicon as a base material has a problem that the on-resistance at the time of current conduction is high, the generation loss is extremely large, and it cannot be applied to a high-voltage, large-current power converter. This problem can be solved by using SiC as a base material. However, even a SiC Schottky diode has the property that the leakage current when a reverse voltage is applied increases. In particular, when a high voltage near the withstand voltage is applied at a high temperature, the leakage current increases, so that the generation loss in the reverse voltage blocking state increases. This has the disadvantage that it occurs locally in the diode element and the element is easily destroyed by partial thermal runaway.
【０００３】このようなショットキーダイオードの逆方
向の電圧印加時の漏れ電流を改善する従来技術として、
例えばＳｏｌｉｄ−Ｓｔａｔｅ Ｅｌｅｃｔｒｏｎｉｃ
ｓ，Ｖｏｌ．２８．Ｎｏ．１１，ｐｐ．１０８９−１０
９３（１９８５）の技術論文にＢ．Ｊ．Ｂａｌｉｇａ氏
によってＳｉを基材としたショットキーダイオードに適
用されたＪｕｎｃｔｉｏｎ−Ｂａｒｒｉｅｒ−Ｃｏｎｔ
ｒｏｌｌｅｄ Ｓｃｈｏｔｔｋｙ（ＪＢＳ） Ｒｅｃｔ
ｉｆｉｅｒという技術が開示されている。図２は、その
ショットキーダイオードの概略構成を示す断面図であ
る。図２において、１は高不純物濃度のｎ＋型層２と比
較的低不純物濃度のｎ−型層３とからなる半導体基体、
６はｎ型層２に低抵抗のオーム性接触したカソード電
極、５は比較的低不純物濃度のｎ型層３の表面にショッ
トキー障壁５１を形成するショットキー金属であって、
その表面終端部には局所電界を緩和するカードリング用
のｐ＋型層４が設けられると共に、ショットキー障壁部
分にはｐ＋型層８が複数個具備されている。このｐ＋型
層８は、逆電圧印加時に隣接するｐ＋型層のｐｎ接合か
らｎ−型層３に向かって拡がる空乏層が互いに重なる程
度の間隔で分散配置され、介在するショットキー障壁５
１に加わる逆電圧の電界強度を低減する作用があり、シ
ョットキー障壁部分における漏れ電流を減少させる働き
がある、と説明されている。この従来技術をＳｉＣを基
材にしたショットキーダイオードに適用すれば、逆電圧
阻止特性を格段に向上させ得ることが期待できる。As a conventional technique for improving the leakage current when a voltage is applied in the reverse direction to such a Schottky diode,
For example, Solid-State Electronic
s, Vol. 28. No. 11, pp. 1089-10
93 (1985). J. Junction-Barrier-Cont applied to a Si-based Schottky diode by Baliga
rolled Shottky (JBS) Rect
A technique called "ifier" is disclosed. FIG. 2 is a sectional view showing a schematic configuration of the Schottky diode. In FIG. 2, reference numeral 1 denotes a semiconductor substrate comprising an n + type layer 2 having a high impurity concentration and an n− type layer 3 having a relatively low impurity concentration;
Reference numeral 6 denotes a cathode electrode which is in ohmic contact with the n-type layer 2 having a low resistance, and 5 denotes a Schottky metal which forms a Schottky barrier 51 on the surface of the n-type layer 3 having a relatively low impurity concentration.
A p + -type layer 4 for card ring for relaxing a local electric field is provided at the surface terminal portion, and a plurality of p + -type layers 8 are provided at a Schottky barrier portion. The p + -type layers 8 are dispersedly arranged at intervals such that the depletion layers extending from the pn junction of the adjacent p + -type layers toward the n − -type layer 3 when a reverse voltage is applied overlap each other.
It is described that this has the function of reducing the electric field strength of the reverse voltage applied to 1 and the function of reducing the leakage current in the Schottky barrier portion. If this conventional technique is applied to a Schottky diode using SiC as a base material, it can be expected that the reverse voltage blocking characteristic can be significantly improved.
【０００４】しかしながら、以下に述べるＳｉＣ特有の
製作プロセス上の制限から、この構造をそのままＳｉＣ
のショットキーダイオードに適用するには多大な困難が
ある。すなわち、前記の従来例において、ｐ＋型層８
は、介在するショットキー障壁５１に加わる逆電圧の電
界強度を低減するために、逆電圧印加時に互いの空乏層
が重なる程度に間隔を狭くする必要があるとともに、数
１００〜数１０００Ｖの高い逆電圧に対して電圧阻止能
力を保持するために、比較的深い高濃度層として形成し
なければならない。しかし、ＳｉＣの場合、その接合絶
縁破壊電界がＳｉの約１０倍という物性上の特長を生か
した接合設計になるので、一般にｎ−型層３の不純物濃
度はＳｉの場合の７０〜１００倍の高濃度に設定され、
そのため空乏層の拡がりは著しく少なくなり、空乏層の
ピンチオフ効果を発揮するためには、前記のｐ＋型層８
の間隔は１μｍ程度の極めて狭い値にする必要がある。
この結果、電流導通時において電圧降下が著しく増大す
る、という問題が起こる。また、深いｐ型層の形成には
Ｓｉではボロンやアルミニウム等のアクセプタ不純物を
熱拡散法で拡散されるが、ＳｉＣではこれらの不純物の
拡散係数が極めて小さいので、この拡散法は適用でき
ず、イオン注入法を適用しなければならない。しかし、
イオン注入によって１μｍ以上の深い打ち込み層を選択
的に形成することは極めて難しい。厚い膜厚の注入マス
クの形成が困難なことに加えて、消去できない結晶欠陥
が誘起されるからである。したがって、漏れ電流が低減
できるＳｉでのＪＢＳ構造をＳｉＣのショットキーダイ
オードにそのままは適用することは殆ど不可能である。However, due to the limitations on the manufacturing process peculiar to SiC described below, this structure is directly used for SiC.
There is a great difficulty in applying this to Schottky diodes. That is, in the above conventional example, the p + type layer 8
In order to reduce the electric field strength of the reverse voltage applied to the intervening Schottky barrier 51, it is necessary to narrow the interval so that the depletion layers overlap each other when the reverse voltage is applied, and to increase the reverse voltage of several hundreds to several thousand volts. In order to maintain the voltage blocking ability with respect to the voltage, it must be formed as a relatively deep high concentration layer. However, in the case of SiC, the junction design takes advantage of the physical property that the junction breakdown electric field is about 10 times that of Si. Therefore, the impurity concentration of the n − -type layer 3 is generally 70 to 100 times that of Si. Set to high concentration,
Therefore, the expansion of the depletion layer is significantly reduced. In order to exhibit the depletion layer pinch-off effect, the p +
Is required to be a very narrow value of about 1 μm.
As a result, there arises a problem that the voltage drop significantly increases when the current is conducted. For forming a deep p-type layer, acceptor impurities such as boron and aluminum are diffused by thermal diffusion in Si. However, in SiC, since the diffusion coefficients of these impurities are extremely small, this diffusion method cannot be applied. Ion implantation must be applied. But,
It is extremely difficult to selectively form a deep implanted layer of 1 μm or more by ion implantation. This is because it is difficult to form an implantation mask having a large thickness, and crystal defects that cannot be erased are induced. Therefore, it is almost impossible to directly apply the JBS structure made of Si, which can reduce the leakage current, to a Schottky diode made of SiC.
【０００５】[0005]
【発明が解決しようとする課題】以上のように、高耐
圧、大電流のパワーショットキーダイオードには、高
温、高電圧における逆電圧時の漏れ電流の低減というシ
ョットキーダイオードの従来からの課題と、順方向の電
流導通時において電圧降下が著しく増大するという課題
を解決する必要がある。本発明の課題は、上記問題点に
鑑み、順方向の電流導通時の電圧降下の増大を伴うこと
なく、漏れ電流を低減して逆電圧阻止特性を著しく向上
させた高耐圧、大電流のＳｉＣショットキーダイオード
を提供することにある。As described above, the power Schottky diode with a high breakdown voltage and a large current has the conventional problem of the Schottky diode of reducing the leakage current at the time of reverse voltage at high temperature and high voltage. In addition, it is necessary to solve the problem that the voltage drop significantly increases during forward current conduction. SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a high-breakdown-voltage, large-current SiC which has a reduced leakage current and a remarkably improved reverse voltage blocking characteristic without increasing a voltage drop during forward current conduction. It is to provide a Schottky diode.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
に、ショットキー障壁が形成され、ＳｉＣ半導体基体の
表面近くの基体内に基体と反対導電型の埋込み層を複数
個分散配置する。さらに、該埋込み層とショットキー障
壁が形成される間に介在する半導体基体の不純物濃度を
低減する。In order to solve the above problems, a Schottky barrier is formed, and a plurality of buried layers of the opposite conductivity type to the substrate are dispersedly arranged in a substrate near the surface of the SiC semiconductor substrate. Further, the impurity concentration of the semiconductor substrate interposed between the formation of the buried layer and the Schottky barrier is reduced.
【０００７】本発明は、素子に逆電圧が印加されると、
半導体基体と埋込み層の間のｐｎ接合に印加される逆電
圧によって、そこに拡がる空乏層が重なり合い、ショッ
トキー障壁部分に印加される電界強度を緩和できる。こ
のとき、埋込み層間の空乏層は従来の表面層間より拡が
りやすいので、層間の間隔も幅広く設定できる。また、
埋込み層は実質的な深いｐｎ接合となり、高電圧に耐え
る阻止能力が可能になる。以上の作用により、順方向の
電流導通時の電圧降下の増大を伴うことなく、逆方向の
漏れ電流が低減された高耐圧のＳｉＣショットキーダイ
オードを実現することができる。さらに、ショットキー
障壁と埋込み層間に不純物濃度の低い層を介在させるこ
とによって、ショットキー障壁にかかる逆バイアス電界
をさらに低減できるので、漏れ電流の一層の低減と阻止
電圧の向上が可能になる。According to the present invention, when a reverse voltage is applied to the element,
Due to the reverse voltage applied to the pn junction between the semiconductor substrate and the buried layer, the depletion layers extending there overlap, and the electric field intensity applied to the Schottky barrier can be reduced. At this time, the depletion layer between the buried layers is easier to spread than the conventional surface layer, so that the distance between the layers can be set wider. Also,
The buried layer becomes a substantially deep pn junction, allowing blocking capability to withstand high voltages. By the above operation, a SiC Schottky diode with a high withstand voltage in which the leakage current in the reverse direction is reduced can be realized without increasing the voltage drop when the current flows in the forward direction. Further, by interposing a layer having a low impurity concentration between the Schottky barrier and the buried layer, the reverse bias electric field applied to the Schottky barrier can be further reduced, so that the leakage current can be further reduced and the blocking voltage can be improved.
【０００８】[0008]
【発明の実施の形態】以下、本発明の実施形態を図面を
用いて説明する。図１は、本発明の第一の実施形態であ
り、逆特性の改良された高耐圧のＳｉＣショットキーダ
イオードの断面図を示す。図１において、上下に主表面
を有する平行平板状のＳｉＣ半導体基体１は、不純物濃
度約３×１０の１９乗、厚さ約２００μｍの低抵抗のｎ
＋型層２と、不純物濃度約１×１０の１６乗、厚さ約１
２μｍの高抵抗のｎ−型層３とからなり、ｎ＋型層２が
露出する一方の主表面に低抵抗のオーム性接触したＮｉ
金属等のカソード電極６、ｎ−型層３が露出する他方の
主表面にはアノード電極となるＴｉ／Ａ１またはＰｔ等
のショットキー金属５をそれぞれ設け、ｎ−型層３とシ
ョットキー金属５との接する部分にはショットキー障壁
５１を形成する。ショットキー金属５が終端する部分に
は他方の主表面からｎ−型層３内にボロンのイオン注入
により形成された注入量約１×１０の１５乗／ｃｍ2、
深さ約０．５μｍの比較的高濃度のｐ＋型層４を設け、
その表面においてショットキー電極５と低抵抗にオーム
性接触する。そして、基体表面中央の主な機能領域とな
る部分において、他方の主表面から約１μｍの位置のｎ
−型層３内に高さ約０．５μｍ、幅約１μｍのボロン注
入により形成された比較的高濃度のｐ＋型埋込み層７を
約３μｍの間隔つまり幅広の間隔で複数個設け、それぞ
れｎ−型層３との間にｐｎ接合７１を形成する。図１に
は３ヶの埋込み層７を示したが、実際の素子では半導体
基体の大きさに応じて多数個配列する。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a high-breakdown-voltage SiC Schottky diode according to a first embodiment of the present invention, which has improved reverse characteristics. In FIG. 1, a parallel-plate-shaped SiC semiconductor substrate 1 having upper and lower main surfaces is a low-resistance n having an impurity concentration of about 3 × 10 19 and a thickness of about 200 μm.
+ Type layer 2, impurity concentration of about 1 × 10 16, thickness of about 1
A n-type layer 3 having a high resistance of 2 .mu.m, and a low resistance ohmic contact Ni contacting one main surface where the n + type layer 2 is exposed.
A Schottky metal 5 such as Ti / A1 or Pt serving as an anode electrode is provided on the other main surface where the cathode electrode 6 of metal or the like and the n− type layer 3 are exposed, respectively. A Schottky barrier 51 is formed in a portion in contact with. In the portion where the Schottky metal 5 terminates, an implantation amount of about 1 × 10 15 / cm 2 formed by boron ion implantation into the n − -type layer 3 from the other main surface,
A relatively high concentration p + type layer 4 having a depth of about 0.5 μm is provided,
On the surface thereof, the Schottky electrode 5 makes ohmic contact with low resistance. Then, in a portion to be a main functional area at the center of the substrate surface, n at a position of about 1 μm from the other main surface.
A plurality of relatively high-concentration p + type buried layers 7 formed by boron implantation having a height of about 0.5 μm and a width of about 1 μm are provided in the − type layer 3 at intervals of about 3 μm, that is, at a wide interval. A pn junction 71 is formed with the mold layer 3. FIG. 1 shows three buried layers 7, but in an actual device, many buried layers 7 are arranged according to the size of the semiconductor substrate.
【０００９】本実施形態における各部の作用を以下に説
明する。ダイオードとしての電流の整流作用は、ｎ−型
層３とショットキー金属５の間に形成されたショットキ
ー障壁５１の部分で動作する。すなわち、ショットキー
金属５がカソード電極６に対して正電位となる向きの電
圧が印加されたとき、ショットキー障壁５１の概ね０．
１〜０．５Ｖの比較的低い障壁を超えて電子がショット
キー金属５からｎ−型層３へ流れ、さらにカソード電極
６に向かって流れて導通する。また、上記と逆向きの電
圧が印加されたとき、電子の流れはショットキー障壁５
１によって塞き止められ、電流の流れを阻止する。ショ
ットキー金属５の終端部に設けたｐ＋型層４は、逆電圧
印加状態においてショットキー障壁５１にかかる局所集
中電界による降伏電圧の低下を防ぐもので、ｐ＋ｎ接合
の高い逆電圧阻止特性を利用している。この例では、通
常よく使われているいわゆるガードリング構造を示した
が、他の構造、例えばフィールドリミッティングリング
（ＦＬＲ）、フィールドプレート（ＦＰ）、またはジャ
ンクション・ターミネーション・エクステンション（Ｊ
ＴＥ）なども適用できる。The operation of each part in this embodiment will be described below. The rectifying action of the current as a diode operates in a portion of the Schottky barrier 51 formed between the n − -type layer 3 and the Schottky metal 5. That is, when a voltage in a direction in which the Schottky metal 5 has a positive potential with respect to the cathode electrode 6 is applied, the voltage of the Schottky barrier 51 becomes approximately 0.1.
Electrons flow from the Schottky metal 5 to the n − -type layer 3 beyond the relatively low barrier of 1 to 0.5 V, and further flow toward the cathode electrode 6 to conduct. When a voltage in the opposite direction is applied, the flow of electrons is reduced by the Schottky barrier 5.
1 to block the flow of current. The p + -type layer 4 provided at the end of the Schottky metal 5 prevents the breakdown voltage from decreasing due to the local concentrated electric field applied to the Schottky barrier 51 in the state where a reverse voltage is applied, and utilizes the high reverse voltage blocking characteristic of the p + n junction. are doing. In this example, a so-called guard ring structure that is commonly used is shown, but other structures such as a field limiting ring (FLR), a field plate (FP), or a junction termination extension (J) are used.
TE) can also be applied.
【００１０】本実施形態において、複数個のｐ＋型埋込
み層７が新規な点である。逆電圧印加時において、空乏
層ははじめショットキー障壁５１よりｎ−型層３内に拡
がるが、約１００Ｖの逆電圧においてこの空乏層はｐ＋
型埋込み層７に到達する。さらに高い逆電圧により、空
乏層はｐ＋型埋込み層７から拡がり、約４００Ｖの電圧
で隣り合ったｐ＋型埋込み層７から拡がる空乏層が重な
る。それ以上の逆電圧では空乏層はｎ−型層３内をｎ＋
型層２に向かって一様に拡がり、約１２００Ｖでその先
端はｎ＋型層２に到達し、素子はパンチスルーにより降
伏する。上記した逆電圧印加時の動作において、ショッ
トキー障壁５１にかかる逆方向の電界は、はじめ逆電圧
の増加とともに強くなるが、ｐ＋型埋込み層７から拡が
る空乏層が重なる電圧以上の逆電圧ではこの部分のピン
チオフ効果によって、さらに高い強度の電界にはならな
い。この作用によって高電圧印加時のショットキー障壁
部５１における漏れ電流の著しい増加を防止することが
できる。また、図２の従来例のｐ＋型層８の間隔が１μ
ｍ程度の極めて狭い値であるに比し、本実施形態では、
ｐ＋型埋込み層７を約３μｍの間隔つまり幅広の間隔で
分散配置するので、順方向の電流導通時の電圧降下の増
大を伴うことなく、逆に低くすることがでる。In this embodiment, a plurality of p + type buried layers 7 is a novel point. When a reverse voltage is applied, the depletion layer first expands into the n − -type layer 3 from the Schottky barrier 51, but at a reverse voltage of about 100 V, the depletion layer becomes p +
The mold buried layer 7 is reached. Due to the higher reverse voltage, the depletion layer spreads from the p + -type buried layer 7, and the depletion layer spreading from the adjacent p + -type buried layer 7 at a voltage of about 400 V overlaps. At a reverse voltage higher than that, the depletion layer becomes n + in the n− type layer 3.
It spreads uniformly toward the mold layer 2, and at about 1200 V, its tip reaches the n + type layer 2, and the element breaks down by punch-through. In the operation when the reverse voltage is applied, the electric field in the reverse direction applied to the Schottky barrier 51 initially increases as the reverse voltage increases. However, when the reverse voltage is higher than the voltage at which the depletion layer spreading from the p + -type buried layer 7 overlaps, the reverse electric field increases. Due to the pinch-off effect of the parts, no higher strength electric field is created. By this function, it is possible to prevent a remarkable increase in leakage current in Schottky barrier portion 51 when a high voltage is applied. Further, the interval between the p + type layers 8 of the conventional example shown in FIG.
In contrast to the extremely narrow value of about m, in the present embodiment,
Since the p + type buried layers 7 are dispersedly arranged at intervals of about 3 μm, that is, at wide intervals, the voltage can be lowered without increasing the voltage drop during forward current conduction.
【００１１】図３は、本発明の第二の実施形態であり、
図１の第一の実施形態のさらに逆電圧特性の改善された
ショットキーダイオードの断面図を示す。図中の各部に
付した構成部分の番号が図１に示した第一の実施形態と
同じ部分はその構造、導電型および作用が等しい部分を
指している。図３では、ｎ−型層３内に比較的高濃度の
ｐ＋型埋込み層７が複数個設けられる点は第一の実施形
態と同じであるが、さらに、該ｐ＋型埋込み層７より上
に不純物濃度が１〜３×１０の１５乗の高抵抗のｎ−−
型層３１をｎ−型層３との界面３１３で接して積層する
点が異なる。かかる構成にすれると、素子に逆電圧が印
加されたとき、ショットキー障壁５１より拡がる空乏層
がｐ＋型埋込み層７に到達する電圧は５０Ｖ以下に減少
し、ｐ＋型埋込み層７間のピンチオフ状態以降でもこの
電圧が保持される。その結果、ショットキー障壁５１に
かかる電界が低減されることになり、逆電圧印加時の漏
れ電流を著しく低減できる。FIG. 3 shows a second embodiment of the present invention.
FIG. 2 shows a cross-sectional view of a Schottky diode of the first embodiment of FIG. 1 with further improved reverse voltage characteristics. The same reference numerals as those in the first embodiment shown in FIG. 1 indicate the parts having the same structure, conductivity type and function. In FIG. 3, the point that a plurality of p + -type buried layers 7 having a relatively high concentration are provided in the n − -type layer 3 is the same as in the first embodiment, but is further provided above the p + -type buried layers 7. High resistance n−− with impurity concentration of 1 to 3 × 10 15
The difference is that the mold layer 31 is laminated in contact with the interface 313 with the n − -type layer 3. With this configuration, when a reverse voltage is applied to the element, the voltage at which the depletion layer extending from the Schottky barrier 51 reaches the p + -type buried layer 7 is reduced to 50 V or less, and the pinch-off between the p + -type buried layers 7 is reduced. This voltage is maintained even after the state. As a result, the electric field applied to the Schottky barrier 51 is reduced, and the leakage current when a reverse voltage is applied can be significantly reduced.
【００１２】本実施形態では、接合温度１５０℃におい
て、逆方向に１０００Ｖの電圧を印加したときの漏れ電
流密度が１×１０の−４乗Ａ／ｃｍ2程度に極めて低減
され、降伏電圧順が１２００Ｖと高く、かつ、順方向の
電流導通時の電圧降下が１００Ａ／ｃｍ2の電流密度に
おいて１．１〜１．２Ｖと極めて低いショットキーダイ
オードが得られる。したがって、本実施形態では導通特
性および逆電圧特性がともに優れた高耐圧、大電流のＳ
ｉＣショットキーダイオードを実現することができる。In this embodiment, at a junction temperature of 150 ° C., the leakage current density when a voltage of 1000 V is applied in the reverse direction is extremely reduced to about 1 × 10 −4 A / cm 2 , and the breakdown voltage order is reduced. A Schottky diode as high as 1200 V and having an extremely low voltage drop of 1.1 to 1.2 V at a current density of 100 A / cm 2 at the time of forward current conduction is obtained. Therefore, in this embodiment, a high breakdown voltage and a large current
An iC Schottky diode can be realized.
【００１３】図４は、図３のの第二の実施形態の製作方
法の主要な工程を示す。図中の各部に付した構成部分の
番号が図３に示した第二の実施形態と同じ部分はその構
造、導電型および作用が等しい部分を指している。図４
（ａ）は、ｎ−型層３の一方の主表面部分であり、下部
のｎ＋型層などの半導体基体の部分は省略されている。
図４（ｂ）では、ｎ−型層３の表面よりボロンの選択的
なイオン注入によりｐ＋型埋込み層７を部分的に形成す
る。注入量を約１×１０の１５乗／ｃｍ2とし、打ち込
みエネルギーを５０ｋｅＶ，３０ｋｅＶおよび１０ｋｅ
Ｖの３段階に注入して、ボックス状の不純物分布とした
後、約１５００℃のアニールを行い、活性化処理する。
続いて、図４（ｃ）では、エピタキシャル成長法により
窒素をドーパントとして濃度１〜３×１０の１５乗、厚
さ約１μｍのｎ−−型層３１を積層する。その後、図４
（ｄ）では、Ｔｉ／Ａ１のショットキー金属を表面に蒸
着してデバイスの機能領域を製作する。FIG. 4 shows the main steps of the manufacturing method of the second embodiment shown in FIG. The same reference numerals as in the second embodiment shown in FIG. 3 denote the same parts in the structure, conductivity type and function as those in the second embodiment shown in FIG. FIG.
(A) is one main surface portion of the n − -type layer 3 and a portion of the semiconductor substrate such as a lower n + -type layer is omitted.
In FIG. 4B, the p + -type buried layer 7 is partially formed by selective ion implantation of boron from the surface of the n − -type layer 3. The implantation amount is about 1 × 10 15 / cm 2 and the implantation energy is 50 keV, 30 keV and 10 keV.
V is implanted into three stages to form a box-shaped impurity distribution, and then annealing is performed at about 1500 ° C. to perform an activation process.
Subsequently, in FIG. 4C, an n − -type layer 31 having a concentration of 1 to 3 × 10 and a thickness of about 1 μm is stacked using nitrogen as a dopant by an epitaxial growth method. Then, FIG.
In (d), a functional region of the device is manufactured by depositing a Schottky metal of Ti / A1 on the surface.
【００１４】本発明の実施形態では、半導体基体１の導
電型をｎ型の場合を示したが、記述した伝導型を全て反
対伝導型にすれば、ｐ型の場合にも適用される。In the embodiment of the present invention, the case where the conductivity type of the semiconductor substrate 1 is n-type has been described. However, if all the described conductivity types are of the opposite conductivity type, the present invention can be applied to the case of p-type.
【００１５】[0015]
【発明の効果】以上説明したように、本発明によれば、
高耐圧、大電流のＳｉＣショットキーダイオードの逆方
向の漏れ電流特性を著しく向上させることができる。ま
た、ショットキー障壁と埋込み層間に不純物濃度の低い
層を介在させることによって、ショットキー障壁にかか
る逆バイアス電界をさらに低減することができ、漏れ電
流の一層の低減と阻止電圧の向上が可能になる。また、
順方向の電流導通時の電圧降下の増大を伴うことなく、
逆方向の漏れ電流を低減した導通特性および逆電圧特性
がともに優れた高耐圧、大電流のＳｉＣショットキーダ
イオードを実現することができる。As described above, according to the present invention,
The leakage current characteristics in the reverse direction of a SiC Schottky diode with a high breakdown voltage and a large current can be significantly improved. In addition, by interposing a low impurity concentration layer between the Schottky barrier and the buried layer, the reverse bias electric field applied to the Schottky barrier can be further reduced, thereby further reducing the leakage current and improving the blocking voltage. Become. Also,
Without increasing the voltage drop during forward current conduction,
It is possible to realize a SiC Schottky diode with a high breakdown voltage and a large current, which is excellent in both the conduction characteristics and the reverse voltage characteristics in which the leakage current in the reverse direction is reduced.
【図１】本発明の第一の実施形態であり、逆特性の改良
された高耐圧のＳｉＣショットキーダイオードの断面図FIG. 1 is a cross-sectional view of a high-breakdown-voltage SiC Schottky diode with improved reverse characteristics according to a first embodiment of the present invention.
【図２】従来例を示す断面図FIG. 2 is a sectional view showing a conventional example.
【図３】本発明の第二の実施形態を示す断面図FIG. 3 is a sectional view showing a second embodiment of the present invention.
【図４】本発明のショットキーダイオードの製作工程を
示す図FIG. 4 is a diagram showing a manufacturing process of the Schottky diode of the present invention.
１…ＳｉＣ半導体基体、２…ｎ＋型層、３…ｎ−型層、
３１…低濃度ｎ−−型層、３１３…ｎ−型層とｎ−−型
層の接合する界面、４…ガードリングとなるｐ＋型層、
５…アノード電極となるショットキー金属、５１…ショ
ットキー障壁、６…カソード電極、７…比較的高濃度ｐ
＋型層埋込み層、８…ｐ＋型層DESCRIPTION OF SYMBOLS 1 ... SiC semiconductor base, 2 ... n + type layer, 3 ... n- type layer,
31 ... low-concentration n- type layer, 313 ... interface joining n-type layer and n- type layer, 4 ... p + type layer serving as guard ring,
5: Schottky metal serving as anode electrode, 51: Schottky barrier, 6: cathode electrode, 7: relatively high concentration p
+ Type layer buried layer, 8 ... p + type layer
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大野 俊之 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 小野瀬 秀勝 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 浅野 勝則 大阪府大阪市北区中之島三丁目３番22号 関西電力株式会社内 (72)発明者 林 智基 大阪府大阪市北区中之島三丁目３番22号 関西電力株式会社内 (72)発明者 菅原 良孝 大阪府大阪市北区中之島三丁目３番22号 関西電力株式会社内 Ｆターム(参考） 4M104 AA03 CC03 FF31 FF35 GG18 HH20 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Toshiyuki Ohno 7-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd. Hitachi Research Laboratory, Ltd. (72) Inventor Hidekatsu Onose 7-1, Omikamachi, Hitachi City, Ibaraki Prefecture No. 1 Inside Hitachi, Ltd.Hitachi Research Laboratories (72) Katsunori Asano 3--22 Nakanoshima, Kita-ku, Osaka-shi, Osaka Prefecture Kansai Electric Power Co., Inc. (72) Tomoki Hayashi Nakanoshima, Kita-ku, Osaka, Osaka 3-2-2, Kansai Electric Power Co., Inc. (72) Inventor Yoshitaka Sugawara 3-2-2, Nakanoshima, Kita-ku, Osaka-shi, Osaka F-term in Kansai Electric Power Co., Inc. 4M104 AA03 CC03 FF31 FF35 GG18 HH20
Claims (4)
純物濃度および低不純物濃度の二つの半導体層が積層さ
れたＳｉＣ半導体基体と、前記基体の第一主表面に形成
され、前記第一導電型の低不純物濃度の半導体層との間
にショットキー障壁をなすショットキー金属と、前記基
体の第二主表面に形成され、前記第一導電型の高不純物
濃度の半導体層にオーム性抵抗接触されるカソード電極
からなるＳｉＣショットキーダイオードにおいて、前記
基体内の第一主表面に近い部分に前記第一導電型の低不
純物濃度の半導体層との間にｐｎ接合を形成する第二導
電型の埋込み層を複数個分散配置することを特徴とする
ＳｉＣショットキーダイオード。1. An SiC semiconductor substrate having a pair of main surfaces, on which two semiconductor layers of a first conductivity type having a high impurity concentration and a low impurity concentration are stacked, and formed on a first main surface of the substrate. A Schottky metal forming a Schottky barrier between the first conductive type low impurity concentration semiconductor layer and the first conductive type high impurity concentration semiconductor layer formed on the second main surface of the base; In a SiC Schottky diode comprising a cathode electrode in ohmic resistance contact, a pn junction is formed between the first conductive type low impurity concentration semiconductor layer and a portion near the first main surface in the base. An SiC Schottky diode, wherein a plurality of buried layers of two conductivity types are dispersedly arranged.
純物濃度および低不純物濃度の二つの半導体層が積層さ
れたＳｉＣ半導体基体と、前記基体の第一主表面に形成
され、前記第一導電型の低不純物濃度の半導体層との間
にショットキー障壁をなすショットキー金属と、前記基
体の第二主表面に形成され、前記第一導電型の高不純物
濃度の半導体層にオーム性抵抗接触されるカソード電極
からなるＳｉＣショットキーダイオードにおいて、前記
基体内の第一主表面に近い部分に前記第一導電型の低不
純物濃度の半導体層との間にｐｎ接合を形成する第二導
電型の埋込み層を複数個分散配置するとともに、前記第
一導電型の低不純物濃度の半導体層が前記埋込み層と前
記ショットキー障壁の間でさらに減じられた低不純物濃
度を有する領域を具備することを特徴とするＳｉＣショ
ットキーダイオード。2. An SiC semiconductor substrate having a pair of main surfaces, on which two semiconductor layers of a high conductivity concentration and a low impurity concentration of a first conductivity type are stacked, and formed on a first main surface of the substrate. A Schottky metal forming a Schottky barrier between the first conductive type low impurity concentration semiconductor layer and the first conductive type high impurity concentration semiconductor layer formed on the second main surface of the base; In a SiC Schottky diode comprising a cathode electrode in ohmic resistance contact, a pn junction is formed between the first conductive type low impurity concentration semiconductor layer and a portion near the first main surface in the base. A plurality of two-conductivity-type buried layers are dispersed and arranged, and the first-conductivity-type low-impurity-concentration semiconductor layer has a further reduced low-impurity-concentration region between the buried layer and the Schottky barrier. An SiC Schottky diode, comprising:
第二導電型の埋込み層を複数個分散配置する際、前記埋
込み層の間隔を幅広くして順方向の電流導通時の電圧降
下を低くすることを特徴とするＳｉＣショットキーダイ
オード。3. The buried layer of the second conductivity type according to claim 1, wherein a plurality of the buried layers of the second conductivity type are dispersed, so that the distance between the buried layers is widened to reduce a voltage drop during forward current conduction. A SiC Schottky diode.
て、カソード電極がショットキー金属に対して正電位と
なる向きの電圧が主電極間に印加されたとき、半導体素
子の降伏電圧より十分低い電圧において前記ショットキ
ー障壁より拡がる空乏層が前記第二導電型の埋込み層に
到達し、それ以上の電圧の印加によって該埋込み層の間
に拡がる空乏層が互いに重なるように設定されることを
特徴とするＳｉＣショットキーダイオード。4. The semiconductor device according to claim 1, wherein when a voltage having a direction in which the cathode electrode has a positive potential with respect to the Schottky metal is applied between the main electrodes, the voltage is sufficiently higher than the breakdown voltage of the semiconductor element. At a low voltage, a depletion layer extending from the Schottky barrier reaches the buried layer of the second conductivity type, and the depletion layers extending between the buried layers are set so as to overlap each other by applying a voltage higher than that. Characteristic SiC Schottky diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28478098A JP4088852B2 (en) | 1998-09-21 | 1998-09-21 | SiC Schottky diode |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28478098A JP4088852B2 (en) | 1998-09-21 | 1998-09-21 | SiC Schottky diode |
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| Publication Number | Publication Date |
|---|---|
| JP2000101101A true JP2000101101A (en) | 2000-04-07 |
| JP4088852B2 JP4088852B2 (en) | 2008-05-21 |
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ID=17682928
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28478098A Expired - Fee Related JP4088852B2 (en) | 1998-09-21 | 1998-09-21 | SiC Schottky diode |
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