JP2000100816A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2000100816A
JP2000100816A JP10265404A JP26540498A JP2000100816A JP 2000100816 A JP2000100816 A JP 2000100816A JP 10265404 A JP10265404 A JP 10265404A JP 26540498 A JP26540498 A JP 26540498A JP 2000100816 A JP2000100816 A JP 2000100816A
Authority
JP
Japan
Prior art keywords
film
bonding pad
semiconductor device
interlayer insulating
bpsg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10265404A
Other languages
Japanese (ja)
Inventor
Yasuki Sase
泰規 佐瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP10265404A priority Critical patent/JP2000100816A/en
Publication of JP2000100816A publication Critical patent/JP2000100816A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent defective adhesiveness between wiring and a BPSG interface, when a barrier metal containing Ti is used in a semiconductor device with the BPSG as an interlayer insulating film. SOLUTION: A semiconductor device includes a dioxide silicon film 3, as an interlayer insulating film, containing at least one kind of either phosphorous and boron. An interlayer insulating film 2 is removed at the position of a bonding pad, with a depth extending to the surface or the inside of a field oxide film 2 formed on a silicon substrate. A metal nitride film 7 and an aluminum film 5 are sequentially formed at the position of the bonding pad, and bonding pad is completed. Then, defective bonding can be prevented, while barrier characteristics of the contact is maintained.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置に関し、
特に半導体素子上のボンディングパッドの構造に関する
ものである。The present invention relates to a semiconductor device,
In particular, the present invention relates to a structure of a bonding pad on a semiconductor element.

【０００２】[0002]

【従来の技術】従来、シリコン基板の上に、例えばほう
素−りん・けい酸ガラス膜（ＢＰＳＧ膜：Ｂｏｒｏｎ−
ｄｏｐｅｄ Ｐｈｏｓｐｈｏ Ｓｉｌｉｃａｔｅ Ｇｌａ
ｓｓ膜）等の酸化シリコン系絶縁膜を形成してＡｌ系の
電極配線を設けるようにしたものでは、コンタクト部の
接合突き抜けや、Ｓｉ析出によるコンタクト抵抗の増大
などをまねくＡｌとＳｉの反応を抑制するために、絶縁
膜と電極配線の界面に拡散バリヤ層を設けることが行わ
れている。2. Description of the Related Art Conventionally, for example, a boron-phosphorus-silicate glass film (BPSG film: Boron-
doped Phospho Silicate Gla
In the case where an Al-based electrode wiring is provided by forming a silicon oxide-based insulating film such as an ss film, etc., the reaction between Al and Si, which leads to junction penetration of a contact portion and an increase in contact resistance due to Si deposition, is performed. In order to suppress this, a diffusion barrier layer is provided at the interface between the insulating film and the electrode wiring.

【０００３】すなわち、図２に概略の部分断面図を、ま
た図３に要部の拡大断面図を示すように、シリコン基板
１の上に形成したフィールド酸化膜２、及び層間絶縁膜
であるＢＰＳＧ膜３の上面に拡散バリヤ層としてバリヤ
メタル膜４が積層され、さらにこのバリヤメタル膜４の
上にＡｌ合金でなる電極配線５が設けられている。な
お、バリヤメタル膜４はＢＰＳＧ膜３側に設けられたＴ
ｉ膜６と、電極配線５側に設けられたＴｉＮ膜７とでな
る二重膜の構成を取っており、これには一般的にコンタ
クト抵抗を低減するための熱処理が加えられる。That is, as shown in a schematic partial sectional view of FIG. 2 and an enlarged sectional view of a main part of FIG. 3, a field oxide film 2 formed on a silicon substrate 1 and a BPSG which is an interlayer insulating film. A barrier metal film 4 is laminated on the upper surface of the film 3 as a diffusion barrier layer, and an electrode wiring 5 made of an Al alloy is provided on the barrier metal film 4. Note that the barrier metal film 4 is formed of T
It has a double-film structure consisting of the i-film 6 and the TiN film 7 provided on the electrode wiring 5 side, and is generally subjected to a heat treatment for reducing the contact resistance.

【０００４】また、電極配線５上には絶縁保護膜８が被
覆されており、この絶縁保護膜８の所定位置を開孔さ
せ、その中に露出するパッド開口部９に回路への給電、
あるいは信号の伝達等を行うためにリードワイヤ１０が
接続されている。この接続はパッド開口部９及びリード
ワイヤ１０に対して熱、圧力、振動などの外力が加えら
れ、両者の境界面に組成変形を与え、拡散接合によって
行われる。[0004] Further, an insulating protective film 8 is coated on the electrode wiring 5, a predetermined position of the insulating protective film 8 is opened, and power is supplied to a circuit through a pad opening 9 exposed therein.
Alternatively, a lead wire 10 is connected to perform signal transmission and the like. This connection is performed by applying an external force such as heat, pressure, or vibration to the pad opening 9 and the lead wire 10 to apply a composition deformation to a boundary surface between the two and to perform diffusion bonding.

【０００５】しかしながら上記の従来技術においては、
リードワイヤ１０を接合する際に、あるいは接合後にお
いて、パッド部９でＢＰＳＧ膜３とバリヤメタル膜４と
の界面近傍での剥離が発生する場合がある。[0005] However, in the above prior art,
At the time of joining the lead wires 10 or after the joining, peeling may occur in the pad portion 9 near the interface between the BPSG film 3 and the barrier metal film 4.

【０００６】このため、このような剥離の原因につて
は、特許公開H06314722に示されるように、ＢＰＳＧ膜
３の主部であるＳｉＯ2 のＯ（酸素）を、ＢＰＳＧ膜３
に密着するバリヤメタル膜４中のＴｉが吸い出し、Ｔｉ
Ｏ2 となって安定化するため、Ｔｉ膜６との界面近傍の
ＢＰＳＧ膜３内に図６中に模式的に示すように酸素の空
乏を有するＳｉリッチの脆弱領域１１が形成される。こ
の現象はバリアメタル層がＴｉ膜６とＴｉＮ膜７の２層
構造である場合のみならず、ＴｉＮ膜単層構造でも起こ
る場合がある。そして領域１１が外力が加わることで破
壊されることになり、ここから剥離が発生するからであ
る。[0006] For this reason, the cause of such separation is disclosed in Japanese Patent Application Laid-Open No. H06314722, in which O (oxygen) of SiO 2, which is the main part of the BPSG film 3, is replaced by the BPSG film 3.
Ti in the barrier metal film 4 that adheres to the substrate is sucked out, and Ti
As shown in FIG. 6, a Si-rich fragile region 11 having oxygen depletion is formed in the BPSG film 3 in the vicinity of the interface with the Ti film 6 for stabilization as O2. This phenomenon may occur not only when the barrier metal layer has a two-layer structure of the Ti film 6 and the TiN film 7 but also when the barrier metal layer has a single-layer structure of the TiN film. This is because the region 11 is destroyed by the application of an external force, and peeling occurs from this region.

【０００７】さらに、剥離がコンタクト抵抗を低減する
ために加えられるバリヤメタル膜４の熱処理、あるいは
後工程で行われる成膜時の熱処理など加熱され温度が上
昇することに影響されて生じ、熱処理温度が高いほど発
生する頻度が多くなるものであることが判明した。また
バリヤメタル膜４の下地層であるＢＰＳＧ膜３にドープ
されているＢやＰ等の不純物の含有量が大きいほど剥離
不良が発生する頻度が多くなるものであることも報告さ
れている。逆にＢやＰ等の不純物の含有量が小さいと剥
離不良は激減する。Further, the peeling is caused by an increase in the heating temperature, such as a heat treatment of the barrier metal film 4 added to reduce the contact resistance or a heat treatment at the time of film formation performed in a later step. It has been found that the higher the value, the more frequently it occurs. It is also reported that the larger the content of impurities such as B and P doped in the BPSG film 3, which is the base layer of the barrier metal film 4, the more frequently the occurrence of peeling failure occurs. Conversely, when the content of impurities such as B and P is small, the peeling failure is drastically reduced.

【０００８】また、特許公開H01037031によれば、 ＢＰ
ＳＧ膜３中の不純物、特にリン，ホウ素はＡｌ合金であ
る電極配線５の中への拡散が起こりやすく、この不純物
の影響による初期ボンディング性の低下あるいは金−Al
合金層の高温時の早期劣化、水分の侵入により酸類が発
生してAlを腐食させる耐食性不良現象などを引き起こす
とも言われている。According to Patent Publication H01037031, BP
Impurities in the SG film 3, particularly phosphorus and boron, are likely to diffuse into the electrode wiring 5 made of an Al alloy.
It is also said that the alloy layer deteriorates early at high temperatures at high temperatures, and the invasion of moisture causes acids to be generated, resulting in a poor corrosion resistance phenomenon that corrodes Al.

【０００９】[0009]

【発明が解決しようとする課題】上記のように基板面に
形成されたシリコン酸化膜等の絶縁膜上にバリアメタル
膜を直接介在させて電極配線を設けるようにした従来の
ものでは、絶縁膜とバリアメタル膜の密着性が十分であ
るとは言えず剥離する虞があった。このような状況に鑑
みて本発明はなされたもので、その目的とするところは
バリアメタル膜のコンタクト抵抗を低減したものとしな
がらも、絶縁膜上のバリアメタル膜の密着性を向上させ
ることができる信頼性の高い半導体装置を製造工程数増
加させることなく提供することにある。As described above, in a conventional device in which an electrode wiring is provided by directly interposing a barrier metal film on an insulating film such as a silicon oxide film formed on a substrate surface, as described above. And the barrier metal film cannot be said to have sufficient adhesion, and may be peeled off. The present invention has been made in view of such circumstances, and an object of the present invention is to improve the adhesion of a barrier metal film on an insulating film while reducing the contact resistance of the barrier metal film. It is to provide a highly reliable semiconductor device without increasing the number of manufacturing steps.

【００１０】[0010]

【課題を解決するための手段】このような目的を達成す
るために本発明は、リン，ホウ素のうち少なくとも１種
以上を含有する二酸化珪素膜を層間絶縁膜とする半導体
装置においては、ボンディングパッドの個所の箇所にシ
リコン基板上に形成されたフィールド酸化膜の表面もし
くは内部達する深さに上記の層間絶縁膜を除去し、前記
ボンディングパッドの個所に高融点金属及び金属ナイト
ライド膜から成るバリアメタル層およびアルミニウム膜
を順に形成してボンディングパッドとしたものである。According to the present invention, there is provided a semiconductor device having a silicon dioxide film containing at least one of phosphorus and boron as an interlayer insulating film. The above-mentioned interlayer insulating film is removed to a depth reaching the surface or the inside of the field oxide film formed on the silicon substrate at the location of the above, and a barrier metal comprising a high melting point metal and a metal nitride film is provided at the location of the bonding pad. A bonding pad is formed by sequentially forming a layer and an aluminum film.

【００１１】[0011]

【作用】本発明による半導体装置においては、バリアメ
タル層と下層の膜との密着力が上がり、またアルミニウ
ム膜中への不純物の拡散を抑制することができる。In the semiconductor device according to the present invention, the adhesion between the barrier metal layer and the underlying film is increased, and the diffusion of impurities into the aluminum film can be suppressed.

【００１２】[0012]

【発明の実施の形態】図１は本発明に係わる半導体装置
の一実施例のボンディングパッド部分を示す断面図であ
る。本実施例では、下層から順に、シリコン基板１上に
フィールド酸化膜２の上に、さらに層間絶縁膜であるＢ
ＰＳＧ膜３を形成する。そして、このＢＰＳＧ膜３のボ
ンディングパッド部分のみをエッチングにより除去して
開孔部5aを形成する。本実施例においてはこの開口部５
ａ形成はコンタクトホール形成と同時に行った。その
後、開孔部５aを含むＢＰＳＧ膜３上にコンタクト抵抗
低減のためにＴｉ膜７さらにその上にコンタクト部の接
合突き抜けや、Ｓｉ析出によるコンタクト抵抗の増大な
どをまねくＡｌとＳｉの反応を抑制するためにＴｉＮ膜
８をバリアメタル層として被着した後、コンタクト抵抗
を低減させるべくH2雰囲気中で摂氏500〜700度のアニー
ルを行った後に、Ａｌ膜５を被着する。次いで、Ｔｉ膜
６、ＴｉＮ膜７とＡｌ膜５を所定形状にパターニングし
た後、その上に絶縁保護膜９を被着して、この膜のボン
ディングパッドとなる部分を開孔させて開孔部９aを形
成させることにより、図１に示すように、Ａｌ膜８の周
囲部を絶縁保護膜にて被覆せしめて、このAl膜８をボン
ディングパッドとして構成したものである。FIG. 1 is a sectional view showing a bonding pad portion of an embodiment of a semiconductor device according to the present invention. In the present embodiment, in order from the lower layer, on the field oxide film 2 on the silicon substrate 1 and further on the interlayer insulating film B
The PSG film 3 is formed. Then, only the bonding pad portion of the BPSG film 3 is removed by etching to form an opening 5a. In this embodiment, the opening 5
The formation of a was performed simultaneously with the formation of the contact hole. Thereafter, on the BPSG film 3 including the opening 5a, a Ti film 7 is formed on the BPSG film 3 in order to reduce the contact resistance. Further, a reaction between Al and Si, which causes a contact penetration through the contact portion and an increase in contact resistance due to Si deposition, is suppressed. After the TiN film 8 is deposited as a barrier metal layer to perform the annealing, annealing is performed at 500 to 700 degrees Celsius in an H2 atmosphere to reduce the contact resistance, and then the Al film 5 is deposited. Next, after patterning the Ti film 6, the TiN film 7 and the Al film 5 into a predetermined shape, an insulating protective film 9 is deposited thereon, and a portion of the film serving as a bonding pad is opened to form an opening. By forming 9a, as shown in FIG. 1, the periphery of the Al film 8 is covered with an insulating protective film, and this Al film 8 is configured as a bonding pad.

【００１３】このように、上記実施例によると、ボンデ
ィングパッド領域ではＴｉ膜６の直下にはＢＰＳＧ膜３
が存在しないようにしたので、Ｔｉ膜６とBPSG膜３との
接触する部分がなくなり、そのためにボンディングパッ
ドを形成する金属部分とその下地の密着力が上がり、ま
たバリアメタル層の効果によりＡｌ膜８中への不純物の
拡散を抑制できる。これによって、Ｔｉ膜６とＢＰＳＧ
膜３との密着力の低さを密着力の高いＴｉ膜６と熱酸化
膜であるフィールド酸化膜２との接合に変えてボンディ
ング初期のはく離をなくし、またＢＰＳＧ膜３中の不純
物（特にリン，ホウ素）による初期ボンディング性の低
下を防止できるとともに、膜の界面を通じて侵入した水
とリン，ホウ素との反応を抑制することができる。さら
に、ボンディングパッド部分の金−Al合金層に悪影響を
およぼすリンの拡散を抑えることができる。従ってこの
ような効果により長期的信頼性の向上を図ることができ
る。As described above, according to the above-described embodiment, the BPSG film 3 is formed immediately below the Ti film 6 in the bonding pad region.
Is eliminated, so that there is no portion where the Ti film 6 and the BPSG film 3 are in contact with each other, thereby increasing the adhesion between the metal portion forming the bonding pad and the base, and the effect of the barrier metal layer on the Al film. 8 can be suppressed from diffusing. Thereby, the Ti film 6 and the BPSG
The low adhesive strength with the film 3 is changed to the bonding between the Ti film 6 having high adhesive strength and the field oxide film 2 which is a thermal oxide film to prevent the initial peeling of the bonding, and the impurities (particularly phosphorus) in the BPSG film 3 are removed. , Boron), it is possible to prevent a decrease in the initial bonding property and to suppress the reaction between water and phosphorus and boron that have invaded through the interface of the film. Further, the diffusion of phosphorus which adversely affects the gold-Al alloy layer in the bonding pad portion can be suppressed. Therefore, the long-term reliability can be improved by such an effect.

【００１４】[0014]

【発明の効果】以上説明したように本発明は、ボンディ
ングパッドをバリアメタル層およびアルミニウム膜の下
にリン及びホウ素を含む二酸化珪素膜が存在しない構造
としたことにより、バリアメタル層と下層の膜との密着
力が上がり、またアルミニウム膜中への不純物の拡散を
抑制できるので、ボンディング性の向上が計れると共に
金−アルミニウム接合部の早期劣化を防止できる効果が
ある。これによって、半導体素子の長期信頼性を確保す
ることが可能となる。As described above, according to the present invention, the bonding pad has a structure in which the silicon dioxide film containing phosphorus and boron does not exist under the barrier metal layer and the aluminum film. And the diffusion of impurities into the aluminum film can be suppressed, so that the bonding properties can be improved and the gold-aluminum junction can be prevented from being deteriorated early. This makes it possible to ensure long-term reliability of the semiconductor element.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明に係わる半導体装置の一実施例のボンデ
ィングパッド部分を示す断面図。FIG. 1 is a sectional view showing a bonding pad portion of an embodiment of a semiconductor device according to the present invention.

【図２】従来の半導体装置のボンディングパッド部分を
示す断面図。FIG. 2 is a sectional view showing a bonding pad portion of a conventional semiconductor device.

【図３】図２の一部を拡大した図。FIG. 3 is an enlarged view of a part of FIG. 2;

【符号の説明】[Explanation of symbols]

１…シリコン基板 ２…フィールド酸化膜 ３…ＢＰＳＧ膜 ４…バリアメタル膜 ５…ＡＬ膜 ５ａ…開口部 ６…Ｔｉ膜 ７…ＴｉＮ膜 ８…パッシベーション絶縁保護膜 ９…パッド開口部 １０…リードワイヤー １１…脆弱層 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Field oxide film 3 ... BPSG film 4 ... Barrier metal film 5 ... AL film 5a ... Opening 6 ... Ti film 7 ... TiN film 8 ... Passivation insulating protective film 9 ... Pad opening 10 ... Lead wire 11 … Vulnerable layer

───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 4M104 AA01 BB14 DD19 FF13 HH04 HH09 HH20 5F033 HH08 HH18 HH33 MM08 MM13 QQ09 QQ73 RR15 VV07 XX14 XX18 XX28 XX29 5F044 EE04 EE06 EE08 EE12 5F058 BC02 BC04 BJ02 BJ05  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA01 BB14 DD19 FF13 HH04 HH09 HH20 5F033 HH08 HH18 HH33 MM08 MM13 QQ09 QQ73 RR15 VV07 XX14 XX18 XX28 XX29 5F044 EE04 EE06 EE08 EE02 B05B58

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】リン，ホウ素のうち少なくとも１種以上を
含有する二酸化珪素膜を層間絶縁膜とする半導体装置に
おいて、ボンディングパッドの箇所にシリコン基板上に
形成されたフィールド酸化膜の表面もしくは内部達する
深さに上記の層間絶縁膜を除去し、前記ボンディングパ
ッドの個所に金属ナイトライド膜およびアルミニウム膜
を順に形成してボンディングパッドしたことを特徴とす
る半導体装置。In a semiconductor device using a silicon dioxide film containing at least one of phosphorus and boron as an interlayer insulating film, a surface of a field oxide film formed on a silicon substrate reaches or reaches a bonding pad. A semiconductor device, wherein the interlayer insulating film is removed to a depth, and a metal nitride film and an aluminum film are sequentially formed at a position of the bonding pad to form a bonding pad. 【請求項２】前記金属ナイトライドの下層に高融点金属
層を形成してあることを特徴とする請求項１記載の半導
体装置。2. The semiconductor device according to claim 1, wherein a high melting point metal layer is formed below said metal nitride.
JP10265404A 1998-09-18 1998-09-18 Semiconductor device Withdrawn JP2000100816A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10265404A JP2000100816A (en) 1998-09-18 1998-09-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10265404A JP2000100816A (en) 1998-09-18 1998-09-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2000100816A true JP2000100816A (en) 2000-04-07

Family

ID=17416705

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10265404A Withdrawn JP2000100816A (en) 1998-09-18 1998-09-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2000100816A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6723628B2 (en) 2000-03-27 2004-04-20 Seiko Epson Corporation Method for forming bonding pad structures in semiconductor devices
US6812123B2 (en) 2000-03-27 2004-11-02 Seiko Epson Corporation Semiconductor devices and methods for manufacturing the same
JP2005026691A (en) * 2003-07-01 2005-01-27 Stmicroelectronics Inc System and method for increasing strength of bond formed with small-diameter wire in ball bonding
US7679191B2 (en) * 2005-07-13 2010-03-16 Nec Electronics Corporation Polysilicon film with increased roughness
EP3182443A4 (en) * 2014-08-11 2017-08-23 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device
US10217832B2 (en) 2016-10-12 2019-02-26 Fuji Electric Co., Ltd. Semiconductor device
US10217859B2 (en) 2016-10-12 2019-02-26 Fuji Electric Co., Ltd. Semiconductor device
US10418336B2 (en) 2017-03-14 2019-09-17 Fuji Electric Co., Ltd. Manufacturing method of semiconductor device and semiconductor device
US11594502B2 (en) 2017-07-13 2023-02-28 Fuji Electric Co., Ltd. Semiconductor device having conductive film
CN115831911A (en) * 2022-12-16 2023-03-21 上海功成半导体科技有限公司 Pad structure and electronic device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6723628B2 (en) 2000-03-27 2004-04-20 Seiko Epson Corporation Method for forming bonding pad structures in semiconductor devices
US6812123B2 (en) 2000-03-27 2004-11-02 Seiko Epson Corporation Semiconductor devices and methods for manufacturing the same
JP2005026691A (en) * 2003-07-01 2005-01-27 Stmicroelectronics Inc System and method for increasing strength of bond formed with small-diameter wire in ball bonding
US7679191B2 (en) * 2005-07-13 2010-03-16 Nec Electronics Corporation Polysilicon film with increased roughness
EP3182443A4 (en) * 2014-08-11 2017-08-23 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device
US10217832B2 (en) 2016-10-12 2019-02-26 Fuji Electric Co., Ltd. Semiconductor device
US10217859B2 (en) 2016-10-12 2019-02-26 Fuji Electric Co., Ltd. Semiconductor device
US10418336B2 (en) 2017-03-14 2019-09-17 Fuji Electric Co., Ltd. Manufacturing method of semiconductor device and semiconductor device
US11594502B2 (en) 2017-07-13 2023-02-28 Fuji Electric Co., Ltd. Semiconductor device having conductive film
CN115831911A (en) * 2022-12-16 2023-03-21 上海功成半导体科技有限公司 Pad structure and electronic device
CN115831911B (en) * 2022-12-16 2023-10-27 上海功成半导体科技有限公司 Bonding pad structure and electronic device

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