JP2000100779A - Semiconductor manufacturing device - Google Patents
Semiconductor manufacturing deviceInfo
- Publication number
- JP2000100779A JP2000100779A JP10263729A JP26372998A JP2000100779A JP 2000100779 A JP2000100779 A JP 2000100779A JP 10263729 A JP10263729 A JP 10263729A JP 26372998 A JP26372998 A JP 26372998A JP 2000100779 A JP2000100779 A JP 2000100779A
- Authority
- JP
- Japan
- Prior art keywords
- chamber
- wall
- wafer
- semiconductor manufacturing
- comb
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、チャンバーに櫛型
電極を有する半導体製造装置に関する。The present invention relates to a semiconductor manufacturing apparatus having a comb-shaped electrode in a chamber.
【０００２】[0002]
【従来の技術】図１は従来の櫛型電極を有する半導体製
造装置の構成を横から見た図である。図において１は石
英チャンバー、２は薄膜除去プロセスのためのガス取り
入れ口、３はチャンバー１に装着された櫛型電極、４は
ウェハー、５はウェハーステージである。次にこの装置
の動作について説明する。チャンバー１内にガス取り入
れ口２よりプロセスガスが供給され、櫛型電極３の間に
ＲＦ電圧を印加することによりプラズマ放電を生じさ
せ、ウェハー４表面の薄膜の除去を行う。2. Description of the Related Art FIG. 1 is a side view of the structure of a conventional semiconductor manufacturing apparatus having comb electrodes. In the figure, 1 is a quartz chamber, 2 is a gas inlet for a thin film removal process, 3 is a comb-shaped electrode mounted in the chamber 1, 4 is a wafer, and 5 is a wafer stage. Next, the operation of this device will be described. A process gas is supplied into the chamber 1 from a gas inlet 2, and a plasma discharge is generated by applying an RF voltage between the comb-shaped electrodes 3 to remove a thin film on the surface of the wafer 4.
【０００３】[0003]
【発明が解決しようとする課題】上記のような構成の半
導体製造装置において処理を行うと、チャンバー１の内
壁の電極間６において、チャンバー１の構成素材である
石英もしくはプロセスによりチャンバー１内壁に付着し
た反応成生物が、プラズマによりダメージをうけ剥離す
る。結果的にそれら剥離した小片がウェハー４上に異物
として落下・付着し、半導体のパターン形成に悪影響を
及ぼしていた。この発明は上記のような問題点を解消す
るためになされたもので、チャンバー内壁へのダメージ
を軽減し、ウェハーへの異物付着を防止することを目的
とする。When processing is performed in the semiconductor manufacturing apparatus having the above-described structure, the material adheres to the inner wall of the chamber 1 between the electrodes 6 on the inner wall of the chamber 1 by quartz or a process, which is a constituent material of the chamber 1. The resulting reaction product is damaged by the plasma and peels off. As a result, the separated small pieces fall and adhere as foreign matter on the wafer 4, which adversely affects the pattern formation of the semiconductor. The present invention has been made to solve the above problems, and has as its object to reduce damage to an inner wall of a chamber and prevent foreign matter from adhering to a wafer.
【０００４】[0004]
【課題を解決するための手段】この発明は、電極間の距
離を広くとることによりチャンバー内壁へのプラズマに
よるダメージを軽減することで、ウェハーへの異物落下
を防止するものである。SUMMARY OF THE INVENTION The present invention is to prevent foreign matter from falling onto a wafer by reducing the damage of the inner wall of the chamber due to plasma by increasing the distance between the electrodes.
【０００５】[0005]
【作用】この発明においては、チャンバー内壁へのプラ
ズマダメージが軽減され、チャンバーの構成素材および
チャンバー内壁に付着した反応成生物の剥離を防止する
ことが出来るため、ウェハーへの異物付着を抑えること
が出来る。According to the present invention, plasma damage to the inner wall of the chamber is reduced, and the constituent materials of the chamber and reaction products adhered to the inner wall of the chamber can be prevented from peeling off. I can do it.
【０００６】[0006]
【発明の実施の形態】本発明の櫛型電極を有する半導体
製造装置の一実施例として、レジスト除去工程に用いら
れる枚葉式アッシング装置を例にとり説明する。図２は
櫛型電極を有する枚葉式アッシング装置を横から見た構
成図を示したものである。図において、１は石英チャン
バー、２は薄膜除去プロセスのためのガス取り入れ口、
３はチャンバー１に装着されたアルミから成る櫛型電
極、４はシリコンウェハー、５はウェハーステージであ
る。ガス取り入れ口２からプロセスガスであるＯ２を供
給し、櫛型電極３に出力８００ＷのＲＦ電圧を印加する
ことでプラズマを生じさせる。この際、櫛型電極３の電
極間距離を従来の１０ｍｍよりも大きくすることで、チ
ャンバー１内壁へのプラズマダメージを低減することが
出来る。電極間を大きく取るほどプラズマによるチャン
バー内壁へのダメージは小さくなるが、同時にウェハー
４上のレジストのアッシングレートが低下することを考
慮に入れ、電極間の距離は１１ｍｍ〜２５ｍｍ程度と
し、更に好ましくは１４ｍｍ〜１６ｍｍとする。本実施
例では電極間距離を１５ｍｍとすることにより、チャン
バー内壁からの異物発生を防止している。DESCRIPTION OF THE PREFERRED EMBODIMENTS As an embodiment of a semiconductor manufacturing apparatus having a comb-shaped electrode according to the present invention, a single-wafer ashing apparatus used in a resist removing step will be described as an example. FIG. 2 is a diagram showing the configuration of a single-wafer ashing apparatus having comb-shaped electrodes as viewed from the side. In the figure, 1 is a quartz chamber, 2 is a gas inlet for a thin film removal process,
Reference numeral 3 denotes a comb-shaped electrode made of aluminum mounted in the chamber 1, 4 denotes a silicon wafer, and 5 denotes a wafer stage. O2, which is a process gas, is supplied from the gas inlet 2 and an RF voltage having an output of 800 W is applied to the comb electrode 3 to generate plasma. At this time, plasma damage to the inner wall of the chamber 1 can be reduced by making the inter-electrode distance of the comb-shaped electrode 3 larger than the conventional distance of 10 mm. The larger the distance between the electrodes, the smaller the damage to the inner wall of the chamber due to the plasma. 14 mm to 16 mm. In the present embodiment, by setting the distance between the electrodes to 15 mm, the generation of foreign matter from the inner wall of the chamber is prevented.
【０００７】[0007]
【発明の効果】以上の様に、本発明の半導体製造装置に
よれば、櫛型電極の電極間距離を大きくすることでチャ
ンバー内壁へのプラズマダメージを軽減し、ウェハーへ
の異物付着を抑えるという効果がある。As described above, according to the semiconductor manufacturing apparatus of the present invention, plasma damage to the inner wall of the chamber is reduced by increasing the inter-electrode distance between the comb-shaped electrodes, and foreign matter adhesion to the wafer is suppressed. effective.
【図１】従来の半導体装置を横から見た構成図。FIG. 1 is a configuration diagram of a conventional semiconductor device as viewed from the side.
【図２】本発明の実施例による半導体製造装置を横から
見た構成図。FIG. 2 is a side view showing a configuration of a semiconductor manufacturing apparatus according to an embodiment of the present invention.
１ 石英チャンバー ２ ガス取り入れ口 ３ 櫛型電極 ４ ウェハー ５ ウェハーステージ ６ プラズマによるチャンバー内壁へのダメージが著し
い部分DESCRIPTION OF SYMBOLS 1 Quartz chamber 2 Gas intake 3 Comb electrode 4 Wafer 5 Wafer stage 6 Part where plasma inner wall is significantly damaged
Claims (2)
を有する半導体製造装置において、電極間隔を広くする
ことを特徴とする半導体製造装置。1. A semiconductor manufacturing apparatus having a comb-shaped electrode for plasma discharge in a processing chamber, wherein an electrode interval is widened.
２５ｍｍにすることを特徴とする半導体製造装置。2. The method according to claim 1, wherein the distance between the electrodes is 11 mm or more.
A semiconductor manufacturing apparatus having a thickness of 25 mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10263729A JP2000100779A (en) | 1998-09-17 | 1998-09-17 | Semiconductor manufacturing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10263729A JP2000100779A (en) | 1998-09-17 | 1998-09-17 | Semiconductor manufacturing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000100779A true JP2000100779A (en) | 2000-04-07 |
Family
ID=17393500
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10263729A Withdrawn JP2000100779A (en) | 1998-09-17 | 1998-09-17 | Semiconductor manufacturing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000100779A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090255630A1 (en) * | 2005-04-28 | 2009-10-15 | Hitachi Kokusai Electric Inc. | Substrate processing apparatus and electrode member |
-
1998
- 1998-09-17 JP JP10263729A patent/JP2000100779A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090255630A1 (en) * | 2005-04-28 | 2009-10-15 | Hitachi Kokusai Electric Inc. | Substrate processing apparatus and electrode member |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20060110 |