JP2000058642A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
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- JP2000058642A JP2000058642A JP10223867A JP22386798A JP2000058642A JP 2000058642 A JP2000058642 A JP 2000058642A JP 10223867 A JP10223867 A JP 10223867A JP 22386798 A JP22386798 A JP 22386798A JP 2000058642 A JP2000058642 A JP 2000058642A
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- JP
- Japan
- Prior art keywords
- insulating film
- interlayer insulating
- connection hole
- layer
- filling material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置の製造
方法に係わり、特に、メチル基を含む有機ＳＯＧを層間
絶縁膜に用いた電極配線の形成方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an electrode wiring using an organic SOG containing a methyl group as an interlayer insulating film.
【０００２】[0002]
【従来の技術】集積回路の高密度化が進み、また高速化
が要求されるに伴い、最近では集積回路での配線容量の
抑制が大きな課題となっている。そのため、配線間の層
間絶縁膜としては、誘電率４．０〜４．５程度のシリコ
ン酸化膜（ＳｉＯ2）に比べて低い誘電率２．８程度の
メチル基を含む有機ＳＯＧ膜が利用されるようになって
きた。次に、従来の電極配線の形成方法を図２により説
明する。図２は、電極配線の形成工程を示す概略工程断
面図である。2. Description of the Related Art As the density of integrated circuits has increased and the speed of the integrated circuits has increased, it has recently become a major issue to suppress the wiring capacitance in the integrated circuits. For this reason, an organic SOG film containing a methyl group having a dielectric constant of about 2.8 lower than a silicon oxide film (SiO 2 ) having a dielectric constant of about 4.0 to 4.5 is used as an interlayer insulating film between the wirings. It has become. Next, a conventional method for forming an electrode wiring will be described with reference to FIG. FIG. 2 is a schematic process cross-sectional view showing a process of forming an electrode wiring.
【０００３】先ず、図２（ａ）に示すように、拡散層や
電極金属等の導電層２２を有する半導体基板２１上に、
メチル基を含む有機ＳＯＧ膜（層間絶縁膜）２３を形成
する。 次に、図２（ｂ）に示すように、後述する酸素
ガスを含むプラズマを用いてレジストマスクを剥離する
際、層間絶縁膜の変質を防止するために、酸素を反応ガ
スとする反応性イオンエッチングにより、前記層間絶縁
膜２３の表面よりメチル基を除去し、酸化層からなる改
質層２４を形成する。First, as shown in FIG. 2A, a semiconductor substrate 21 having a conductive layer 22 such as a diffusion layer or an electrode metal is placed on a semiconductor substrate 21.
An organic SOG film (interlayer insulating film) 23 containing a methyl group is formed. Next, as shown in FIG. 2B, when the resist mask is stripped using a plasma containing an oxygen gas, which will be described later, reactive ions using oxygen as a reactive gas are used in order to prevent deterioration of the interlayer insulating film. By etching, methyl groups are removed from the surface of the interlayer insulating film 23 to form a modified layer 24 made of an oxide layer.
【０００４】次に、図２（ｃ）に示すように、前記改質
層２４上にレジスト膜を塗布し、電子ビーム露光によ
り、レジストパターンを露光、 現像し、前記改質層２４
に対応する位置に開口を有するレジストマスク２５を形
成する。[0004] Next, as shown in FIG. 2 (c), a resist film is applied on the modified layer 24, and a resist pattern is exposed and developed by electron beam exposure.
A resist mask 25 having an opening at a position corresponding to is formed.
【０００５】次に、図２（ｄ）に示すように、前記レジ
ストマスク２５をマスクとして、オクタフルオロシクロ
ブタン（Ｃ4Ｆ8），一酸化炭素（ＣＯ），アルゴン（Ａ
ｒ），酸素（Ｏ2）の混合ガスを反応ガスとする反応性
イオンエッチングにより、前記改質層２４及び前記層間
絶縁膜２３をエッチングし、前記導電層２２に達する接
続孔２６を形成する。その後、図２（ｅ）に示すよう
に、前記レジストマスク２５を、酸素を含むプラズマを
用いて剥離する。Next, as shown in FIG. 2D, using the resist mask 25 as a mask, octafluorocyclobutane (C 4 F 8 ), carbon monoxide (CO), and argon (A) are used.
The modified layer 24 and the interlayer insulating film 23 are etched by reactive ion etching using a mixed gas of r) and oxygen (O 2 ) as a reaction gas, and a connection hole 26 reaching the conductive layer 22 is formed. Thereafter, as shown in FIG. 2E, the resist mask 25 is peeled off using a plasma containing oxygen.
【０００６】しかる後、図２（ｆ）に示すように、前記
接続孔２６内にＡｌ等の金属膜２７を埋め込む。この
後、必要に応じ上層配線としての金属配線を形成する。After that, as shown in FIG. 2F, a metal film 27 of Al or the like is buried in the connection hole 26. Thereafter, a metal wiring as an upper layer wiring is formed as necessary.
【０００７】しかしながら、従来の電極配線の形成方法
では、レジストマスクの剥離工程において、前記接続孔
内の前記層間絶縁膜が酸素雰囲気中に晒されるため、層
間絶縁膜中に含まれるメチル基が酸化され、吸湿性膜に
変質する。この層間絶縁膜の吸湿性膜への変質により、
金属配線が腐蝕し配線の信頼性を低下させる。また、層
間絶縁膜中に含まれるメチル基が酸化されることにより
誘電率が高くなり、配線容量の増加を招く等の問題があ
る。この層間絶縁膜の変質を防ぐために、接続孔内の側
壁に酸素プラズマによる改質処理を施し、酸化膜からな
る改質層を形成する方法が、例えば、Ｔ．Ｆｕｒｕｓａ
ｗａ ａｎｄ Ｙ．Ｈｏｍｍａ：Ｅｘｔｅｎｄｅｄ Ａ
ｂｓｔｒａｃｔｓ ｏｆ １ｍｔ．Ｃｏｎｆ．ｏｎ Ｓ
ｏｌｉｄ Ｓｔａｔｅ Ｄｅｖｉｃｅｓ ａｎｄ Ｍａ
ｔｅｒｔａｌｓ、ｐｐ．１４５（１９９６）に報告され
ている。However, in the conventional method for forming an electrode wiring, in the step of stripping the resist mask, the interlayer insulating film in the connection hole is exposed to an oxygen atmosphere, so that methyl groups contained in the interlayer insulating film are oxidized. And is transformed into a hygroscopic film. Due to the change of the interlayer insulating film into a hygroscopic film,
The metal wiring corrodes and lowers the reliability of the wiring. In addition, the oxidation of the methyl group contained in the interlayer insulating film increases the dielectric constant, which causes a problem such as an increase in wiring capacitance. In order to prevent the deterioration of the interlayer insulating film, a method of forming a modified layer composed of an oxide film by performing a reforming process using oxygen plasma on a side wall in the connection hole is disclosed in, for example, T.I. Furusa
wa and Y. Homma: Extended A
bracts of 1mt. Conf. on S
olid State Devices and Ma
tertals, pp. 145 (1996).
【０００８】しかし、この方法では、接続孔のアスペク
ト比が２程度までは、接続孔内の側壁の改質が可能であ
るが、アスペクト比が２を超える場合には、プラズマ処
理による改質処理をすることができず、層間絶縁膜は変
質するという問題があった。However, in this method, it is possible to modify the side wall in the connection hole up to an aspect ratio of the connection hole of about 2, but when the aspect ratio exceeds 2, the modification treatment by the plasma treatment is performed. Therefore, there is a problem that the interlayer insulating film is deteriorated.
【０００９】[0009]
【発明が解決しようとする課題】このように、従来のい
ずれの電極配線の形成方法においても、層間絶縁膜の接
続孔内部の側壁が、レジストマスクの剥離工程における
酸素雰囲気に晒され、層間絶縁膜中のメチル基が酸化さ
れるため、層間絶縁膜の誘電率が高くなり配線容量の増
加を招いたり、また層間絶縁膜が吸湿性膜に変質するこ
とにより金属配線の信頼性低下を招く等の問題がある。
本発明は、上記問題点に鑑みなされたもので、酸素雰囲
気でのレジストマスクの剥離工程において、層間絶縁膜
の変質を防止し得る半導体装置の製造方法を提供するも
のである。As described above, in any of the conventional methods for forming an electrode wiring, the side wall inside the connection hole of the interlayer insulating film is exposed to an oxygen atmosphere in the step of removing the resist mask. Since the methyl group in the film is oxidized, the dielectric constant of the interlayer insulating film increases and the wiring capacity increases, and the interlayer insulating film changes to a hygroscopic film, thereby lowering the reliability of the metal wiring. There is a problem.
The present invention has been made in view of the above problems, and provides a method for manufacturing a semiconductor device capable of preventing deterioration of an interlayer insulating film in a step of removing a resist mask in an oxygen atmosphere.
【００１０】[0010]
【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体装置の製造方法では、導電層を有す
る半導体基板上にメチル基を含む有機ＳＯＧからなる層
間絶縁膜を形成する工程と、前記層間絶縁膜の表面を改
質し、改質層を形成する工程と、前記改質層上にレジス
トマスクを形成する工程と、前記レジストマスクをマス
クにして前記改質層及び前記層間絶縁膜をエッチング
し、前記導電層に達する接続孔を形成する工程と、前記
接続孔内部に、前記層間絶縁膜とエッチングの選択比が
異なる材質からなる充填物質を埋め込む工程と、前記充
填物質の表面を改質し改質層を形成する工程と、前記レ
ジストマスクを酸素プラズマを利用して剥離する工程
と、前記充填物質を前記接続孔内より除去する工程と、
前記接続孔内に導電物質を充填する工程とを具備するこ
とを特徴としている。更に、前記充填物質は、ハイドロ
ジェンシルスキオキサン、ポリシラン、シリコン酸化膜
のうちから、選択された１つよりなることを特徴として
いる。In order to achieve the above object, in a method of manufacturing a semiconductor device according to the present invention, a step of forming an interlayer insulating film made of organic SOG containing a methyl group on a semiconductor substrate having a conductive layer is provided. Modifying the surface of the interlayer insulating film to form a modified layer; forming a resist mask on the modified layer; and forming the modified layer and the interlayer using the resist mask as a mask. Etching an insulating film to form a connection hole reaching the conductive layer; filling the connection hole with a filling material made of a material having a different etching selectivity from the interlayer insulating film; Forming a modified layer by modifying the surface, removing the resist mask using oxygen plasma, and removing the filler from the connection hole;
Filling the connection hole with a conductive material. Further, the filling material is made of one selected from hydrogensilsquioxane, polysilane, and silicon oxide film.
【００１１】更に、前記充填物質は、スピンコート法，
またはＣＶＤ法により前記接続孔内に埋め込むことを特
徴としている。更に、前記充填物質の除去は、ＨＦを含
む液体或いは気体、またはアルカリ性溶液により行うこ
とを特徴としている。更に、前記充填物質表面の改質層
の形成は、酸素を含むプラズマによるものであることを
特徴としている。Further, the filling material may be a spin coating method,
Alternatively, it is characterized by being buried in the connection hole by a CVD method. Further, it is characterized in that the filling material is removed by using a liquid or gas containing HF or an alkaline solution. Further, the modified layer on the surface of the filling material is formed by plasma containing oxygen.
【００１２】[0012]
【発明の実施の形態】以下、この発明の実施の形態につ
いて説明する。図１は、この本発明の実施の形態に係わ
る半導体装置の製造方法を示す概略工程断面図である。Embodiments of the present invention will be described below. FIG. 1 is a schematic process sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【００１３】先ず、図１（ａ）に示すように、シリコン
基板１１上の絶縁膜（ＳｉＯ2）１２に、例えばＡｌか
らなる下層の金属配線層（導電層）１３を埋め込み、こ
の下層の金属配線層１３を含む絶縁膜１２上に、誘電率
２．８程度のメチル基を含む例えば、ポリメチルシロキ
サンのような有機ＳＯＧ膜１４（層間絶縁膜）を膜厚９
０００ナ に形成する。この有機ＳＯＧ膜１４は、有機Ｓ
ＯＧをスピンコート法により塗布し、さらに１５０℃で
３０秒、２００℃で３０秒、４５０℃で３０分焼成する
ことにより形成する。First, as shown in FIG. 1A, a lower metal wiring layer (conductive layer) 13 made of, for example, Al is buried in an insulating film (SiO 2 ) 12 on a silicon substrate 11, and the lower metal layer is formed. On the insulating film 12 including the wiring layer 13, an organic SOG film 14 (interlayer insulating film) containing a methyl group having a dielectric constant of about 2.8, such as polymethylsiloxane, having a thickness of 9 is formed.
000 na. This organic SOG film 14 is made of organic S
OG is applied by a spin coating method, and further formed by baking at 150 ° C. for 30 seconds, 200 ° C. for 30 seconds, and 450 ° C. for 30 minutes.
【００１４】次に、図１（ｂ）に示すように、その有機
ＳＯＧ膜１４の表面を約１０ｎｍ酸化させ、酸化膜から
なる改質層１５を形成する。この改質層１５は、後述す
るレジストパターン膜を酸素を含むプラズマにより剥離
する工程において、酸素による有機ＳＯＧ膜１４の変質
を防止するためである。Next, as shown in FIG. 1B, the surface of the organic SOG film 14 is oxidized by about 10 nm to form a modified layer 15 made of an oxide film. This modified layer 15 is to prevent the organic SOG film 14 from being deteriorated by oxygen in a step of peeling the resist pattern film using plasma containing oxygen, which will be described later.
【００１５】またこの改質膜１４は、マグネトロン反応
イオンエッチング（ＲＩＥ）装置より、酸素（Ｏ2）ガ
ス流量を１００ｓｃｃｍ、ＲＦ電力を２００Ｗ、反応圧
力を１００ｍＴｏｒｒとする条件で生成したプラズマに
６０秒間晒すことにより形成する。The modified film 14 is formed by a magnetron reactive ion etching (RIE) apparatus using a plasma generated under the conditions of an oxygen (O 2 ) gas flow rate of 100 sccm, RF power of 200 W and a reaction pressure of 100 mTorr for 60 seconds. Formed by exposure.
【００１６】その後、図１（ｃ）に示すように、この改
質膜１５上に、レジスト膜を膜厚４５００ナ に形成し、
次に、例えば、電子ビーム露光により所定パターンを露
光、現像して、前記下層の金属配線層１３に対応する位
置に開口を有するレジストパターン膜１６を形成する。Thereafter, as shown in FIG. 1C, a resist film having a thickness of 4500 nm is formed on the modified film 15.
Next, for example, a predetermined pattern is exposed and developed by electron beam exposure to form a resist pattern film 16 having an opening at a position corresponding to the lower metal wiring layer 13.
【００１７】次に、図１（ｄ）に示すように、マグネト
ロンＲＩＥ装置により、オクタフルシクロオクタン（Ｃ
4Ｆ8）／一酸化炭素（ＣＯ）／アルゴン（Ａｒ）／酸素
（Ｏ2）＝１０／５０／２００／１０ｓｃｃｍ、ＲＦ電
力を１７００Ｗ，反応圧力を４０ｍＴｏｒｒとする条件
で生成したプラズマに１８０秒間晒して、レジストパタ
ーン膜１６より露出した前記改質層及びその下の前記有
機ＳＯＧ膜１４をエッチングすることにより、下層金属
配線層１３に達する接続孔１７を形成する。その後、図
１（ｅ）に示すように、この接続孔１７内に、有機ＳＯ
Ｇ膜とエッチング選択比が異なる材料、例えばハイドロ
ジェンシルセスキオキシン（ＨＳＱ）からなる充填物質
１８を充填する。この充填物質１８は、接続孔１７内の
側面に、有機ＳＯＧ膜１４が露出しないようにスピンコ
ート法により、少なくとも有機ＳＯＧ膜１４と改質膜１
５との境界の高さまで充填し、好ましくは改質膜１５の
上表面の高さまで充填する。Next, as shown in FIG. 1D, octaflucyclooctane (C
4 F 8 ) / carbon monoxide (CO) / argon (Ar) / oxygen (O 2 ) = 10/50/200/10 sccm, RF power is 1700 W, reaction pressure is 40 mTorr, and plasma is generated for 180 seconds. By exposing and etching the modified layer exposed from the resist pattern film 16 and the organic SOG film 14 thereunder, a connection hole 17 reaching the lower metal wiring layer 13 is formed. After that, as shown in FIG.
A filling material 18 made of a material having a different etching selectivity from the G film, for example, hydrogen silsesquioxin (HSQ) is filled. The filling material 18 is applied to at least the organic SOG film 14 and the modified film 1 by spin coating so that the organic SOG film 14 is not exposed on the side surface inside the connection hole 17.
5 and preferably up to the height of the upper surface of the modified film 15.
【００１８】しかし、この充填物質１８は、レジストパ
ターン膜１６の上表面の高さまで充填されていても差し
支えない。次に、図1 （ｆ）に示すように、レジストパ
ターン膜の剥離工程において、前記充填物質の変質を防
止するために、前記有機ＳＯＧ膜表面の改質と同様の条
件で、この充填物質１８表面を酸化し、酸化膜からなる
改質層１９を形成する。However, the filling material 18 may be filled up to the height of the upper surface of the resist pattern film 16. Next, as shown in FIG. 1F, in the step of removing the resist pattern film, in order to prevent the alteration of the filling material, the filling material 18 is formed under the same conditions as those for modifying the surface of the organic SOG film. The surface is oxidized to form a modified layer 19 made of an oxide film.
【００１９】次に、図１（ｇ ）に示すように、レジス
トパターン膜１６を、マイクロ波パワーを２．４５ＧＨ
Ｚ、ＲＦ電力を１５００Ｗ、反応圧力を０．４５Ｔｏｒ
ｒ、Ｏ2流量を１０００ｓｃｃｍとする条件で生成した
酸素プラズマ雰囲気に６０秒晒すことにより、レジスト
パターン膜１６を剥離する。Next, as shown in FIG. 1 (g), the resist pattern film 16 is made to have a microwave power of 2.45 GHz.
Z, RF power 1500 W, reaction pressure 0.45 Torr
The resist pattern film 16 is peeled off by exposing it to an oxygen plasma atmosphere generated at a flow rate of 1000 sccm for r and O 2 for 60 seconds.
【００２０】しかる後、図１（ｈ）に示すように、前記
充填物質１８を、濃度１．０％の弗酸（ＨＦ）水溶液
で、３０秒間エッチングし、この充填物質１８を除去す
る。この時、充填物質１８表面の改質層１９も一緒に除
去される。Thereafter, as shown in FIG. 1 (h), the filling material 18 is etched with a 1.0% aqueous solution of hydrofluoric acid (HF) for 30 seconds to remove the filling material 18. At this time, the modified layer 19 on the surface of the filling material 18 is also removed.
【００２１】次に、図１（ｉ）に示すように、この充填
物質１８を除去した後の前記接続孔１７内にＡｌ等の金
属配線層１８を充填し、必要に応じ、その金属配線層２
０上に上層の金属配線層を形成する。Next, as shown in FIG. 1 (i), a metal wiring layer 18 of Al or the like is filled in the connection hole 17 after removing the filling material 18, and if necessary, the metal wiring layer 18 is formed. 2
An upper metal wiring layer is formed on the first metal layer.
【００２２】上記実施形態の半導体装置の製造方法によ
れば、充填物を接続内に埋め込むことにより、その接続
孔内の層間絶縁膜側壁を覆った後、酸素プラズマによる
レジスト剥離を行っていいる。According to the method of manufacturing a semiconductor device of the above embodiment, the filling is buried in the connection to cover the side wall of the interlayer insulating film in the connection hole, and then the resist is stripped by oxygen plasma.
【００２３】そのため接続孔内の層間絶縁膜は、酸素プ
ラズマに晒されることがなく、本来の誘電率を保持する
と共に、吸湿性膜に変質することがなく、配線間容量の
抑制及び高信頼性の金属配線が得られる。Therefore, the interlayer insulating film in the connection hole is not exposed to oxygen plasma, maintains its original dielectric constant, does not change into a hygroscopic film, suppresses the capacitance between wirings, and has high reliability. Is obtained.
【００２４】なお、上記実施例に於いては、メチル基を
含む有機ＳＯＧ膜（層間絶縁膜）として、メチルシロキ
サンを用いたが、エチルシロキサンでもよい。また、充
填物質として、無機ＳＯＧのハイドロジエンシルセスキ
オキサンを用いたが、シリコンとシリコンの結合を主鎖
に持つポリマーに有機物( 炭素) を含んだポリシランと
称する例えば、ポリジフェニシラン、ポリフェニルメチ
ルシラン或はシリコン酸化膜を用いいてもよい。In the above embodiment, methylsiloxane is used as the organic SOG film (interlayer insulating film) containing a methyl group, but ethylsiloxane may be used. As the filling material, inorganic SOG hydrogen silsesquioxane was used. However, a polymer having an organic substance (carbon) in a polymer having a silicon-silicon bond in the main chain is referred to as polysilane, for example, polydiphenylsilane, polyphenyl. Methylsilane or a silicon oxide film may be used.
【００２５】[0025]
【発明の効果】本発明の半導体装置の製造方法では、充
填物を接続孔内に埋め込むことにより、その接続孔内の
層間絶縁膜側壁を覆った後、酸素プラズマによるレジス
ト剥離を行っている。According to the method of manufacturing a semiconductor device of the present invention, the filling is buried in the connection hole to cover the side wall of the interlayer insulating film in the connection hole, and then the resist is stripped by oxygen plasma.
【００２６】そのため接続孔内の層間絶縁膜は、酸素プ
ラズマに晒されることがなく、本来の誘電率を保持する
と共に、吸湿性膜に変質することがなく、配線容量の抑
制及び高信頼性の金属配線が得られる。Therefore, the interlayer insulating film in the connection hole is not exposed to oxygen plasma, retains the original dielectric constant, does not change into a hygroscopic film, suppresses the wiring capacitance and achieves high reliability. A metal wiring is obtained.
【図１】本発明の実施形態に係る半導体装置の製造方法
を示す概略工程断面図。FIG. 1 is a schematic sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図２】従来の半導体装置の製造方法を示す概略工程断
面図。FIG. 2 is a schematic process sectional view showing a conventional method for manufacturing a semiconductor device.
１１、２１・・・ シリコン基板( 半導体基板) １２・・・ 絶縁膜 １３、２２・・・ 下層金属配線層（導電層） １４、２３・・・ 層間絶縁膜 １５、１９、２４・・・ 改質層 １６、２５・・・ レジストマスク １７、２６・・・ 接続孔 １８・・・ 充填物質 ２０、２７・・・ 金属配線膜 11, 21 ... silicon substrate (semiconductor substrate) 12 ... insulating film 13, 22 ... lower metal wiring layer (conductive layer) 14, 23 ... interlayer insulating film 15, 19, 24 ... Material layer 16, 25 Resist mask 17, 26 Connection hole 18 Filling material 20, 27 Metal wiring film
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 4M104 AA01 BB02 CC01 DD08 DD09 DD20 EE18 5F033 AA12 AA15 AA29 AA64 DA04 DA13 DA34 EA02 EA06 EA11 EA29 FA03 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA01 BB02 CC01 DD08 DD09 DD20 EE18 5F033 AA12 AA15 AA29 AA64 DA04 DA13 DA34 EA02 EA06 EA11 EA29 FA03
Claims (5)
含む有機ＳＯＧからなる層間絶縁膜を形成する工程と、
前記層間絶縁膜表面を改質し改質層を形成する工程と、
前記改質層上にレジストマスクを形成する工程と、前記
レジストマスクをマスクにして前記改質層及び前記層間
絶縁膜をエッチングし、前記導電層に達する接続孔を形
成する工程と、前記接続孔内部に、前記層間絶縁膜とエ
ッチングの選択比が異なる材質からなる充填物質を埋め
込む工程と、前記充填物質の表面を改質し改質層を形成
する工程と、前記レジストマスクを酸素プラズマを利用
して剥離する工程と、前記充填物質を前記接続孔内より
除去する工程と、前記接続孔内に導電物質を充填する工
程とを具備することを特徴とする半導体装置の製造方
法。A step of forming an interlayer insulating film made of organic SOG containing a methyl group on a semiconductor substrate having a conductive layer;
Forming a modified layer by modifying the surface of the interlayer insulating film;
Forming a resist mask on the modified layer; etching the modified layer and the interlayer insulating film using the resist mask as a mask to form a connection hole reaching the conductive layer; A step of burying a filling material made of a material having a different etching selectivity from the interlayer insulating film, a step of modifying the surface of the filling material to form a modified layer, and using the resist mask with oxygen plasma. And removing the filler material from the connection hole, and filling the connection hole with a conductive material.
オキサン、ポリシラン、シリコン酸化膜のうちから、選
択された１つよりなることを特徴とする請求項１に記載
の半導体装置の製造方法。2. The method according to claim 1, wherein the filling material comprises one selected from hydrogen silsquioxane, polysilane, and a silicon oxide film.
ＣＶＤ法により前記接続孔内に埋め込むことを特徴とす
る請求項１に記載の半導体装置の製造方法。3. The method according to claim 1, wherein the filling material is buried in the connection holes by a spin coating method or a CVD method.
いは気体、またはアルカリ性溶液により行うことを特徴
とする請求項１に記載の半導体装置の製造方法。4. The method according to claim 1, wherein the removing of the filling material is performed by using a solution or gas containing HF or an alkaline solution.
ガスを含むプラズマによるものであることを特徴とする
請求項１に記載の半導体装置の製造方法。5. The method according to claim 1, wherein the formation of the modified layer on the surface of the filling material is performed by plasma containing oxygen gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10223867A JP2000058642A (en) | 1998-08-07 | 1998-08-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10223867A JP2000058642A (en) | 1998-08-07 | 1998-08-07 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000058642A true JP2000058642A (en) | 2000-02-25 |
Family
ID=16804960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10223867A Pending JP2000058642A (en) | 1998-08-07 | 1998-08-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000058642A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001313333A (en) * | 2000-02-23 | 2001-11-09 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| JP2002026121A (en) * | 2000-06-30 | 2002-01-25 | Tokyo Electron Ltd | Semiconductor device and method of manufacturing the same, and method of forming insulation film |
| JP2002043423A (en) * | 2000-07-24 | 2002-02-08 | Tokyo Ohka Kogyo Co Ltd | Method for processing film and method for manufacturing semiconductor device using the same |
| JP2004056123A (en) * | 2000-02-23 | 2004-02-19 | Matsushita Electric Ind Co Ltd | Manufacturing method of semiconductor device |
| US6815341B2 (en) | 2000-02-23 | 2004-11-09 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating metal interconnect in a carbon-containing silicon oxide film |
| US6818997B2 (en) * | 2002-01-23 | 2004-11-16 | Micron Technology, Inc. | Semiconductor constructions |
| JP2011221477A (en) * | 2010-04-05 | 2011-11-04 | Samsung Mobile Display Co Ltd | Touch screen panel integrated flat panel display unit and method for manufacturing the same |
| KR101087508B1 (en) | 2003-07-18 | 2011-11-29 | 매그나칩 반도체 유한회사 | Method of forming copper wiring in semiconductor device |
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1998
- 1998-08-07 JP JP10223867A patent/JP2000058642A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001313333A (en) * | 2000-02-23 | 2001-11-09 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| JP2004056123A (en) * | 2000-02-23 | 2004-02-19 | Matsushita Electric Ind Co Ltd | Manufacturing method of semiconductor device |
| US6815341B2 (en) | 2000-02-23 | 2004-11-09 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating metal interconnect in a carbon-containing silicon oxide film |
| US7030009B2 (en) | 2000-02-23 | 2006-04-18 | Matsushita Electric Industrial Co., Ltd. | Method for forming metal interconnect in a carbon containing silicon oxide film |
| JP2002026121A (en) * | 2000-06-30 | 2002-01-25 | Tokyo Electron Ltd | Semiconductor device and method of manufacturing the same, and method of forming insulation film |
| JP2002043423A (en) * | 2000-07-24 | 2002-02-08 | Tokyo Ohka Kogyo Co Ltd | Method for processing film and method for manufacturing semiconductor device using the same |
| US6818997B2 (en) * | 2002-01-23 | 2004-11-16 | Micron Technology, Inc. | Semiconductor constructions |
| KR101087508B1 (en) | 2003-07-18 | 2011-11-29 | 매그나칩 반도체 유한회사 | Method of forming copper wiring in semiconductor device |
| JP2011221477A (en) * | 2010-04-05 | 2011-11-04 | Samsung Mobile Display Co Ltd | Touch screen panel integrated flat panel display unit and method for manufacturing the same |
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