JP2000054189A - MATERIAL FOR ELECTRIC AND ELECTRONIC PARTS USED BY BONDING WITH Sn-Bi-BASED SOLDER, ELECTRIC AND ELECTRONIC PARTS USING IT, ELECTRIC AND ELECTRONIC PARTS-MOUNTED SUBSTRATE, AND SOLDER BONDING, OR MOUNTING METHOD USING IT - Google Patents
MATERIAL FOR ELECTRIC AND ELECTRONIC PARTS USED BY BONDING WITH Sn-Bi-BASED SOLDER, ELECTRIC AND ELECTRONIC PARTS USING IT, ELECTRIC AND ELECTRONIC PARTS-MOUNTED SUBSTRATE, AND SOLDER BONDING, OR MOUNTING METHOD USING ITInfo
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- JP2000054189A JP2000054189A JP22591298A JP22591298A JP2000054189A JP 2000054189 A JP2000054189 A JP 2000054189A JP 22591298 A JP22591298 A JP 22591298A JP 22591298 A JP22591298 A JP 22591298A JP 2000054189 A JP2000054189 A JP 2000054189A
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- solder
- electric
- alloy
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は電気・電子部品用材
料とそれを用いた電気・電子部品、電気・電子部品実装
基板、ならびに、それを用いたはんだ接合方法または実
装方法に関し、更に詳しくは、Ｓｎ−Ｂｉ系はんだを用
いて相手材にはんだ接合したときに、その接合部の接合
信頼性が高くなる電気・電子部品用材料とそれを用いた
電気・電子部品、電気・電子部品実装基板、ならびに、
それを用いたはんだ接合方法または実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a material for electric / electronic parts, an electric / electronic part using the same, a substrate for mounting electric / electronic parts, and a solder joining method or a mounting method using the same. And electrical / electronic component materials that increase the joining reliability of the joint when soldered to a mating material using Sn-Bi solder, and electrical / electronic components and electrical / electronic component mounting boards using the same , And
The present invention relates to a solder joining method or a mounting method using the same.
【０００２】[0002]
【従来の技術】各種の電気・電子機器に組み込まれる部
品の材料としては、従来から、ＣｕまたはＣｕ合金が広
く用いられている。すなわち、その用途は個別半導体や
ＩＣパッケージのリード線やリードピン、またはリード
フレームなどのリード材料を代表例とし、更にはソケッ
ト類やコネクタ，スイッチの端子や接点ばねなどのコン
タクト材料にも及んでいる。これらの用途は、Ｃｕまた
はＣｕ合金が、導電性，熱伝導性が優れているととも
に、機械的な強度や加工性の点でも優れ、また経済的に
も有利であるという性質を利用したものである。2. Description of the Related Art Conventionally, Cu or Cu alloy has been widely used as a material of components incorporated in various electric and electronic devices. That is, the application is typically to lead materials such as lead wires and lead pins of individual semiconductors and IC packages, or lead frames, and also extends to contact materials such as sockets, connectors, switch terminals, and contact springs. . These applications are based on the fact that Cu or Cu alloy has excellent electrical and thermal conductivity, mechanical strength and workability, and is economically advantageous. is there.
【０００３】上記したリード材料としては、従来から、
コバール合金や４２アロイに代表されるＦｅ−Ｎｉ系合
金，Ｆｅ−Ｃ系合金などのＦｅ系材料も使用されてい
る。このＦｅ系材料は、前記したＣｕ合金に比べると、
熱伝導性や導電性は劣るものの、機械的な強度が高く、
また熱膨張率がＳｉチップやパッケージの封止樹脂のそ
れに近似しているので、その表面に厚み数十μｍ程度の
Ｃｕめっきを施して導電性とはんだ濡れ性を高めた状態
にしてダイオードやコンデンサなどのリード線として用
いられている。As the lead material described above, conventionally,
Fe-based materials such as Kovar alloys, Fe-Ni-based alloys represented by 42 alloys, and Fe-C-based alloys are also used. This Fe-based material, compared to the above-mentioned Cu alloy,
Thermal conductivity and conductivity are inferior, but mechanical strength is high,
In addition, since the coefficient of thermal expansion is similar to that of the sealing resin for Si chips and packages, the surface of the diode or capacitor is plated with Cu several tens of μm thick to improve conductivity and solder wettability. It is used as a lead wire.
【０００４】そして、上記した材料の場合、その表面に
は、めっきに代表される表面処理を施すことにより材料
機能の信頼性を高めて実使用するということが行われて
いる。例えば、はんだ付けによってプリント配線基板に
部品を実装するときに用いるリード材料や部品の端子材
料の場合、その表面にＳｎめっきまたはＳｎ合金めっき
を施してはんだ付け性を高めるという処置が採られてい
る。具体的には、半導体パッケージを組み立てたのちリ
ードフレームのアウターリード部に例えばＳｎ−Ｐｂ合
金を用いて外装はんだめっきを施したり、個別半導体や
コンデンサのリード線にも予めＳｎめっきやＳｎ−Ｐｂ
合金めっきを施し、更に加熱してリフロー処理を行うこ
ともある。[0004] In the case of the above-mentioned materials, their surfaces are subjected to a surface treatment typified by plating to enhance the reliability of the material functions, and are actually used. For example, in the case of a lead material or a terminal material of a component used when mounting a component on a printed wiring board by soldering, a measure is taken to improve the solderability by applying Sn plating or Sn alloy plating to the surface thereof. . Specifically, after assembling the semiconductor package, the outer lead portion of the lead frame is subjected to exterior solder plating using, for example, an Sn-Pb alloy, or the lead wires of individual semiconductors and capacitors are subjected to Sn plating or Sn-Pb
In some cases, alloy plating is performed, followed by reflow treatment by heating.
【０００５】更には、ＣｕまたはＣｕ合金から成る材料
の場合、その表面にＳｎまたはＳｎ合金のめっきを施す
と、得られた材料は前記した特性の外に耐食性，耐摩耗
性も優れ、しかも経済的に有利であるということから、
リード材料の外に各種端子やコネクタなどの材料として
も多用されている。ところで、これらの材料をプリント
配線基板やハイブリッドＩＣ基板などに実装する場合に
は、相手材との間でＳｎ−Ｐｂ合金であるはんだを用い
て実施されるのが通例である。しかしながら、はんだに
含まれているＰｂは人体に悪影響を与える虞れがあると
のことから、今後は、その優れた性質を備えているにも
かかわらず使用が敬遠されようとしている。そしてＰｂ
を含まないＳｎ合金、具体的には、Ｓｎ−Ａｇ系、Ｓｎ
−Ｚｎ系、Ｓｎ−Ｉｎ系、Ｓｎ−Ｂｉ系などの実用化が
検討されている。Further, in the case of a material made of Cu or Cu alloy, if the surface is plated with Sn or Sn alloy, the obtained material has excellent corrosion resistance and wear resistance in addition to the above-mentioned characteristics, and is economical. Because it is advantageous
In addition to the lead material, it is often used as a material for various terminals and connectors. By the way, when these materials are mounted on a printed wiring board, a hybrid IC board, or the like, it is customary to use a solder, which is an Sn-Pb alloy, with a counterpart material. However, Pb contained in the solder may adversely affect the human body. Therefore, in the future, the use of Pb, despite its excellent properties, will be avoided. And Pb
Alloys containing no Sn, specifically, Sn-Ag based, Sn
-Practical application of Zn-based, Sn-In-based, Sn-Bi-based and the like is being studied.
【０００６】これらのうち、Ｓｎ−Ａｇ系のものは接合
強度や濡れ性の点では優れているが、他方では高融点、
高価格であるという難点があり、またＳｎ−Ｚｎ系のも
のは低価格であるとはいえ、濡れ性が悪く、しかも非酸
化性雰囲気下でなければ使用できないという難点があ
る。更に、Ｓｎ−Ｉｎ系は低融点であるとはいえ高価格
である。[0006] Of these, Sn-Ag type is excellent in bonding strength and wettability, but on the other hand, it has high melting point,
It is disadvantageous in that it is expensive, and although Sn-Zn-based ones are inexpensive, they have poor wettability and can be used only in a non-oxidizing atmosphere. Furthermore, the Sn-In type has a low melting point but is expensive.
【０００７】Ｓｎ−Ｂｉ系は耐熱性に劣り、また脆いと
いう点で問題がある反面、低融点化が容易でありまた低
コスト化も可能であるという利点を備えている。そし
て、接合強度や濡れ性の点で優れているが高融点である
ことが難点であったＳｎ−Ａｇ系もＢｉを添加すること
により、低融点化することができるということから、最
近では、Ｂｉを含有させたＳｎ基合金が早期に実用化さ
れる傾向にある。[0007] The Sn-Bi system is inferior in heat resistance and has a problem in that it is brittle, but has an advantage that the melting point can be easily reduced and the cost can be reduced. In addition, since the Sn-Ag system, which is excellent in bonding strength and wettability but is difficult to have a high melting point, can be lowered in melting point by adding Bi, recently, There is a tendency that a Sn-based alloy containing Bi is put to practical use at an early stage.
【０００８】具体的には、Ｓｎ−２％Ｂｉ−３％Ａｇ、
Ｓｎ−５％Ｂｉ−３.２５％Ａｇ、Ｓｎ−４.８％Ｂｉ−
３.４％Ａｇ、Ｓｎ−６％Ｂｉ−３％Ａｇ、Ｓｎ−７.５
％Ｂｉ−２％Ａｇ−０.５％Ｃｕ、Ｓｎ−９.５％Ｂｉ−
２.５％Ａｇ、Ｓｎ−１０％Ｂｉ−２.８％Ａｇ−０.６
％Ｃｕ、Ｓｎ−２２％Ｂｉ−２％Ａｇ、Ｓｎ−０.５％
Ｂｉ−３.５％Ａｇ−３％Ｉｎ、Ｓｎ−３％Ｂｉ−３.５
％Ａｇ−３％Ｉｎ、Ｓｎ−６％Ｂｉ−６％Ｚｎ、Ｓｎ−
１０％Ｂｉ−８％Ｚｎ、Ｓｎ−８％Ｂｉ−７％Ｚｎ、Ｓ
ｎ−１４％Ｂｉ−５％Ｚｎ、Ｓｎ−５８％Ｂｉなどの材
料が検討されている。Specifically, Sn-2% Bi-3% Ag,
Sn-5% Bi-3.25% Ag, Sn-4.8% Bi-
3.4% Ag, Sn-6% Bi-3% Ag, Sn-7.5
% Bi-2% Ag-0.5% Cu, Sn-9.5% Bi-
2.5% Ag, Sn-10% Bi-2.8% Ag-0.6
% Cu, Sn-22% Bi-2% Ag, Sn-0.5%
Bi-3.5% Ag-3% In, Sn-3% Bi-3.5
% Ag-3% In, Sn-6% Bi-6% Zn, Sn-
10% Bi-8% Zn, Sn-8% Bi-7% Zn, S
Materials such as n-14% Bi-5% Zn and Sn-58% Bi have been studied.
【０００９】以後、上記したようなＡｇ，Ｃｕ，Ｚｎ，
ＩｎなどＢｉ以外の元素も含有するＳｎ基合金はんだも
Ｓｎ−Ｂｉ系はんだと称する。このように、Ｓｎ−Ｂｉ
系のはんだは低融点化が容易であり、また比較的低価格
化を実現できるなどの利点を備えているが、他方では次
のような問題もある。すなわち、はんだ接合部が高温環
境下に曝されると、当該接合部の接合強度が経時的に大
きく低下していくということである。とくに、Ｂｉ含有
量が２重量％以上になると、溶融はんだが凝固するとき
に、Ｂｉの偏析とそれに伴ってＳｎとＢｉを含む２元以
上の共晶融解現象が起こり、接合部に低融点部分が発生
して接合部の強度劣化を誘発し、最悪の場合には、その
接合部にクラックの発生することもあるということであ
る。Hereinafter, Ag, Cu, Zn,
An Sn-based alloy solder containing an element other than Bi such as In is also referred to as a Sn-Bi-based solder. Thus, Sn-Bi
Although the system solder has such advantages that the melting point can be easily reduced and the price can be relatively reduced, it has the following problems. That is, when the solder joint is exposed to a high-temperature environment, the joint strength of the joint decreases greatly with time. In particular, when the Bi content is 2% by weight or more, when the molten solder is solidified, the segregation of Bi and the eutectic melting phenomenon of two or more elements containing Sn and Bi occur, and the low melting point portion is formed at the joint. This causes the strength of the joint to deteriorate, and in the worst case, cracks may occur at the joint.
【００１０】このことは、次のような点で不都合であ
る。すなわち、最近では、プリント配線基板への各種部
品の高密度実装が進展しているが、そのことに伴って、
基板からの放熱量は増加の一途をたどっている。したが
って、実装時に上記したＳｎ−Ｂｉ系はんだを用いる
と、その接合部は常時高温状態に曝されることになるた
め、当該接合部の強度は経時的に劣化していき、機器の
実働過程で断線や短絡事故を招くこともある。換言すれ
ば、Ｓｎ−Ｂｉ系はんだを用いた接合部は、高温環境下
に曝された場合、その接合信頼性に劣るということであ
る。[0010] This is disadvantageous in the following points. In other words, recently, high-density mounting of various components on printed wiring boards has been progressing,
The amount of heat radiation from the substrate is steadily increasing. Therefore, when the above-mentioned Sn-Bi solder is used at the time of mounting, the joint is always exposed to a high temperature state, so that the strength of the joint deteriorates with time, and during the actual operation of the device, A disconnection or short circuit accident may be caused. In other words, the joint using the Sn-Bi-based solder is inferior in joint reliability when exposed to a high-temperature environment.
【００１１】[0011]
【発明が解決しようとする課題】本発明は、Ｓｎ−Ｂｉ
系はんだを接合用はんだ材料として用いたときに形成さ
れる接合部の上記した問題を解決し、形成された接合部
の高温環境下における経時的な強度低下が起こりづらく
なり、もって接合部の接合信頼性を高めることを可能に
する電気・電子部品用材料とそれを用いた電気・電子部
品実装基板、ならびに、それを用いたはんだ接合方法の
提供を目的とする。SUMMARY OF THE INVENTION The present invention is directed to a Sn-Bi
Solving the above-mentioned problems of the joints formed when using a system solder as a solder material for joining, the strength of the formed joints over time in a high-temperature environment is unlikely to decrease, and thus the joining of the joints An object of the present invention is to provide a material for an electric / electronic component that can enhance reliability, an electric / electronic component mounting board using the same, and a solder joining method using the same.
【００１２】[0012]
【課題を解決するための手段】上記した目的を達成する
ために、本発明においては、少なくとも表面がＣｕまた
はＣｕ合金から成る基体の前記表面に、Ｃｕ3Ｓｎ（ε
相）層とＣｕ6Ｓｎ5（η'相）層とがこの順序で積層さ
れて成る中間層を介して、純Ｓｎから成る厚み１〜２０
μｍの表面層が形成されていることを特徴とする、Ｓｎ
−Ｂｉ系はんだを接合して用いられる電気・電子部品用
材料（以下、材料Ａという）、少なくとも表面がＣｕま
たはＣｕ合金から成る基体の前記表面に、Ｃｕ3Ｓｎ
（ε相）層とＣｕ6Ｓｎ5（η'相）層とがこの順序で積
層されて成る中間層を介して、Ｓｎ−Ａｇ合金から成る
厚み１〜２０μｍの表面層が形成されていることを特徴
とする、Ｓｎ−Ｂｉ系はんだを接合して用いられる電気
・電子部品用材料（以下、材料Ｂという）、少なくとも
表面がＣｕまたはＣｕ合金から成る基体の前記表面に、
Ｃｕ3Ｓｎ（ε相）層とＣｕ6Ｓｎ5（η'相）層とがこの
順序で積層されて成る中間層を介して、Ｓｎ−Ｂｉ合金
から成る厚み１〜２０μｍの表面層が形成されているこ
とを特徴とする、Ｓｎ−Ｂｉ系はんだを接合して用いら
れる電気・電子部品用材料（以下、材料Ｃという）が提
供される。In order to achieve the above object, according to the present invention, at least the surface of a substrate made of Cu or a Cu alloy has Cu 3 Sn (ε
Phase) layer and a Cu 6 Sn 5 (η ′ phase) layer are stacked in this order through an intermediate layer to form a layer of pure Sn having a thickness of 1 to 20.
Sn, wherein a surface layer of μm is formed.
A material for electric / electronic parts (hereinafter referred to as a material A) used by bonding a Bi-based solder, and Cu 3 Sn on the surface of a substrate having at least a surface made of Cu or a Cu alloy;
A 1-20 μm thick surface layer made of a Sn—Ag alloy is formed via an intermediate layer formed by laminating an (ε phase) layer and a Cu 6 Sn 5 (η ′ phase) layer in this order. A material for electric / electronic parts (hereinafter, referred to as a material B) used by joining Sn-Bi-based solder, at least the surface of which is made of Cu or a Cu alloy,
A surface layer of a Sn—Bi alloy having a thickness of 1 to 20 μm is formed via an intermediate layer formed by laminating a Cu 3 Sn (ε phase) layer and a Cu 6 Sn 5 (η ′ phase) layer in this order. A material for electric / electronic parts (hereinafter, referred to as material C) which is used by joining Sn-Bi-based solder is provided.
【００１３】また、本発明においては、少なくとも表面
がＣｕまたはＣｕ合金から成る基体の前記表面に、純Ａ
ｇから成る厚み１〜１０μｍの表面層が形成されている
ことを特徴とする、Ｓｎ−Ｂｉ系はんだを接合して用い
られる電気・電子部品用材料（以下、材料Ｄという）が
提供され、更に、上記した材料Ａ〜Ｄにおける表面層に
は、Ｃｕが０.２〜３重量％含有されていることを特徴
とする、Ｓｎ−Ｂｉ系はんだを接合して用いられる電気
・電子部品用材料（以下、材料Ｅという）が提供され
る。Further, in the present invention, pure A is added to the surface of the substrate, at least the surface of which is made of Cu or a Cu alloy.
g, and a material for electric / electronic parts (hereinafter, referred to as material D) used by joining Sn-Bi-based solder, wherein a surface layer having a thickness of 1 to 10 μm is formed. The surface layer of each of the above-mentioned materials A to D contains 0.2 to 3% by weight of Cu, and is a material for electric / electronic parts used by joining Sn-Bi solders ( Hereinafter, referred to as material E).
【００１４】また、本発明においては、前記材料Ａ〜Ｅ
のいずれかを用いたことを特徴とする電気・電子部品と
電気・電子部品実装基板が提供される。更に、本発明に
おいては、前記材料Ａ〜Ｅいずれかの電気・電子部品用
材料またはそれらを用いた電気・電子部品を、Ｂｉ含有
量が２重量％以上であるＳｎ−Ｂｉ系はんだを用いて相
手材もしくは回路基板に接合または実装することを特徴
とするはんだ接合または実装方法が提供される。In the present invention, the materials A to E
An electric / electronic component and an electric / electronic component mounting board characterized by using any one of the above are provided. Further, in the present invention, the material for electric / electronic parts of any of the above-mentioned materials A to E or the electric / electronic part using them is formed by using an Sn-Bi solder having a Bi content of 2% by weight or more. A solder joining or mounting method characterized by joining or mounting to a counterpart material or a circuit board is provided.
【００１５】[0015]
【発明の実施の形態】図１は、本発明の材料Ａ、材料
Ｂ、材料Ｃの層構造を示す断面図であり、図２は本発明
の材料Ｄの層構造を示す断面図である。まず、図１で示
した材料は、基体１の表面に、Ｃｕ3Ｓｎ（ε相）から
成る層２ａとＣｕ6Ｓｎ5（η'相）から成る層２ｂとが
この順序で積層されている中間層２を介して、後述する
表面層３が形成された層構造になっている。FIG. 1 is a sectional view showing a layer structure of a material A, a material B and a material C of the present invention, and FIG. 2 is a sectional view showing a layer structure of a material D of the present invention. First, in the material shown in FIG. 1, a layer 2a made of Cu 3 Sn (ε phase) and a layer 2b made of Cu 6 Sn 5 (η ′ phase) are laminated on the surface of the substrate 1 in this order. It has a layer structure in which a surface layer 3 described later is formed via the intermediate layer 2.
【００１６】ここで、基体１としては、少なくともその
表面がＣｕまたはＣｕ合金で形成されているものであれ
ば何であってもよく、例えば、ＣｕまたはＣｕ合金材そ
のものや、炭素鋼，Ｆｅ−Ｎｉ系合金、Ｆｅ−Ｎｉ−Ｃ
ｏ系合金，ステンレス鋼などのＦｅ系材料を芯材とし、
その表面をＣｕまたはＣｕ合金で被覆したものなどをあ
げることができる。後者の基体の場合、目的とする部品
の用途に求められる機械的な強度や導電性との関係を勘
案して芯材とその表面に形成するＣｕまたはＣｕ合金、
とりわけＣｕ合金の種類は適宜に選定される。Here, the substrate 1 may be anything as long as at least its surface is formed of Cu or a Cu alloy, for example, Cu or Cu alloy itself, carbon steel, Fe--Ni Alloy, Fe-Ni-C
Fe-based materials such as o-based alloys and stainless steel
One whose surface is coated with Cu or a Cu alloy can be cited. In the case of the latter substrate, Cu or Cu alloy formed on the core material and its surface in consideration of the relationship between mechanical strength and conductivity required for the intended use of the part,
In particular, the type of Cu alloy is appropriately selected.
【００１７】また、基体１の形状も、部品としての用途
目的や後述する表面層形成方法に対応して、線状、板
状、条など適宜に選定される。そして、材料Ａの場合
は、表面層３が純Ｓｎで構成され、材料Ｂの場合は表面
層３が後述するＳｎ−Ａｇ合金で構成され、また材料Ｃ
の場合は表面層３が後述するＳｎ−Ｂｉ合金で構成さ
れ、これら表面層３の厚みは材料Ａ〜Ｃのいずれにおい
ても１〜２０μｍになっている。The shape of the substrate 1 is also appropriately selected, such as a linear shape, a plate shape, or a strip, in accordance with the purpose of use as a part or the surface layer forming method described later. In the case of the material A, the surface layer 3 is composed of pure Sn, in the case of the material B, the surface layer 3 is composed of an Sn-Ag alloy described later, and in the case of the material C
In this case, the surface layer 3 is made of a Sn—Bi alloy described later, and the thickness of the surface layer 3 is 1 to 20 μm in any of the materials A to C.
【００１８】また、図２で示した材料Ｄは、基体１の表
面に純Ａｇから成る表面層３が、直接、形成された層構
造になっていて、その表面層３の厚みは１〜１０μｍに
設定されている。これらの表面層３は、厚み制御や材料
の製造管理が容易であるということから電気めっき法を
適用して形成される。The material D shown in FIG. 2 has a layer structure in which the surface layer 3 made of pure Ag is directly formed on the surface of the substrate 1, and the thickness of the surface layer 3 is 1 to 10 μm. Is set to These surface layers 3 are formed by applying an electroplating method because the thickness control and the production control of the material are easy.
【００１９】例えば、材料Ａ〜Ｃの場合は、公知のＳｎ
めっき浴やＳｎ合金めっき浴に基体を浸漬して電気めっ
きを行い、また材料Ｄの場合はシアン化銀やシアン化カ
リのめっき浴や市販のノーシアンめっき浴を用いて表面
層を形成することができる。また、Ｓｎ−Ａｇ合金、Ｓ
ｎ−Ｂｉ合金の表面層を形成する場合には、例えばＡｇ
やＢｉを一旦基体の表面にめっきしたのちその上にＳｎ
めっきを行い、更に、それに続けて加熱処理を施して合
金化することもできる。この逆の方法で合金化を意図す
ると、表面層の表面ムラや表面変色が発生するので望ま
しくない。For example, in the case of materials A to C, a known Sn
Electroplating is performed by immersing the substrate in a plating bath or Sn alloy plating bath, and in the case of material D, a surface layer can be formed using a silver cyanide or potassium cyanide plating bath or a commercially available cyanide-free plating bath. it can. In addition, Sn-Ag alloy, S
When forming a surface layer of an n-Bi alloy, for example, Ag
Or Bi once plated on the surface of the substrate and then Sn
Plating can be performed, and subsequently, a heat treatment can be performed to form an alloy. If alloying is intended by the reverse method, surface unevenness and surface discoloration of the surface layer occur, which is not desirable.
【００２０】なお、材料Ａ，Ｂ、Ｃのように基体１の表
面にＳｎやＳｎ合金をめっきして表面層を形成すると、
更に続けて加熱処理を行うと、基体表面の主成分である
Ｃｕと表面層の主成分であるＳｎとの相互拡散により、
両者の界面には図１で示した中間層２が形成され、基体
１と表面層３との密着性が確保される。この中間層２
は、基体１側に位置するＣｕ3Ｓｎ（ε相）層２ａと表
面層３側に位置するＣｕ6Ｓｎ5（η’相）層２ｂとの積
層構造になっている。When a surface layer is formed by plating Sn or a Sn alloy on the surface of the substrate 1 like the materials A, B, and C,
When heat treatment is further continued, mutual diffusion of Cu, which is the main component of the substrate surface, and Sn, which is the main component of the surface layer,
The intermediate layer 2 shown in FIG. 1 is formed at the interface between them, and the adhesion between the substrate 1 and the surface layer 3 is ensured. This middle layer 2
Has a laminated structure of a Cu 3 Sn (ε phase) layer 2a located on the base 1 side and a Cu 6 Sn 5 (η ′ phase) layer 2b located on the surface layer 3 side.
【００２１】これらの層は、基体表面側ではＣｕリッチ
の相になって基体表面との密着性の確保に寄与し、また
表面層側ではＳｎリッチな相になって表面層との密着性
の確保に寄与し、両層２ａ，２ｂの界面では２つの相が
混在する状態になることにより、全体で基体表面と表面
層との密着性を確保しているのである。しかし、材料Ｄ
の場合は、基体１と純Ａｇから成る表面層３との間では
上記したような各成分間での相互拡散は起こりづらいの
で、図２で示したような２層構造になる。These layers form a Cu-rich phase on the substrate surface side and contribute to ensuring adhesion to the substrate surface, and a Sn-rich phase on the surface layer side to improve adhesion to the surface layer. This contributes to the securing, and the two phases are mixed at the interface between the two layers 2a and 2b, so that the adhesion between the substrate surface and the surface layer is secured as a whole. However, material D
In the case of (1), the above-described mutual diffusion between the components is unlikely to occur between the substrate 1 and the surface layer 3 made of pure Ag, so that a two-layer structure as shown in FIG. 2 is obtained.
【００２２】ここで、材料Ａ〜Ｃにおいて、表面層３の
厚みが薄すぎると、表面層の形成から例えば実装使用に
至るまでの間に、ＣｕとＳｎの相互拡散が進行してＣｕ
3Ｓｎ（ε相）とＣｕ6Ｓｎ5（η’相）の生成量が増加
してＳｎ−Ｂｉ系はんだを用いたはんだ接合時における
濡れ性の確保が困難になるだけでなく、材料の耐熱性低
下を招くようになるので、その厚みは１μｍ以上である
ことが必要である。しかしながら、その厚みを２０μｍ
より厚くしても性能は飽和して無駄になるだけでなく、
徒らに製造コストの上昇を招くようになるので、厚みの
上限は２０μｍに設定される。Here, in the materials A to C, if the thickness of the surface layer 3 is too thin, the interdiffusion of Cu and Sn progresses during the period from the formation of the surface layer to, for example, the mounting use, and Cu
The amount of 3 Sn (ε phase) and Cu 6 Sn 5 (η ′ phase) generated increases, which not only makes it difficult to secure wettability at the time of soldering using Sn—Bi solder, but also makes the material heat resistant. It is necessary that the thickness is 1 μm or more, since this causes a reduction in the properties. However, its thickness is 20 μm
Even if it is thicker, the performance will not only be saturated and wasted,
Unnecessarily, the production cost is increased, so the upper limit of the thickness is set to 20 μm.
【００２３】また、材料Ｄの場合、表面層３の厚みが１
μｍより薄くなると、実使用までの期間が長期になる場
合、表面層（純Ａｇ層）の下の基体表面の酸化が進んで
酸化銅が表面に表出してきて、やはりはんだ濡れ性の低
下を招く。また、表面層（純Ａｇ層）の厚みをあまり厚
くすると、製造コストが上昇するとともに、はんだ接合
部におけるＡｇ量が多くなって、当該接合部の硫化によ
る変色と腐食を招きやすくなる。このようなことから、
材料Ｄにおける表面層（純Ａｇ層）の厚みは１〜１０μ
ｍに設定される。In the case of the material D, the thickness of the surface layer 3 is 1
When the thickness is smaller than μm, when the period until actual use becomes long, oxidation of the substrate surface under the surface layer (pure Ag layer) proceeds, and copper oxide appears on the surface, which also reduces the solder wettability. Invite. On the other hand, if the thickness of the surface layer (pure Ag layer) is too large, the production cost increases, and the amount of Ag in the solder joint increases, and discoloration and corrosion due to sulfuration of the joint tend to occur. From such a thing,
The thickness of the surface layer (pure Ag layer) in the material D is 1 to 10 μm.
m.
【００２４】材料Ａは、その表面層が純Ｓｎで構成され
ているので、Ｓｎ−Ｂｉ系はんだを用いて相手材と接合
したときに、形成された接合部においてはＢｉ濃度が希
釈された状態になり、その結果、当該接合部の耐熱性は
向上する。材料Ｂの表面層を構成するＳｎ−Ａｇ合金と
しては、共晶組成であるＳｎ−３.５％Ａｇの融点は２
２１℃であるということから、Ａｇ含有量が３.５重量
％前後のものが好ましい。具体的には、Ａｇ含有量は１
〜４重量％であればよい。Since the surface layer of the material A is made of pure Sn, when the material A is joined to a counterpart material using Sn-Bi solder, the Bi concentration in the formed joint is reduced. As a result, the heat resistance of the joint is improved. As a Sn-Ag alloy constituting the surface layer of the material B, the melting point of Sn-3.5% Ag having a eutectic composition is 2
Since the temperature is 21 ° C., those having an Ag content of about 3.5% by weight are preferred. Specifically, the Ag content is 1
-4% by weight.
【００２５】また、Ｓｎ−Ａｇ合金としては、Ａｇ3Ｓ
ｎ（ε相）化合物を含有しているものが好ましい。この
Ａｇ3Ｓｎ（ε相）化合物は、表面層のクリープ特性を
含む耐熱性を高め、また同時に、表面層の主成分である
Ｓｎと基体表面の主成分であるＣｕとの相互拡散を抑制
する機能を発揮するからである。しかし、このＡｇ3Ｓ
ｎ（ε相）化合物があまり多量に表面層に含有されてい
ると、融点の上昇を招くのでその含有量はＡｇ換算量に
して５重量％以下に設定することが好ましい。Further, as the Sn—Ag alloy, Ag 3 S
Those containing an n (ε phase) compound are preferred. This Ag 3 Sn (ε phase) compound enhances the heat resistance including the creep characteristic of the surface layer, and at the same time, suppresses the interdiffusion between Sn, which is the main component of the surface layer, and Cu, which is the main component of the substrate surface. This is because they perform their functions. However, this Ag 3 S
If the surface layer contains an n (ε phase) compound in an excessively large amount, the melting point is increased. Therefore, the content is preferably set to 5% by weight or less in terms of Ag.
【００２６】また、材料Ｃの表面層を構成するＳｎ−Ｂ
ｉ合金の場合、共晶組成であるＳｎ−５７％Ｂｉまで
は、Ｂｉ含有量の増加に応じて合金の液相線は低下して
いく。しかしながら、このことは、耐熱性の低下という
ことを意味する。またＢｉ含有量が５重量％を超えると
材料の曲げ加工性が悪化して割れの発生が起こりやすく
なる。更に，Ｓｎ−Ｂｉ系はんだを用いて接合した接合
部におけるＢｉ量が多くなり、接合部の耐熱性の低下
や、高温環境下における接合信頼性の低下などを引き起
こすようになる。このようなことから、表面層を構成す
るＳｎ−Ｂｉ合金におけるＢｉ含有量は１〜１０重量
％、とくに１〜５重量％に規定することが好ましい。Further, Sn-B constituting the surface layer of the material C
In the case of the i-alloy, the liquidus of the alloy decreases as the Bi content increases up to the eutectic composition of Sn-57% Bi. However, this means a decrease in heat resistance. On the other hand, if the Bi content exceeds 5% by weight, the bending workability of the material deteriorates, and cracks tend to occur. Further, the amount of Bi in the joint portion joined by using the Sn-Bi-based solder increases, which causes a decrease in heat resistance of the joint portion and a decrease in joint reliability in a high-temperature environment. For this reason, the content of Bi in the Sn—Bi alloy constituting the surface layer is preferably set to 1 to 10% by weight, particularly preferably 1 to 5% by weight.
【００２７】なお、この材料Ｃの場合、接合に用いるは
んだもＳｎ−Ｂｉ系はんだであるため、接合部の耐熱性
に不都合を生ずるということはない。次に、材料Ｅにつ
いて説明する。この材料Ｅは、材料Ａ〜Ｄにおける表面
層を構成する材料に、更にＣｕを０.２〜３重量％含有
せしめた材料で表面層が形成されているものである。In the case of the material C, since the solder used for joining is also a Sn-Bi solder, there is no problem with the heat resistance of the joint. Next, the material E will be described. This material E is a material in which Cu is added to the material constituting the surface layer in the materials A to D to further contain 0.2 to 3% by weight of the surface layer.
【００２８】この材料Ｅは、Ｓｎ−Ｂｉ系はんだを用い
て相手材とはんだ接合したり、回路基板に実装（基板電
極部とはんだ接合）したりしたときに、材料Ａ〜Ｄの場
合に比べて、接合部の高温環境下における接合信頼性が
より向上するという効果を発揮する。これは、表面層に
Ｃｕが含有されていることにより、表面層のクリープ特
性を含む耐熱性が向上し、また表面層の主成分であるＳ
ｎやＡｇと基体表面の主成分であるＣｕや他の構成元素
との相互拡散に基づく合金化が抑制されて高温環境下に
おける接合部の経時劣化が進行しづらくなったためであ
る。When this material E is solder-bonded to a counterpart material using Sn-Bi solder or mounted on a circuit board (solder-bonded to the board electrode portion), compared to the materials A to D Thus, the effect that the joining reliability in the high temperature environment of the joining portion is further improved is exhibited. This is because, since Cu is contained in the surface layer, heat resistance including creep characteristics of the surface layer is improved, and S which is a main component of the surface layer is improved.
This is because alloying based on interdiffusion between n or Ag and Cu or another constituent element that is a main component of the substrate surface is suppressed, and deterioration with time of the bonded portion in a high-temperature environment becomes difficult to progress.
【００２９】しかしながら、Ｃｕ含有量が０.２重量％
より少ない場合は上記した効果は発現せず、また３重量
％より多くなると、表面層が純Ｓｎ層やＳｎ合金層であ
る場合は、その液相線が過度に高くなって例えばリフロ
ー処理時やウェーブソルダリング時に不均一な凝固接合
が起こるようになり、しかも表面のＣｕ酸化が起こって
はんだ濡れ性の低下や耐食性の低下なども起こりやすく
なる。このようなことから、Ｃｕ含有量は０.２〜３重
量％に設定される。However, the Cu content is 0.2% by weight.
When the amount is less than the above, the above-mentioned effect is not exhibited. When the amount is more than 3% by weight, when the surface layer is a pure Sn layer or an Sn alloy layer, its liquidus line becomes excessively high, for example, during a reflow treatment. Non-uniform solidification bonding occurs at the time of wave soldering, and furthermore, Cu oxidation of the surface occurs, which tends to cause a decrease in solder wettability and a decrease in corrosion resistance. For these reasons, the Cu content is set to 0.2 to 3% by weight.
【００３０】表面層にＣｕを含有せしめる場合は、表面
層の形成に用いるめっき浴に更に所定量のＣｕイオンを
含有せしめて電気めっきを行えばよい。通常、めっき浴
にＣｕイオンを０.２〜５０ｐｐｍ程度含有せしめれ
ば、表面層におけるＣｕ含有量を上記した値にすること
ができる。なお、本発明の材料の場合、表面層は、上記
したように純Ｓｎ層（材料Ａの場合）、Ｓｎ−Ａｇ合金
層（材料Ｂの場合）、Ｓｎ−Ｂｉ合金層（材料Ｃの場
合）、純Ａｇ層（材料Ｄの場合）のそれぞれ単独で形成
してもよいが、これらＳｎ、Ｓｎ−Ａｇ合金、Ｓｎ−Ｂ
ｉ合金、Ａｇのうち２種類を適宜に選択し、これらを用
いて２層構造の表面層にしてもよい。その場合には接合
部の高温環境下における信頼性が単独使用の場合よりも
向上することがある。When Cu is contained in the surface layer, the plating bath used for forming the surface layer may further contain a predetermined amount of Cu ions, and electroplating may be performed. Usually, if the plating bath contains about 0.2 to 50 ppm of Cu ions, the Cu content in the surface layer can be set to the above-mentioned value. In the case of the material of the present invention, the surface layer is a pure Sn layer (for material A), an Sn-Ag alloy layer (for material B), and a Sn-Bi alloy layer (for material C) as described above. , Pure Ag layer (in the case of material D) may be formed alone, but these Sn, Sn-Ag alloy, Sn-B
Two types may be appropriately selected from i-alloy and Ag, and these may be used to form a surface layer having a two-layer structure. In that case, the reliability of the joint in a high-temperature environment may be improved as compared with the case where the joint is used alone.
【００３１】また、本発明の材料は、上記したようにめ
っき法で層構造を形成したのち、更に非酸化性雰囲気や
還元性雰囲気下でリフロー処理を施すと、例えば表面層
におけるウイスカの生成を抑制することができるととも
に、表面層における各成分の拡散性も低下し、全体の耐
熱性向上、ひいては接合部の信頼性を高めることができ
る。Further, the material of the present invention, after forming a layer structure by the plating method as described above, is further subjected to a reflow treatment in a non-oxidizing atmosphere or a reducing atmosphere, for example, the formation of whiskers in the surface layer. In addition to being able to suppress, the diffusibility of each component in the surface layer is also reduced, so that the overall heat resistance can be improved and the reliability of the joint can be increased.
【００３２】本発明の電気・電子部品は、上記した材料
Ａ〜Ｅのいずれかを用いたものであって、具体的には、
例えば電極やランドが上記材料で形成されているもので
ある。また、本発明の電気・電子部品実装基板は、上記
した材料Ａ〜Ｅのいずれかを用いて各種の電気・電子部
品を製造し、それを実装したものである。The electric / electronic component of the present invention uses any one of the above-mentioned materials A to E.
For example, the electrodes and lands are formed of the above-mentioned materials. Further, the electric / electronic component mounting board of the present invention is manufactured by manufacturing various electric / electronic components using any of the above-mentioned materials A to E and mounting them.
【００３３】本発明のはんだ接合方法は、上記した材料
Ａ〜Ｅのいずれか、またはそれらを用いた電気・電子部
品と、相手材もしくは回路基板とをはんだ接合するとき
に、接合用はんだ材料としてＢｉ含有量が２重量％以上
のＳｎ基合金はんだを用いることを特徴とする。したが
って、本発明のはんだ接合部はＰｂフリー状態にあり、
また前記したように当該接合部の接合信頼性は高い。The solder joining method of the present invention is used as a joining solder material when any one of the above-mentioned materials A to E or an electric / electronic component using them and a mating material or a circuit board are joined by soldering. It is characterized by using a Sn-based alloy solder having a Bi content of 2% by weight or more. Therefore, the solder joint of the present invention is in a Pb-free state,
As described above, the bonding reliability of the bonding portion is high.
【００３４】このようなことから、本発明のはんだ接合
方法により、近年および今後の高温環境用途の電気・電
子部品実装基板を実用化することが可能となる。From the above, according to the solder bonding method of the present invention, it is possible to put into practical use an electric / electronic component mounting board for use in a high-temperature environment in recent years and in the future.
【００３５】[0035]
【実施例】実施例１〜１２、比較例１〜４ 線径０.５ｍｍのＣｕ被覆鋼線を、カソード脱脂槽、酸
洗槽、めっき槽に順次走行せしめて、表１で示しためっ
き層が表面層として形成されているリード線を製造し
た。EXAMPLES Examples 1 to 12 and Comparative Examples 1 to 4 A Cu-coated steel wire having a wire diameter of 0.5 mm was sequentially moved to a cathode degreasing tank, an acid pickling tank, and a plating tank. Was manufactured as a surface layer.
【００３６】各表面層のうち、純Ｓｎ層とＣｕ3Ｓｎ
（ε相）層やＣｕ6Ｓｎ5（η'相）層に対しては、アノ
ード溶解法を適用して、そのときの溶解電位と溶解電気
量から、またその他の層に対しては蛍光Ｘ線によりそれ
ぞれの厚みを測定した。また、表面層の組成は電子線マ
イクロアナライザのＺＡＦ補正法で定量分析し、更にＸ
線回折法により、Ｃｕ被覆鋼線と表面層との界面におけ
るＣｕ3Ｓｎ（ε相）層とＣｕ6Ｓｎ5（η'相）層の有無
を観測した。その結果を表１に示した。Of each surface layer, a pure Sn layer and Cu 3 Sn
The anodic dissolution method is applied to the (ε phase) layer and the Cu 6 Sn 5 (η ′ phase) layer, and the fluorescent X Each thickness was measured with a line. The composition of the surface layer was quantitatively analyzed by a ZAF correction method using an electron beam microanalyzer.
The presence or absence of a Cu 3 Sn (ε phase) layer and a Cu 6 Sn 5 (η ′ phase) layer at the interface between the Cu-coated steel wire and the surface layer was observed by a line diffraction method. The results are shown in Table 1.
【００３７】また、各リード線に、１５０℃の大気中で
５０時間の加熱処理を施したのち、ウエッティングバラ
ンス法ではんだ濡れ性を測定した。はんだ濡れ性の測定
は（株）レスカ製の動的濡れ試験器を用い、はんだとし
ては２３０℃に保持したＳｎ−３８％Ｐｂ共晶はんだ
を、フラックスとしてはＲＭＡタイプのものを用い、試
験の浸漬深さ２ｍｍ、浸漬速度１０ｍｍ／秒の条件で行
って濡れ時間（ゼロクロス時間）を測定した。上記した
加熱前後における測定値を表１に示した。Each lead wire was subjected to a heat treatment in the air at 150 ° C. for 50 hours, and then the solder wettability was measured by a wetting balance method. The measurement of solder wettability was performed using a dynamic wetting tester manufactured by Resca Co., Ltd., and a Sn-38% Pb eutectic solder maintained at 230 ° C. was used as a solder, and an RMA type flux was used as a flux. The immersion depth was 2 mm, the immersion speed was 10 mm / sec, and the wetting time (zero cross time) was measured. The measured values before and after the above-mentioned heating are shown in Table 1.
【００３８】[0038]
【表１】 [Table 1]
【００３９】一般に、はんだゼロクロス時間は１秒以下
であることが望ましいものとされている。このことを考
え、また表面層の形成直後から実使用までの過程でＣｕ
3Ｓｎ（ε相）とＣｕ6Ｓｎ5（η'相）の成長や表面酸化
の発生を考えると、表１から明らかなように、表面層の
厚みは１μｍ以上にすべきである。また厚みの上限は２
０μｍに設定すれば充分である。In general, it is desirable that the solder zero crossing time is 1 second or less. Considering this, Cu is required in the process from immediately after formation of the surface layer to actual use.
Considering the growth of 3 Sn (ε phase) and Cu 6 Sn 5 (η ′ phase) and the occurrence of surface oxidation, as is clear from Table 1, the thickness of the surface layer should be 1 μm or more. The upper limit of the thickness is 2
It is sufficient to set it to 0 μm.
【００４０】実施例１３〜２６、比較例５〜１２ 厚み０.４ｍｍのタフピッチ銅板に、カソード脱脂、酸
洗処理を行ったのち、表２で示した第１めっき浴、第２
めっき浴、および第３めっき浴で順次めっき処理を行
い、表２で示した層構造のめっき層を形成した。なお、
めっき浴にＣｕイオンを含有せしめた事例も実施し、ま
た、得られた材料の１部については表２で示した条件の
リフロー処理を行った。Examples 13 to 26, Comparative Examples 5 to 12 A 0.4 mm thick tough pitch copper plate was subjected to cathodic degreasing and pickling treatments, followed by a first plating bath and a second plating bath shown in Table 2.
Plating was sequentially performed in the plating bath and the third plating bath to form a plating layer having a layer structure shown in Table 2. In addition,
A case in which Cu ions were contained in the plating bath was also implemented, and a part of the obtained material was subjected to a reflow treatment under the conditions shown in Table 2.
【００４１】表面層の組成と厚みは、電子線マイクロア
ナライザのＺＡＦ補正法による定量分析、蛍光Ｘ線測定
を適用してそれぞれ測定した。なお、Ｓｎ−Ａｇ合金を
めっきして形成した表面層からは、いずれもＡｇ3Ｓｎ
（ε相）化合物が検出された。以上の結果を表２〜表４
に示した。The composition and thickness of the surface layer were measured by applying a quantitative analysis by a ZAF correction method using an electron beam microanalyzer and X-ray fluorescence measurement. In addition, from the surface layer formed by plating the Sn—Ag alloy, Ag 3 Sn
(Ε phase) Compound was detected. Table 2 to Table 4 show the above results.
It was shown to.
【００４２】[0042]
【表２】 [Table 2]
【００４３】[0043]
【表３】 [Table 3]
【００４４】[0044]
【表４】 [Table 4]
【００４５】得られた各材料を２５ｍｍ角に切出し、そ
の試料に、直径３ｍｍのＣｕ被覆鋼線を各種のはんだで
接合した。このとき、用いたはんだは次のような組成の
ものであった。なお、はんだ接合部の大きさは直径６ｍ
ｍと一定にした。 はんだ１：Ｓｎ−２％Ｂｉ−３.５％Ａｇ−３％Ｉｎ、 はんだ２：Ｓｎ−７.５％Ｂｉ−２％Ａｇ−０.７５％Ｃ
ｕ、 はんだ３：Ｓｎ−５７％Ｂｉ、 はんだ４：Ｓｎ−１％Ｂｉ−３％Ａｇ、 はんだ５：Ｓｎ−３.５％Ａｇ、 はんだ６：Ｓｎ−３８％Ｐｂ（共晶）。Each of the obtained materials was cut into a 25 mm square, and a Cu-coated steel wire having a diameter of 3 mm was joined to the sample with various solders. At this time, the used solder had the following composition. The size of the solder joint is 6 m in diameter.
m. Solder 1: Sn-2% Bi-3.5% Ag-3% In, Solder 2: Sn-7.5% Bi-2% Ag-0.75% C
u, Solder 3: Sn-57% Bi, Solder 4: Sn-1% Bi-3% Ag, Solder 5: Sn-3.5% Ag, Solder 6: Sn-38% Pb (eutectic).
【００４６】ついで、室温下において、各試料とＣｕ被
覆鋼線との接合強度（Ｔ0：Ｎ／ｍｍ2）を測定した。そ
してはんだ接合材料に対し、大気中において温度１５０
℃で表５〜表１２で示した時間の劣化促進処理を施し、
そのときの各試料とＣｕ被覆鋼線との接合強度（Ｔ1：
Ｎ／ｍｍ2）を測定し、（Ｔ0−Ｔ1）×１００／Ｔ0を算
出してはんだ接合部の劣化率（％）を測定した。Next, the bonding strength (T 0 : N / mm 2 ) between each sample and the Cu-coated steel wire was measured at room temperature. Then, the solder bonding material is subjected to a temperature of 150 in air.
Subjected to the degradation promotion treatment at the temperature shown in Tables 5 to 12,
At that time, the bonding strength between each sample and the Cu-coated steel wire (T 1 :
N / mm 2 ), and (T 0 −T 1 ) × 100 / T 0 was calculated to determine the deterioration rate (%) of the solder joint.
【００４７】はんだ１、はんだ２、はんだ３を用いた場
合の結果を一括して表５〜表８に示し、はんだ４、はん
だ５、はんだ６を用いた場合の結果を表９〜表１２に示
した。強度と劣化率を勘案して接合部の信頼性の概略評
価も併記した。表中、○印は、１）Ｔ0が１５Ｎ／ｍｍ2
を超え、かつ１５０℃で１０００時間の劣化促進処理後
の劣化率が４０％未満であるか、２）Ｔ0が２０Ｎ／ｍ
ｍ2を超え、かつ１５０℃で１０００時間の劣化促進処
理後の劣化率が５０％未満であるか、または、３）Ｔ0
が２５Ｎ／ｍｍ2を超え、かつ１５０℃で１０００時間
の劣化促進処理後の劣化率が５５％未満であるかのいず
れかの場合を示し、△印は、１５０℃で１０００時間の
劣化促進処理後の強度が１０Ｎ／ｍｍ2以上で、かつ上
記○印に該当しない場合を示し、×印は、１５０℃で１
０００時間の劣化促進処理後の強度が１０Ｎ／ｍｍ2未
満である場合を示す。The results when solder 1, solder 2, and solder 3 were used are collectively shown in Tables 5 to 8, and the results when solder 4, solder 5, and solder 6 were used are shown in Tables 9 to 12. Indicated. In consideration of the strength and the deterioration rate, an outline evaluation of the joint reliability is also shown. In the table, circles indicate 1) T 0 is 15 N / mm 2.
Is greater than 40% and the degradation rate after the degradation promotion treatment at 150 ° C. for 1000 hours is less than 40%, or 2) T 0 is 20 N / m.
m 2 and the degradation rate after the degradation promotion treatment at 150 ° C. for 1000 hours is less than 50%, or 3) T 0
Is greater than 25 N / mm 2 and the rate of deterioration after the deterioration promotion treatment at 150 ° C. for 1000 hours is less than 55%. The subsequent strength is 10 N / mm 2 or more and does not correspond to the above-mentioned ○ mark.
The case where the strength after the deterioration promotion treatment for 000 hours is less than 10 N / mm 2 is shown.
【００４８】[0048]
【表５】 [Table 5]
【００４９】[0049]
【表６】 [Table 6]
【００５０】[0050]
【表７】 [Table 7]
【００５１】[0051]
【表８】 [Table 8]
【００５２】[0052]
【表９】 [Table 9]
【００５３】[0053]
【表１０】 [Table 10]
【００５４】[0054]
【表１１】 [Table 11]
【００５５】[0055]
【表１２】 [Table 12]
【００５６】表５〜表１２から明らかなように、本発明
の材料は、いずれも、Ｂｉ含有量が２重量％以上である
Ｓｎ−Ｂｉ系はんだを用いて相手材にはんだ接合したと
きに、その接合部を高温環境下に長時間曝しても、当該
接合部の接合強度の劣化率は小さく、信頼性の高い接合
部を形成することができる。とくに、表面層にＣｕを含
有せしめた材料や、表面層を２層構造の合金層で形成し
た材料の場合は、Ｓｎ−Ｂｉ系はんだを用いたときの接
合部の信頼性が更に向上している。As is clear from Tables 5 to 12, all of the materials of the present invention can be obtained by using a Sn-Bi solder having a Bi content of 2% by weight or more when soldered to a mating material. Even if the joint is exposed to a high-temperature environment for a long time, the rate of deterioration of the joint strength of the joint is small and a highly reliable joint can be formed. In particular, in the case of a material in which Cu is contained in the surface layer or a material in which the surface layer is formed of an alloy layer having a two-layer structure, the reliability of the joint when Sn-Bi solder is used is further improved. I have.
【００５７】[0057]
【発明の効果】以上の説明で明らかなように、本発明の
材料、およびそれを用いた電気・電子部品は、Ｐｂフリ
ーのはんだとして使用されはじめているＢｉ含有量が２
重量％以上のＳｎ基合金はんだで相手材に接合したとき
や、回路基板などに実装したときに、その接合部の高温
環境下における接合信頼性を確保することができる。As is clear from the above description, the material of the present invention and the electric / electronic parts using the same have a Bi content of 2 which has begun to be used as a Pb-free solder.
When bonded to a counterpart material with Sn-based alloy solder of not less than weight%, or when mounted on a circuit board or the like, the bonding reliability of the bonded portion in a high temperature environment can be ensured.
【００５８】したがって、本発明の材料を用いて各種の
電気・電子部品を製造し、それを基板実装することによ
り、環境汚染もなく、高温環境下で使用される各種電気
・電子部品実装基板を製造することができ、その工業的
価値は大である。Therefore, by manufacturing various electric / electronic parts using the material of the present invention and mounting them on a substrate, various electric / electronic parts mounting boards used under a high temperature environment without environmental pollution can be obtained. It can be manufactured and its industrial value is great.
【図１】本発明の材料の層構造を示す断面図である。FIG. 1 is a sectional view showing a layer structure of a material of the present invention.
【図２】本発明の別の材料の層構造を示す断面図であ
る。FIG. 2 is a sectional view showing a layer structure of another material of the present invention.
１ 基体 ２ 中間層 ２ａ Ｃｕ3Ｓｎ（ε相）層 ２ｂ Ｃｕ6Ｓｎ5（η'相）層 ３ 表面層REFERENCE SIGNS LIST 1 base 2 intermediate layer 2a Cu 3 Sn (ε phase) layer 2b Cu 6 Sn 5 (η ′ phase) layer 3 surface layer
───────────────────────────────────────────────────── フロントページの続き (72)発明者 田中 仁志 東京都千代田区丸の内２丁目６番１号 古 河電気工業株式会社内 Ｆターム(参考） 4K024 AA07 AA10 AA15 AA16 AA21 AB01 AB04 BA09 BB09 BB11 DB01 GA01 4K044 AA06 AB10 BA10 BB01 BB05 BC05 BC08 CA18 CA62 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hitoshi Tanaka 2-6-1 Marunouchi, Chiyoda-ku, Tokyo Furukawa Electric Co., Ltd. F-term (reference) 4K024 AA07 AA10 AA15 AA16 AA21 AB01 AB04 BA09 BB09 BB11 DB01 GA01 4K044 AA06 AB10 BA10 BB01 BB05 BC05 BC08 CA18 CA62
Claims (8)
ら成る基体の前記表面に、Ｃｕ3Ｓｎ（ε相）層とＣｕ6
Ｓｎ5（η'相）層とがこの順序で積層されて成る中間層
を介して、純Ｓｎから成る厚み１〜２０μｍの表面層が
形成されていることを特徴とする、Ｓｎ−Ｂｉ系はんだ
を接合して用いられる電気・電子部品用材料。1. A method according to claim 1, wherein a Cu 3 Sn (ε phase) layer and a Cu 6
A Sn—Bi-based solder, wherein a surface layer made of pure Sn and having a thickness of 1 to 20 μm is formed via an intermediate layer formed by laminating a Sn 5 (η ′ phase) layer in this order. For electrical and electronic parts used by bonding
ら成る基体の前記表面に、Ｃｕ3Ｓｎ（ε相）層とＣｕ6
Ｓｎ5（η'相）層とがこの順序で積層されて成る中間層
を介して、Ｓｎ−Ａｇ合金から成る厚み１〜２０μｍの
表面層が形成されていることを特徴とする、Ｓｎ−Ｂｉ
系はんだを接合して用いられる電気・電子部品用材料。2. A Cu 3 Sn (ε phase) layer and a Cu 6 Sn
Via an intermediate layer and a Sn 5 (η 'phase) layer formed by laminating in this order, wherein the surface layer of 1~20μm thickness consisting of Sn-Ag alloy is formed, Sn-Bi
Materials for electric and electronic parts used by joining series solder.
ら成る基体の前記表面に、Ｃｕ3Ｓｎ（ε相）層とＣｕ6
Ｓｎ5（η'相）層とがこの順序で積層されて成る中間層
を介して、Ｓｎ−Ｂｉ合金から成る厚み１〜２０μｍの
表面層が形成されていることを特徴とする、Ｓｎ−Ｂｉ
系はんだを接合して用いられる電気・電子部品用材料。3. A Cu 3 Sn (ε phase) layer and a Cu 6 Sn
A Sn-Bi alloy, wherein a surface layer made of a Sn-Bi alloy and having a thickness of 1 to 20 µm is formed via an intermediate layer formed by laminating a Sn 5 (η 'phase) layer in this order.
Materials for electric and electronic parts used by joining series solder.
ら成る基体の前記表面に、純Ａｇから成る厚み１〜１０
μｍの表面層が形成されていることを特徴とする、Ｓｎ
−Ｂｉ系はんだを接合して用いられる電気・電子部品用
材料。4. A substrate having at least a surface made of Cu or a Cu alloy and having a thickness of 1 to 10
Sn, wherein a surface layer of μm is formed.
-Materials for electric and electronic parts used by joining Bi-based solder.
おける表面層には、Ｃｕが０.２〜３重量％含有されて
いることを特徴とする、Ｓｎ−Ｂｉ系はんだを接合して
用いられる電気・電子部品用材料。5. The Sn—Bi solder according to claim 1, wherein the surface layer of the electric / electronic component material according to claim 1 contains 0.2 to 3% by weight of Cu. Used for electrical and electronic parts.
品用材料を用いたことを特徴とする電気・電子部品。6. An electric / electronic component using the electric / electronic component material according to claim 1.
品用材料を用いたことを特徴とする電気・電子部品実装
基板。7. An electric / electronic component mounting board, wherein the electric / electronic component material according to claim 1 is used.
品用材料またはそれらを用いた電気・電子部品を、Ｂｉ
含有量が２重量％以上であるＳｎ−Ｂｉ系はんだを用い
て相手材もしくは回路基板に接合または実装することを
特徴とするはんだ接合または実装方法。8. The electric / electronic component material according to claim 1 or an electric / electronic component using them,
A solder joining or mounting method characterized by joining or mounting to a counterpart material or a circuit board using a Sn-Bi-based solder having a content of 2% by weight or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22591298A JP2000054189A (en) | 1998-08-10 | 1998-08-10 | MATERIAL FOR ELECTRIC AND ELECTRONIC PARTS USED BY BONDING WITH Sn-Bi-BASED SOLDER, ELECTRIC AND ELECTRONIC PARTS USING IT, ELECTRIC AND ELECTRONIC PARTS-MOUNTED SUBSTRATE, AND SOLDER BONDING, OR MOUNTING METHOD USING IT |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22591298A JP2000054189A (en) | 1998-08-10 | 1998-08-10 | MATERIAL FOR ELECTRIC AND ELECTRONIC PARTS USED BY BONDING WITH Sn-Bi-BASED SOLDER, ELECTRIC AND ELECTRONIC PARTS USING IT, ELECTRIC AND ELECTRONIC PARTS-MOUNTED SUBSTRATE, AND SOLDER BONDING, OR MOUNTING METHOD USING IT |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000054189A true JP2000054189A (en) | 2000-02-22 |
Family
ID=16836841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22591298A Pending JP2000054189A (en) | 1998-08-10 | 1998-08-10 | MATERIAL FOR ELECTRIC AND ELECTRONIC PARTS USED BY BONDING WITH Sn-Bi-BASED SOLDER, ELECTRIC AND ELECTRONIC PARTS USING IT, ELECTRIC AND ELECTRONIC PARTS-MOUNTED SUBSTRATE, AND SOLDER BONDING, OR MOUNTING METHOD USING IT |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000054189A (en) |
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