JP2000036550A - Ceramics circuit substrate for power semiconductor module - Google Patents
Ceramics circuit substrate for power semiconductor moduleInfo
- Publication number
- JP2000036550A JP2000036550A JP10204935A JP20493598A JP2000036550A JP 2000036550 A JP2000036550 A JP 2000036550A JP 10204935 A JP10204935 A JP 10204935A JP 20493598 A JP20493598 A JP 20493598A JP 2000036550 A JP2000036550 A JP 2000036550A
- Authority
- JP
- Japan
- Prior art keywords
- power semiconductor
- semiconductor module
- ceramic substrate
- circuit board
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、電力用のパワー
半導体モジュールに採用するセラミックス回路基板に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic circuit board used for a power semiconductor module for electric power.
【０００２】[0002]
【従来の技術】頭記したパワー半導体モジュール用のセ
ラミックス回路基板として、放熱性，電気絶縁性，高周
波数特性の優れたアルミナ系，窒化アルミニウムなどの
セラミックス基板の表面にに導体パターンとなる銅回路
板を接合し、同じく裏面に銅板を接合してなるセラミッ
クス回路基板が広く採用されている。2. Description of the Related Art As a ceramic circuit board for a power semiconductor module described above, a copper circuit which becomes a conductor pattern on the surface of a ceramic substrate made of alumina, aluminum nitride, etc. having excellent heat dissipation, electrical insulation and high frequency characteristics. 2. Description of the Related Art A ceramic circuit board formed by joining plates and also joining a copper plate to the back surface has been widely used.
【０００３】このセラミックス回路基板は、銅ベース板
（ヒートシンク板）に搭載して半田付けし、セラミック
ス回路基板の銅回路板上に複数個のパワー半導体素子な
どを実装した上で外囲樹脂ケース，外部導出端子を組合
せてパワー半導体モジュールの製品を構成している。[0003] This ceramic circuit board is mounted on a copper base plate (heat sink plate) and soldered, a plurality of power semiconductor elements are mounted on the copper circuit board of the ceramic circuit board, and an outer resin case, A power semiconductor module product is configured by combining external lead-out terminals.
【０００４】[0004]
【発明が解決しようとする課題】ところで、セラミック
ス回路基板は放熱性，電気絶縁性などの面で優れた特性
を有するものの、セラミックス基板自身は脆くて曲げ強
度が小さく、昨今のセラミックス基板の薄形化によりパ
ワー半導体モジュール製品としての実使用状態で通電制
御に伴うヒートサイクル，放熱フィンへ取付ける際のね
じ締結などに伴って熱的，機械的なストレスが加わる
と、その応力が集中する箇所でセラミックス基板にクラ
ック，割れが生じやすい。By the way, although ceramic circuit boards have excellent properties such as heat dissipation and electrical insulation, the ceramic boards themselves are brittle and have low bending strength. When thermal and mechanical stresses are applied due to heat cycles associated with energization control and screw fastening when attaching to radiation fins in actual use as power semiconductor module products due to Cracks and cracks easily occur on the substrate.
【０００５】しかも、セラミックス基板にクラック，割
れが発生すると、その部分が絶縁不良となって地絡など
のダメージに進展するおそれがあって製品の信頼性が低
下する。そこで、パワー半導体モジュールとしての実使
用時にセラミックス基板にクラック，割れが生じた場合
でも、絶縁不良のダメージに進展しないようにする対策
として、セラミックス基板上の銅回路板（導体パター
ン）の領域から外れた箇所に沿って基板表面にあらかじ
めスナップラインを形成しておき、製品の実使用時に加
わる熱的，機械的応力を意図的にこのスナップラインに
集中させ、この部分にクラックが生じてもパワー半導体
モジュールとして絶縁不良のダメージに進展しないよう
にした構成のものが、この発明と同一出願人より特開平
９−３１２３５７号として先に提案されている。Moreover, when cracks and cracks occur in the ceramic substrate, the portion may become defective in insulation and may develop into damages such as ground faults, thereby lowering the reliability of products. Therefore, even if cracks or cracks occur in the ceramic substrate during actual use as a power semiconductor module, as a measure to prevent damage to insulation failure, the ceramic substrate is removed from the area of the copper circuit board (conductor pattern) on the ceramic substrate. A snap line is formed in advance on the substrate surface along the place where the thermal and mechanical stresses applied during actual use of the product are intentionally concentrated on this snap line, and even if a crack occurs in this part, the power semiconductor A module which does not progress to damage due to insulation failure as a module has been previously proposed by the same applicant as the present invention as Japanese Patent Application Laid-Open No. 9-313357.
【０００６】しかしながら、前記提案は、その後に行っ
た数多くの製品テスト結果から必ずしも期待通りの成果
が得られず、特にセラミックス基板のクラック発生箇所
を通じて銅ベース（アース電位）と銅回路板（充電部）
との間の沿面絶縁強度が決まってしまい、耐電圧の向上
が図れないなどの不具合の生じることが判明した。ま
た、銅貼りセラミックス回路基板では、銅回路板のパタ
ーン形状を工夫するなどしてクラック，割れを防ぐよう
にした対策も知られているが、この方法では回路パター
ンが制約を受けるなど、回路設計，コスト面の問題点が
残る。[0006] However, the above proposal does not always produce the expected results from the results of a number of product tests performed thereafter. In particular, the copper base (earth potential) and the copper circuit board (charging part) are not allowed to pass through the cracks on the ceramic substrate. )
It has been found that the creeping insulation strength between them is determined, and problems such as the inability to improve the withstand voltage cannot be achieved. In the case of copper-clad ceramic circuit boards, measures to prevent cracks and cracks by devising the pattern shape of the copper circuit board are also known. However, this method imposes limitations on circuit design, such as limiting the circuit pattern. However, the problem of cost remains.
【０００７】この発明は上記の点にかんがみなされたも
のであり、その目的は前記課題を解決し、回路面での設
計変更を要することなく、クラック，割れに対してより
信頼性の高いパワー半導体モジュール用のセラミックス
回路基板を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to solve the above-mentioned problems and to provide a power semiconductor which is more reliable against cracks and cracks without requiring a design change in circuit. An object of the present invention is to provide a ceramic circuit board for a module.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するため
に、この発明によれば、セラミックス基板に銅回路板を
接合したパワー半導体モジュール用のセラミックス回路
基板において、 (1) パワー半導体モジュールとしての実使用状態で熱
的，機械的応力が加わるセラミックス基板に対し、その
応力集中が予測される箇所に沿ってセラミックス基板の
表面に絶縁物の補強材を接合するものとする（請求項
１）。According to the present invention, there is provided a ceramic circuit board for a power semiconductor module in which a copper circuit board is joined to a ceramic substrate. An insulating reinforcing material is joined to the surface of the ceramic substrate along the location where the stress concentration is expected to be applied to the ceramic substrate to which thermal and mechanical stress is applied in an actual use state.
【０００９】パワー半導体モジュールとしての実使用状
態でセラミックス基板に加わる熱的，機械的応力の集中
箇所は、数多くの製品テストの結果から得た知見，コン
ピュータのシミュレーション手法などで予測が可能であ
る。そこで、この応力集中が予測される箇所に沿ってセ
ラミックス基板の表面に絶縁物の補強材を接合すること
により、セラミックス基板としての曲げ強度が高まり、
パワー半導体モジュール製品の実使用状態で加わる熱
的，機械的応力に起因するセラミックス基板のクラッ
ク，割れの発生を未然に防ぐことができる。Concentrations of thermal and mechanical stress applied to the ceramic substrate in the actual use state as a power semiconductor module can be predicted by knowledge obtained from a number of product test results, computer simulation techniques, and the like. Therefore, by joining the reinforcing material of the insulator to the surface of the ceramic substrate along the place where the stress concentration is predicted, the bending strength of the ceramic substrate increases,
It is possible to prevent cracks and cracks in the ceramic substrate caused by thermal and mechanical stress applied in the actual use state of the power semiconductor module product.
【００１０】(2) パワー半導体モジュールとしての実使
用状態で熱的，機械的応力が加わるセラミックス基板に
対し、その応力集中が予測される箇所に沿ってセラミッ
クス基板の表面に高粘着性，高伸び率を有するシリコー
ン系樹脂を塗布，キュアするものとする（請求項２）。
これにより、パワー半導体モジュール製品の実使用時に
加わる熱的，機械的応力に起因してセラミックス基板に
万一クラック，割れが生じても、この部分にはあらかじ
め電気絶縁性に優れたシリコーン系樹脂が盛り付けてあ
るので回路（充電部）に対する絶縁不良（沿面絶縁強度
の劣化）を引き起こすことがなく、製品としての耐電圧
低下が効果的に防げる。(2) The ceramic substrate to which thermal and mechanical stresses are applied in the actual use state as a power semiconductor module has high adhesiveness and high elongation on the surface of the ceramic substrate along a portion where the stress concentration is expected. A silicone resin having a high rate is applied and cured (claim 2).
As a result, even if the ceramic substrate cracks or cracks due to the thermal or mechanical stress applied during the actual use of the power semiconductor module product, a silicone resin having excellent electrical insulation properties is previously applied to this portion. Since it is provided, it does not cause insulation failure (deterioration of creeping insulation strength) with respect to the circuit (charged portion), and effectively prevents the withstand voltage of the product from lowering.
【００１１】[0011]
【発明の実施の形態】以下、この発明の実施の形態を図
１，および図２に示す実施例に基づいて説明する。 〔実施例１〕図１はこの発明の請求項１に対応する実施
例を示すものである。図において、１はセラミックス基
板１ａの主表面に導体パターンを形成する銅回路板１ｂ
を接合し、同じく裏面に銅板１ｃを接合したセラミック
ス回路基板、２は銅回路板１ａにマウントしたパワー半
導体素子、３はセラミックス回路基板１を搭載した銅ベ
ース板（ヒートシンク）であり、銅ベース板３に対して
セラミックス回路基板１の銅板１ｃが半田４で接合され
ている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the embodiments shown in FIGS. [Embodiment 1] FIG. 1 shows an embodiment corresponding to claim 1 of the present invention. In the figure, reference numeral 1 denotes a copper circuit board 1b on which a conductor pattern is formed on a main surface of a ceramic substrate 1a.
And a power semiconductor element mounted on the copper circuit board 1a, a copper base plate (heat sink) 3 on which the ceramic circuit board 1 is mounted, and a copper base plate. 3, a copper plate 1c of the ceramic circuit board 1 is joined with solder 4.
【００１２】ここで、前記セラミックス基板１ａに対し
ては、パワー半導体モジュール製品としての実使用状態
で熱的，機械的な応力の集中が予測される箇所Ｐに沿っ
て、セラミックス基板の表面に絶縁物の補強材５が接着
剤６により接合されている。なお、補強材５の接合はパ
ワー半導体モジュールの組立工程の途中で行うものとす
る。Here, the ceramic substrate 1a is insulated on the surface of the ceramic substrate along a point P where thermal and mechanical stress concentrations are expected in a practical use state as a power semiconductor module product. An object reinforcing material 5 is joined by an adhesive 6. The bonding of the reinforcing member 5 is performed during the assembly process of the power semiconductor module.
【００１３】なお、応力集中の予測される箇所Ｐは、数
多くの製品テスト結果から得た知見，コンピユータのシ
ミュレーションなどから、セラミックス基板１ａの上に
接合した銅回路板１ｂの相互間に沿って銅回路板で覆わ
れてない部分に多く発生することが判明しており、この
検証結果を基に絶縁物の補強材５を図示のように銅回路
板１ｂの相互間の縁に沿って敷設し、接着剤６によりセ
ラミックス基板１ａの表面に接合するようにしている。The point P where the stress concentration is predicted is determined by the knowledge obtained from a number of product test results, computer simulations, etc., based on the distance between the copper circuit boards 1b joined to the ceramic substrate 1a. It has been found that a large amount occurs in portions not covered with the circuit board. Based on the verification results, the reinforcing material 5 made of an insulating material is laid along the edges between the copper circuit boards 1b as shown in the figure. The adhesive 6 is used to join the surface of the ceramic substrate 1a.
【００１４】かかる構成によれば、補強材５を接合した
ことでその部分におけるセラミックス基板１ａの曲げ強
度が増強され、パワー半導体モジュールとしての実使用
時に加わる熱的，機械的応力に対してクラック，割れが
生じない強度を確保することができる。 〔実施例２〕図２はこの発明の請求項２に対応する実施
例を示すものである。この実施例においては、パワー半
導体モジュールとしての実使用状態で熱的，機械的な応
力の集中が予測される箇所Ｐ（図１と同一箇所）に沿っ
てセラミックス基板１ａの表面には、銅回路板１ｂの相
互間の間隙を埋めるように盛り付けて高粘着性，高伸び
率（ゴム性）を有するシリコーン系樹脂（コンパンウン
ド）７が塗布，キュアされている。According to such a configuration, the bending strength of the ceramic substrate 1a at the portion where the reinforcing material 5 is joined is enhanced, and cracks and cracks are generated against thermal and mechanical stress applied during actual use as a power semiconductor module. The strength that does not cause cracking can be secured. [Embodiment 2] FIG. 2 shows an embodiment corresponding to claim 2 of the present invention. In this embodiment, a copper circuit is provided on the surface of the ceramic substrate 1a along a location P (the same location as in FIG. 1) where thermal and mechanical stress concentrations are expected in a practical use state as a power semiconductor module. Silicone resin (compound) 7 having high adhesiveness and high elongation (rubber) is applied and cured so as to fill the gap between the plates 1b.
【００１５】これにより、パワー半導体モジュール製品
としての実使用状態でセラミックス基板１ａに加わる熱
的，機械的な応力集中で前記箇所Ｐにクラック，割れ８
が発生した場合でも、その周域がシリコーン系樹脂７で
覆われているので、銅ベース板（アース電位）３と銅回
路板（充電部）１ｂとの間の沿面絶縁強度，耐電圧の低
下が防げる。As a result, cracks and cracks 8 occur at the location P due to thermal and mechanical stress concentrations applied to the ceramic substrate 1a in an actual use state as a power semiconductor module product.
Even when a crack occurs, the peripheral area is covered with the silicone resin 7, so that the creeping insulation strength and the withstand voltage between the copper base plate (ground potential) 3 and the copper circuit board (charged portion) 1b are reduced. Can prevent.
【００１６】[0016]
【発明の効果】以上述べたように、この発明によるセラ
ミックス回路基板を用いてパワー半導体モジュールの製
品を組立てることにより、次記の効果を奏する。 (1) 請求項１の構成によれば、補強材の接合によりセラ
ミックス基板の曲げ強度が増強し、製品の実使用状態で
セラミックス基板に熱的，機械的応力が加わっても、セ
ラミックス基板にクラック，割れの生じるのを効果的に
防止でき、製品の信頼性向上化が図れる。As described above, the following effects can be obtained by assembling a power semiconductor module product using the ceramic circuit board according to the present invention. (1) According to the configuration of claim 1, the bending strength of the ceramic substrate is enhanced by joining the reinforcing material, and even if a thermal or mechanical stress is applied to the ceramic substrate in the actual use state of the product, the ceramic substrate is cracked. , Cracks can be effectively prevented, and the reliability of the product can be improved.
【００１７】(2) 請求項２の構成によれば、パワー半導
体モジュール製品としての実使用状態で加わる熱的，機
械的な応力によりセラミックス基板にクラック，割れが
発生した場合でも、その周域がシリコーン系樹脂で覆わ
れているので、沿面絶縁強度，耐電圧の低下が防げるの
で製品の高い信頼性を維持できる。(2) According to the second aspect of the present invention, even if cracks and cracks occur in the ceramic substrate due to thermal and mechanical stresses applied in a practical use state as a power semiconductor module product, the peripheral area is reduced. Since it is covered with the silicone resin, it is possible to prevent a decrease in creeping insulation strength and withstand voltage, so that high reliability of the product can be maintained.
【図１】この発明の実施例１に対応するパワー半導体モ
ジュールの要部構造図FIG. 1 is a structural view of a main part of a power semiconductor module according to a first embodiment of the present invention;
【図２】この発明の実施例２に対応するパワー半導体モ
ジュールの要部構造図FIG. 2 is a main part structural diagram of a power semiconductor module corresponding to a second embodiment of the present invention;
１ セラミックス回路基板 １ａ セラミックス基板 １ｂ 銅回路板 １ｃ 銅板 ２ パワー半導体素子 ３ 銅ベース板 ５ 補強材 ６ 接着剤 ７ シリコーン系樹脂 ８ クラック，割れ Ｐ 応力集中の予測箇所 DESCRIPTION OF SYMBOLS 1 Ceramic circuit board 1a Ceramic board 1b Copper circuit board 1c Copper board 2 Power semiconductor element 3 Copper base board 5 Reinforcement material 6 Adhesive 7 Silicone resin 8 Crack, crack P Predicted location of stress concentration
Claims (2)
ワー半導体モジュール用のセラミックス回路基板におい
て、パワー半導体モジュールとしての実使用状態で熱
的，機械的応力が加わるセラミックス基板に対し、その
応力集中が予測される箇所に沿ってセラミックス基板の
表面に絶縁物の補強材を接合したことを特徴とするパワ
ー半導体モジュール用のセラミックス回路基板。In a ceramic circuit board for a power semiconductor module in which a copper circuit board is bonded to a ceramic substrate, the concentration of stress on the ceramic substrate to which thermal and mechanical stress is applied in a practical use state as a power semiconductor module is reduced. A ceramic circuit board for a power semiconductor module, wherein an insulating reinforcing material is joined to a surface of a ceramic substrate along a predicted location.
ワー半導体モジュール用のセラミックス回路基板におい
て、パワー半導体モジュールとしての実使用状態で熱
的，機械的応力が加わるセラミックス基板に対し、その
応力集中が予測される箇所に沿ってセラミックス基板の
表面に高粘着性，高伸び率を有するシリコーン系樹脂を
塗布，キュアしたことを特徴とするパワー半導体モジュ
ール用のセラミックス回路基板。2. A ceramic circuit board for a power semiconductor module in which a copper circuit board is joined to a ceramic substrate, wherein stress concentration is applied to a ceramic substrate to which thermal and mechanical stress is applied in a practical use state as a power semiconductor module. A ceramic circuit board for a power semiconductor module, characterized by applying and curing a silicone resin having a high adhesiveness and a high elongation on the surface of the ceramic substrate along an expected portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20493598A JP3861465B2 (en) | 1998-07-21 | 1998-07-21 | Ceramic circuit board and semiconductor device using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20493598A JP3861465B2 (en) | 1998-07-21 | 1998-07-21 | Ceramic circuit board and semiconductor device using the same |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006216323A Division JP4462250B2 (en) | 2006-08-09 | 2006-08-09 | Ceramic circuit board and semiconductor device using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000036550A true JP2000036550A (en) | 2000-02-02 |
| JP3861465B2 JP3861465B2 (en) | 2006-12-20 |
Family
ID=16498800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20493598A Expired - Fee Related JP3861465B2 (en) | 1998-07-21 | 1998-07-21 | Ceramic circuit board and semiconductor device using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3861465B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007095942A (en) * | 2005-09-28 | 2007-04-12 | Nissan Motor Co Ltd | Joint structure |
| WO2012090740A1 (en) * | 2010-12-28 | 2012-07-05 | 株式会社日立製作所 | Circuit board for semiconductor module |
-
1998
- 1998-07-21 JP JP20493598A patent/JP3861465B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007095942A (en) * | 2005-09-28 | 2007-04-12 | Nissan Motor Co Ltd | Joint structure |
| WO2012090740A1 (en) * | 2010-12-28 | 2012-07-05 | 株式会社日立製作所 | Circuit board for semiconductor module |
| JP2012138541A (en) * | 2010-12-28 | 2012-07-19 | Hitachi Ltd | Circuit board for semiconductor module |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3861465B2 (en) | 2006-12-20 |
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