JP2000031204A - Manufacture of semiconductor package - Google Patents
Manufacture of semiconductor packageInfo
- Publication number
- JP2000031204A JP2000031204A JP10208599A JP20859998A JP2000031204A JP 2000031204 A JP2000031204 A JP 2000031204A JP 10208599 A JP10208599 A JP 10208599A JP 20859998 A JP20859998 A JP 20859998A JP 2000031204 A JP2000031204 A JP 2000031204A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- electrode
- connection
- bump
- melting point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
- H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、フリップチップ実
装型の半導体パッケージの製造方法に関し、特に、半導
体チップの接続電極上に形成されているハンダバンプを
介して、基板上の電極と接続電極とをフリップチップ接
続するフリップチップ実装型の半導体パッケージの製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a flip-chip mounted semiconductor package, and more particularly, to a method for connecting an electrode on a substrate and a connection electrode via a solder bump formed on the connection electrode of the semiconductor chip. The present invention relates to a method of manufacturing a flip-chip mounted semiconductor package for flip-chip connection.
【０００２】[0002]
【従来の技術】従来この種の半導体パッケージの製造方
法としては、例えば、半導体チップのアルミニウム（Ａ
ｌ）電極に直接的にワイヤバンピングを行ってハンダバ
ンプを形成するフリップチップ実装型の半導体パッケー
ジの製造方法が知られている。またこのような製造方法
では、ハンダワイヤを用いてハンダバンプを形成した半
導体チップをフリップチップ実装法で基板電極に接続す
る際、フラックスが通常用いられている。2. Description of the Related Art Conventionally, as a method of manufacturing a semiconductor package of this type, for example, aluminum (A) of a semiconductor chip is used.
1) A method of manufacturing a flip-chip mounting type semiconductor package in which a solder bump is formed by directly performing wire bumping on an electrode is known. In such a manufacturing method, when a semiconductor chip having solder bumps formed using solder wires is connected to a substrate electrode by a flip chip mounting method, a flux is generally used.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、このよ
うな従来の半導体パッケージの製造方法では、前述のフ
ラックスの効果によって、溶融したハンダの表面張力が
強くなる結果、バンプシェア強度が弱くなってしまう。
更に加えて、Ａｌとハンダバンプ中の添加物が原因と考
えられる合金層の拡散によりＡｌ電極とハンダバンプの
界面で剥離が起きやすくなる結果、更にバンプシェア強
度が弱くなってしまう。However, in such a conventional method of manufacturing a semiconductor package, the surface tension of the molten solder is increased due to the effect of the above-mentioned flux, and the bump shear strength is reduced.
In addition, the diffusion of the alloy layer, which is considered to be caused by Al and the additives in the solder bumps, tends to cause peeling at the interface between the Al electrode and the solder bumps, further reducing the bump shear strength.
【０００４】その結果、フリップチップ実装の初期段階
ではフリップチップ接続界面でコンタクト（電気的、機
械的接続状態）が維持されているものの、信頼性試験な
どを実行してハンダバンプに応力が加わった場合にフリ
ップチップ接続界面においてオープン（電気的、機械的
非接続状態）が発生することが考えられるという問題点
があった。[0004] As a result, in the initial stage of flip chip mounting, although contacts (electrical and mechanical connection states) are maintained at the flip chip connection interface, when stress is applied to the solder bumps by performing a reliability test or the like. In addition, there is a problem that an open (electrical or mechanical non-connection state) may occur at the flip chip connection interface.
【０００５】図４を用いて具体的に説明する。図４
（ａ）は、半導体チップ１３Ａ上のＡｌ電極（チップ電
極）１２Ａにハンダワイヤバンピング１１Ａによるハン
ダバンプを形成する様子を示している。続く工程で、図
４（ｂ）のように、フラックス２１Ａを転写する。続い
て、チップ電極１２Ａと基板３２に形成されている電極
（基板電極）とを位置合わせした後、加熱接続する（図
４（ｃ））。A specific description will be given with reference to FIG. FIG.
(A) shows a state in which a solder bump is formed on an Al electrode (chip electrode) 12A on a semiconductor chip 13A by a solder wire bumping 11A. In a subsequent step, the flux 21A is transferred as shown in FIG. Subsequently, after the chip electrode 12A and the electrode (substrate electrode) formed on the substrate 32 are positioned, they are connected by heating (FIG. 4C).
【０００６】このとき加熱後のフラックス３１Ａは、図
４（ｃ）に示すように、熱によりハンダバンプ１１Ａを
取り囲むように流動する。このため、Ａｌ電極１２Ａと
ハンダバンプ１１Ａとの界面に非接触部３３が発生し易
くなる結果（図４（ｄ）の界面の拡大図参照）、Ａｌ電
極１２Ａとハンダバンプ１１Ａとの界面は、図４（ａ）
の界面状態に比べて、剥離しやすい状態になるという問
題点があった。At this time, the heated flux 31A flows so as to surround the solder bump 11A by heat as shown in FIG. 4 (c). For this reason, the non-contact portion 33 is likely to be generated at the interface between the Al electrode 12A and the solder bump 11A (see the enlarged view of the interface in FIG. 4D), and the interface between the Al electrode 12A and the solder bump 11A is as shown in FIG. (A)
However, there is a problem that the state is easily peeled as compared with the interface state.
【０００７】本発明は、このような従来の問題点を解決
することを課題としており、特に、半導体チップの接続
電極（Ａｌ電極）とハンダバンプとの界面を前述したよ
うな剥離現象から保護することでワイヤバンプした直後
の接続状態を維持すると共に、バンプシェア強度を保っ
たままでのフリップチップ接続を実現し、更に加えて、
接続電極のハンダとハンダ成分が異なりかつ低融点のハ
ンダからなるハンダバンプを用いて接続することで、接
続電極側のハンダ成分を溶融させないようなフリップチ
ップ接続を実現することを目的としている。SUMMARY OF THE INVENTION An object of the present invention is to solve such a conventional problem. In particular, it is an object of the present invention to protect an interface between a connection electrode (Al electrode) of a semiconductor chip and a solder bump from the peeling phenomenon as described above. In addition to maintaining the connection state immediately after wire bumping with, the flip chip connection with the bump share strength is maintained, and in addition,
It is an object of the present invention to realize flip-chip connection in which the solder component on the connection electrode side is not melted by connecting using a solder bump made of solder having a different melting point and low melting point from the solder of the connection electrode.
【０００８】[0008]
【課題を解決するための手段】上記課題を解決するため
成された請求項１に記載の発明は、半導体チップの接続
電極上に形成されているハンダバンプを介して、基板上
の電極と接続電極とをフリップチップ接続する半導体パ
ッケージの製造方法において、前記接続電極を覆う部分
の前記ハンダバンプのハンダ成分が前記基板電極に接す
る基板側ハンダのハンダ成分と異なり、かつ当該基板側
ハンダの融点が当該ハンダバンプの融点より低いような
ハンダバンプ構造を形成する工程を有する半導体パッケ
ージの製造方法である。According to a first aspect of the present invention, there is provided a semiconductor device comprising: an electrode on a substrate; and a solder bump formed on the connection electrode of the semiconductor chip. In a method of manufacturing a semiconductor package for flip-chip connection of the solder bumps, the solder component of the solder bump in a portion covering the connection electrode is different from the solder component of the board-side solder in contact with the board electrode, and the melting point of the board-side solder is And a method of manufacturing a semiconductor package having a step of forming a solder bump structure having a melting point lower than the melting point of the semiconductor package.
【０００９】請求項１に記載の発明によれば、接続電極
に接しているハンダがフラックスのある接続時には溶融
しないので、バンプシェア強度を強くすることができ、
接続信頼性を高めることができる。According to the first aspect of the present invention, the solder in contact with the connection electrode does not melt at the time of connection with flux, so that the bump shear strength can be increased,
Connection reliability can be improved.
【００１０】また請求項２に記載の発明は、請求項１に
記載の半導体パッケージの製造方法において、前記ハン
ダバンプ構造の半導体チップをフリップチップ接続する
工程を実行する際に、前記低融点のハンダ成分のみが溶
融するような温度条件下でフリップチップ接続を行うフ
リップチップ接続工程を有する半導体パッケージの製造
方法である。According to a second aspect of the present invention, in the method of manufacturing a semiconductor package according to the first aspect, when the step of flip-chip connecting the semiconductor chip having the solder bump structure is performed, the low-melting solder component is used. This is a method of manufacturing a semiconductor package having a flip-chip connection step of performing flip-chip connection under a temperature condition in which only the melting occurs.
【００１１】請求項２に記載の発明によれば、請求項１
に記載の効果と同様の効果を奏する。According to the invention described in claim 2, according to claim 1,
The same effect as the effect described in (1) is obtained.
【００１２】また請求項３に記載の発明は、請求項１又
は２に記載の半導体パッケージの製造方法において、前
記ハンダバンプ構造を形成する工程を実行する際に、半
導体チップの前記ハンダバンプを、溶融した低融点のハ
ンダ層の中に浸漬した状態で当該低融点ハンダを転写す
ることにより前記ハンダバンプを形成する工程を有する
半導体パッケージの製造方法である。According to a third aspect of the present invention, in the method of manufacturing a semiconductor package according to the first or second aspect, the step of forming the solder bump structure includes melting the solder bumps of the semiconductor chip. A method of manufacturing a semiconductor package, comprising a step of forming the solder bump by transferring the low-melting solder in a state of being immersed in a low-melting solder layer.
【００１３】請求項３に記載の発明によれば、請求項１
又は２に記載の効果に加えて、低融点ハンダの印刷工程
などが要らないので、容易にハンダバンプを形成するこ
とができるようになる。また、使用するフラックスの量
を請求項１，２の製造方法より少なくできるので、バン
プシェア強度を更に強くすることができ、かつ接続後の
フラックス洗浄も短時間で終了できるようになる。According to the third aspect of the present invention, the first aspect is provided.
Or, in addition to the effect described in 2, the printing step of low melting point solder is not required, so that the solder bump can be easily formed. Further, since the amount of the flux to be used can be made smaller than that of the manufacturing method of the first and second aspects, the bump shear strength can be further increased, and the flux cleaning after connection can be completed in a short time.
【００１４】[0014]
【発明の実施の形態】（第１実施形態）第１実施形態の
半導体パッケージの製造方法は、半導体チップ１３の接
続電極（Ａｌ（アルミニウム）電極）１２上に形成され
ている金属突起であるハンダバンプ１１を接続媒体とし
て、基板３２上の電極とＡｌ電極１２とをフリップチッ
プ接続するフリップチップ実装型の半導体パッケージの
製造方法であって、Ａｌ電極１２を覆う部分のハンダバ
ンプ１１のハンダ成分が基板電極に接する基板側ハンダ
４１のハンダとハンダ成分が異なり、かつ基板側ハンダ
４１の融点がハンダバンプ１１の融点より低いようなハ
ンダバンプ構造を形成する工程することにより、半導体
チップ１３のＡｌ電極１２とハンダバンプ１１との界面
を前述したような剥離現象から保護することでワイヤバ
ンプした直後の接続状態を維持すると共に、バンプシェ
ア強度を保ったままでのフリップチップ接続を実現して
いる点、更に加えて、Ａｌ電極１２用のハンダ成分と異
なる低融点ハンダ４１からなるハンダバンプ１１を用い
て接続することで、Ａｌ電極１２側のハンダ成分を溶融
させないようなフリップチップ接続を実現する点に特徴
を有している。DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A method of manufacturing a semiconductor package according to a first embodiment will be described with reference to a solder bump which is a metal protrusion formed on a connection electrode (Al (aluminum) electrode) 12 of a semiconductor chip 13. 11. A method of manufacturing a flip-chip mounting type semiconductor package in which an electrode on a substrate 32 and an Al electrode 12 are flip-chip connected by using 11 as a connection medium, wherein a solder component of the solder bump 11 covering the Al electrode 12 is By forming a solder bump structure in which the solder of the substrate-side solder 41 is different from the solder component and the melting point of the substrate-side solder 41 is lower than the melting point of the solder bump 11, the Al electrode 12 of the semiconductor chip 13 and the solder bump 11 are formed. The interface immediately after wire bumping is protected by protecting the interface with In addition to maintaining the state and realizing flip-chip connection while maintaining the bump shear strength, in addition to the above, the connection is made using the solder bump 11 made of the low melting point solder 41 different from the solder component for the Al electrode 12. This has a feature in realizing flip-chip connection that does not melt the solder component on the Al electrode 12 side.
【００１５】図１は、本発明の半導体パッケージの製造
方法の第１実施形態を説明するための図である。第１実
施形態では、図１（ａ）に示すように、あらかじめ基板
電極に低融点ハンダ４１をプリコートしておき、フラッ
クス２１をハンダバンプ１１の先端のみ転写し、相互の
電極を位置合わせする工程を実行している。ここで、低
融点ハンダ４１を基板３２にコートする方法として、一
般的に印刷方法がある。しかし、基板電極が小さく微細
ピッチの場合、一般的なメッシュの印刷マスクに代え
て、メタルマスクもしくはレーザ加工した樹脂マスクを
用いることが適当である。FIG. 1 is a view for explaining a first embodiment of a method of manufacturing a semiconductor package according to the present invention. In the first embodiment, as shown in FIG. 1A, a step of pre-coating the substrate electrode with a low melting point solder 41, transferring the flux 21 only to the tip of the solder bump 11, and aligning the mutual electrodes is performed. Running. Here, as a method of coating the substrate 32 with the low melting point solder 41, there is generally a printing method. However, when the substrate electrode is small and has a fine pitch, it is appropriate to use a metal mask or a laser-processed resin mask instead of a general mesh print mask.
【００１６】更に前工程に続いて、図１（ｂ）に示すよ
うに、基板電極をハンダ溶融温度で加熱しフリップチッ
プ接続する工程を実行している。またハンダバンプ構造
の半導体チップ１３をフリップチップ接続する工程を実
行する際に、低融点のハンダ４１のハンダ成分のみが溶
融するような温度条件下でフリップチップ接続を行うフ
リップチップ接続工程を実行している。このようなフリ
ップチップ接続を行う場合、使用する低融点ハンダ４１
に合わせて加熱し、接続電極（Ａｌ電極）１２側のハン
ダが溶融しないようにする。ここで、ハンダバンプ１１
の高さ（バンプ高さ）のバラツキは低融点ハンダ４１が
吸収するので、フリップチップ接続後の半導体チップ１
３と基板３２とのギャップは抑えられる。Further, following the previous step, as shown in FIG. 1B, a step of heating the substrate electrode at a solder melting temperature and performing flip-chip connection is performed. Further, when performing the step of flip-chip connecting the semiconductor chip 13 having the solder bump structure, the flip-chip connection step of performing flip-chip connection under such a temperature condition that only the solder component of the low melting point solder 41 is melted is executed. I have. When such a flip-chip connection is made, the low melting point solder 41 to be used is used.
To prevent the solder on the connection electrode (Al electrode) 12 side from melting. Here, the solder bump 11
The variation in the height (bump height) is absorbed by the low melting point solder 41, so that the semiconductor chip 1 after the flip chip connection is formed.
The gap between 3 and substrate 32 is suppressed.
【００１７】更に前工程に続いて、図１（ｃ）に示すよ
うに、接続後にフラックス２１を洗浄する工程を実行し
ている。具体的には、フリップチップ接続後、フラック
ス２１の残渣がなくなるまでフラックス２１を洗浄す
る。その後、ハンダバンプ１１の周囲に封止材を注入し
た後硬化する工程を実行する。これにより、半導体パッ
ケージになった後にＡｌ電極１２側のハンダ成分の融点
でのリフローが行われた場合であっても、ハンダバンプ
１１の周囲にフラックス２１がないため、前述したよう
なフリップチップ接続時におけるＡｌ電極１２との剥離
は発生しない。Further, following the previous step, as shown in FIG. 1C, a step of cleaning the flux 21 after connection is performed. Specifically, after the flip chip connection, the flux 21 is washed until there is no residue of the flux 21. Thereafter, a step of injecting a sealing material around the solder bumps 11 and then hardening is performed. As a result, even when reflow is performed at the melting point of the solder component on the Al electrode 12 side after the semiconductor package is formed, the flux 21 does not exist around the solder bump 11, so that the above-described flip-chip connection Does not occur with the Al electrode 12.
【００１８】以上説明したように、第１実施形態によれ
ば、Ａｌ電極１２に接しているハンダがフラックス２１
のある接続時には溶融しないので、バンプシェア強度を
強くすることができ、接続信頼性を高めることができ
る。As described above, according to the first embodiment, the solder in contact with the Al electrode 12 is
Since there is no melting at the time of the connection with a connection, the bump shear strength can be increased and the connection reliability can be improved.
【００１９】（第２実施形態）図２，図３は、本発明の
半導体パッケージの製造方法の第２実施形態を説明する
ための図である。なお、第１実施形態において既に記述
したものと同一の部分については、同一符号を付し、重
複した説明は省略する。(Second Embodiment) FIGS. 2 and 3 are views for explaining a second embodiment of the method of manufacturing a semiconductor package according to the present invention. Note that the same parts as those already described in the first embodiment are denoted by the same reference numerals, and redundant description will be omitted.
【００２０】第２実施形態の製造方法は、第１実施形態
の製造方法のハンダバンプ構造を形成する工程を実行す
る際に、半導体チップ１３のハンダバンプ１１を、平面
基板７２の上で溶融した低融点のハンダ層７１の中に浸
漬した状態で低融点ハンダ４１を転写することによりハ
ンダバンプ１１を形成する工程を実行する点に特徴を有
している。In the manufacturing method according to the second embodiment, when the step of forming the solder bump structure of the manufacturing method according to the first embodiment is performed, the solder bump 11 of the semiconductor chip 13 is melted on the flat substrate 72 with a low melting point. The method is characterized in that the step of forming the solder bumps 11 by transferring the low melting point solder 41 in a state of being immersed in the solder layer 71 is performed.
【００２１】具体的には、図２（ａ）に示すように、Ａ
ｌ電極１２にハンダバンピングした後、平面基板７２上
に塗布した低融点ハンダ４１を転写する工程を実行して
いる。更に前工程に続いて、図２（ｂ）に示すように、
平面基板７２を低融点ハンダ４１の融点で加熱し、転写
する工程を実行している。更に前工程に続いて、図３
（ｃ）に示すように、基板電極と位置合わせする工程を
実行している。更に前工程に続いて、図３（ｄ）に示す
ように、再び低融点ハンダ４１の融点で加熱しフリップ
チップ接続する工程を実行している。Specifically, as shown in FIG.
After solder bumping the l-electrode 12, a step of transferring the low melting point solder 41 applied on the flat substrate 72 is executed. Further, following the previous step, as shown in FIG.
The step of heating the flat substrate 72 at the melting point of the low melting point solder 41 and transferring the same is performed. Following the previous step, FIG.
As shown in (c), a step of aligning with the substrate electrode is performed. Further, following the previous step, as shown in FIG. 3D, a step of heating again at the melting point of the low melting point solder 41 and performing flip chip connection is performed.
【００２２】以上説明したように、第２実施形態によれ
ば、第１実施形態に記載の効果に加えて、低融点ハンダ
４１の印刷工程などが要らないので、容易にハンダバン
プ１１を形成することができるようになる。また、使用
するフラックス２１の量を請求項１，２の製造方法より
少なくできるので、バンプシェア強度を更に強くするこ
とができ、かつ接続後のフラックス２１洗浄も短時間で
終了できるようになる。As described above, according to the second embodiment, in addition to the effects described in the first embodiment, since the step of printing the low melting point solder 41 is not required, the solder bumps 11 can be easily formed. Will be able to In addition, since the amount of the flux 21 to be used can be reduced as compared with the manufacturing method of the first and second aspects, the bump shear strength can be further increased, and the cleaning of the flux 21 after connection can be completed in a short time.
【００２３】[0023]
【発明の効果】半導体チップの接続電極とハンダバンプ
との界面を前述したような剥離現象から保護することで
ワイヤバンプした直後の接続状態を維持すると共に、バ
ンプシェア強度を保ったままでのフリップチップ接続を
実現できるようになる。更に加えて、接続電極用のハン
ダ成分と異なる低融点ハンダからなるハンダバンプを用
いて接続することで、接続電極側のハンダ成分を溶融さ
せないようなフリップチップ接続を実現できるようにな
る。According to the present invention, the interface between the connection electrodes of the semiconductor chip and the solder bumps is protected from the peeling phenomenon as described above, so that the connection state immediately after the wire bump is maintained and the flip chip connection with the bump shear strength maintained. It can be realized. In addition, by using a solder bump made of low melting point solder different from the solder component for the connection electrode, flip-chip connection can be realized in which the solder component on the connection electrode side is not melted.
【図１】本発明の半導体パッケージの製造方法の第１実
施形態を説明するための図であって、同図（ａ）は、あ
らかじめ基板電極に低融点ハンダをプリコートしてお
き、フラックスをハンダバンプの先端のみ転写し、相互
の電極を位置合わせしたときの様子を示し、同図（ｂ）
は基板電極をハンダ溶融温度で加熱し接続したときの様
子を示し、同図（ｃ）は接続後にフラックス洗浄をした
後の様子を示している。FIG. 1 is a view for explaining a first embodiment of a method of manufacturing a semiconductor package according to the present invention. FIG. 1 (a) shows a method in which a low melting point solder is pre-coated on a substrate electrode in advance, and flux is solder bumped. FIG. 4B shows a state in which only the tips of are transferred and the mutual electrodes are aligned.
Shows the state when the substrate electrode is heated and connected at the solder melting temperature, and FIG. 4C shows the state after flux cleaning after connection.
【図２】本発明の半導体パッケージの製造方法の第２実
施形態を説明するための図であって、同図（ａ）は、接
続電極（Ａｌ電極）にハンダバンピングした後、平面基
板上に塗布した低融点ハンダを転写する様子を示し、同
図（ｂ）は、平面基板を低融点ハンダの融点で加熱し、
転写したときの様子を示している。FIG. 2 is a view for explaining a second embodiment of the method of manufacturing a semiconductor package according to the present invention. FIG. 2 (a) shows a semiconductor package after solder bumping on a connection electrode (Al electrode), and then on a flat substrate. FIG. 3B shows a state in which the applied low melting point solder is transferred. FIG.
This shows a state when the image is transferred.
【図３】本発明の半導体パッケージの製造方法の第２実
施形態を説明するための図であって、同図（ｃ）は、基
板電極と位置合わせしている様子を示し、同図（ｄ）は
再び低融点ハンダの融点で加熱し接続した様子を示して
いる。FIG. 3 is a view for explaining a second embodiment of the method of manufacturing a semiconductor package according to the present invention. FIG. 3 (c) shows a state where the semiconductor package is aligned with a substrate electrode, and FIG. ) Shows a state in which the connection is made by heating again at the melting point of the low melting point solder.
【図４】従来技術を説明するための図であって、同図
（ａ）は、半導体チップ１３Ａ上の接続電極にハンダワ
イヤバンピングによるハンダバンプを形成する様子を示
し、同図（ｂ）はフラックスを転写した様子を示し、同
図（ｃ）はチップ電極と基板電極とを位置合わせした後
に加熱接続した様子を示し、同図（ｄ）は熱によりフラ
ックスがハンダバンプを取り囲んだ様子を示し、接続電
極とハンダバンプとの界面における非接触部の発生状態
を示している。4A and 4B are diagrams for explaining the prior art, wherein FIG. 4A shows a state in which solder bumps are formed on connection electrodes on a semiconductor chip 13A by solder wire bumping, and FIG. (C) shows a state in which the chip electrode and the substrate electrode are aligned and then heated and connected, and FIG. (D) shows a state in which the flux surrounds the solder bump by heat. The state of occurrence of a non-contact portion at the interface between an electrode and a solder bump is shown.
１１…ハンダバンプ １２…接続電極（Ａｌ電極） １３…半導体チップ ２１…フラックス ３１…加熱後のフラックス ３２…基板 ３３…非接触部 ４１…基板側ハンダ（低融点ハンダ） ７１…溶融した低融点ハンダ層 ７２…平面基板 DESCRIPTION OF SYMBOLS 11 ... Solder bump 12 ... Connection electrode (Al electrode) 13 ... Semiconductor chip 21 ... Flux 31 ... Flux after heating 32 ... Substrate 33 ... Non-contact part 41 ... Substrate side solder (low melting point solder) 71 ... Melted low melting point solder layer 72 ... Planar substrate
Claims (3)
いるハンダバンプを介して、基板上の電極と接続電極と
をフリップチップ接続する半導体パッケージの製造方法
において、 前記接続電極を覆う部分の前記ハンダバンプのハンダ成
分が前記基板電極に接する基板側ハンダのハンダ成分と
異なり、かつ当該基板側ハンダの融点が当該ハンダバン
プの融点より低いようなハンダバンプ構造を形成する工
程を有することを特徴とする半導体パッケージの製造方
法。1. A method of manufacturing a semiconductor package in which an electrode on a substrate and a connection electrode are flip-chip connected via a solder bump formed on the connection electrode of a semiconductor chip, wherein a portion of the solder bump covering the connection electrode is provided. Wherein the solder component of the semiconductor package is different from the solder component of the substrate-side solder in contact with the substrate electrode, and the step of forming a solder bump structure such that the melting point of the substrate-side solder is lower than the melting point of the solder bump. Production method.
フリップチップ接続する工程を実行する際に、前記低融
点のハンダ成分のみが溶融するような温度条件下でフリ
ップチップ接続を行うフリップチップ接続工程を有する
ことを特徴とする請求項１に記載の半導体パッケージの
製造方法。2. The method according to claim 1, wherein the step of flip-chip connecting the semiconductor chip having the solder bump structure includes the step of performing flip-chip connection under a temperature condition in which only the low melting point solder component is melted. The method according to claim 1, wherein:
実行する際に、半導体チップの前記ハンダバンプを、溶
融した低融点のハンダ層の中に浸漬した状態で当該低融
点ハンダを転写することにより前記ハンダバンプを形成
する工程を有することを特徴とする請求項１又は２に記
載の半導体パッケージの製造方法。3. The step of forming the solder bump structure, wherein the solder bump is transferred by transferring the low melting point solder in a state where the solder bump of the semiconductor chip is immersed in a molten low melting point solder layer. 3. The method of manufacturing a semiconductor package according to claim 1, further comprising the step of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10208599A JP2000031204A (en) | 1998-07-07 | 1998-07-07 | Manufacture of semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10208599A JP2000031204A (en) | 1998-07-07 | 1998-07-07 | Manufacture of semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000031204A true JP2000031204A (en) | 2000-01-28 |
Family
ID=16558884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10208599A Withdrawn JP2000031204A (en) | 1998-07-07 | 1998-07-07 | Manufacture of semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000031204A (en) |
Cited By (33)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008535225A (en) * | 2005-03-25 | 2008-08-28 | スタッツ チップパック リミテッド | Flip chip wiring having a narrow wiring portion on a substrate |
| JP2009016633A (en) * | 2007-07-06 | 2009-01-22 | Panasonic Corp | Conductive bump, its manufacturing method, electronic component mounting structure using same, and its manufacturing method |
| US8129837B2 (en) | 2003-11-08 | 2012-03-06 | Stats Chippac, Ltd. | Flip chip interconnection pad layout |
| US8129841B2 (en) | 2006-12-14 | 2012-03-06 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
| US8169071B2 (en) | 2008-09-10 | 2012-05-01 | Stats Chippac, Ltd. | Semiconductor device having vertically offset bond on trace interconnects on recessed and raised bond fingers |
| US8188598B2 (en) | 2003-11-10 | 2012-05-29 | Stats Chippac, Ltd. | Bump-on-lead flip chip interconnection |
| US8193035B2 (en) | 2006-09-22 | 2012-06-05 | Stats Chippac, Ltd. | Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud bumps |
| US8198186B2 (en) | 2008-12-31 | 2012-06-12 | Stats Chippac, Ltd. | Semiconductor device and method of confining conductive bump material during reflow with solder mask patch |
| US8216930B2 (en) | 2006-12-14 | 2012-07-10 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
| US8278144B2 (en) | 2005-05-16 | 2012-10-02 | Stats Chippac, Ltd. | Flip chip interconnect solder mask |
| US8350384B2 (en) | 2009-11-24 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
| US8349721B2 (en) | 2008-03-19 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding |
| US8409978B2 (en) | 2010-06-24 | 2013-04-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe |
| US8435834B2 (en) | 2010-09-13 | 2013-05-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP |
| US8492197B2 (en) | 2010-08-17 | 2013-07-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate |
| USRE44500E1 (en) | 2003-11-10 | 2013-09-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
| US8563418B2 (en) | 2010-03-09 | 2013-10-22 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces |
| USRE44562E1 (en) | 2003-11-10 | 2013-10-29 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
| USRE44579E1 (en) | 2003-11-10 | 2013-11-05 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| USRE44608E1 (en) | 2003-11-10 | 2013-11-26 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
| US8659172B2 (en) | 2008-12-31 | 2014-02-25 | Stats Chippac, Ltd. | Semiconductor device and method of confining conductive bump material with solder mask patch |
| US8697490B2 (en) | 2000-03-10 | 2014-04-15 | Stats Chippac, Ltd. | Flip chip interconnection structure |
| US8759972B2 (en) | 2003-11-10 | 2014-06-24 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
| US8841779B2 (en) | 2005-03-25 | 2014-09-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate |
| US9029196B2 (en) | 2003-11-10 | 2015-05-12 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| US9064858B2 (en) | 2003-11-10 | 2015-06-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming bump-on-lead interconnection |
| US9125332B2 (en) | 2008-03-25 | 2015-09-01 | Stats Chippac, Ltd. | Filp chip interconnection structure with bump on partial pad and method thereof |
| US9258904B2 (en) | 2005-05-16 | 2016-02-09 | Stats Chippac, Ltd. | Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings |
| US9345148B2 (en) | 2008-03-25 | 2016-05-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad |
| US9780057B2 (en) | 2003-11-08 | 2017-10-03 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming pad layout for flipchip semiconductor die |
| US9847309B2 (en) | 2006-09-22 | 2017-12-19 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate |
| US10388626B2 (en) | 2000-03-10 | 2019-08-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming flipchip interconnect structure |
| USRE47600E1 (en) | 2003-11-10 | 2019-09-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
-
1998
- 1998-07-07 JP JP10208599A patent/JP2000031204A/en not_active Withdrawn
Cited By (62)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10388626B2 (en) | 2000-03-10 | 2019-08-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming flipchip interconnect structure |
| US8697490B2 (en) | 2000-03-10 | 2014-04-15 | Stats Chippac, Ltd. | Flip chip interconnection structure |
| US8129837B2 (en) | 2003-11-08 | 2012-03-06 | Stats Chippac, Ltd. | Flip chip interconnection pad layout |
| US9780057B2 (en) | 2003-11-08 | 2017-10-03 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming pad layout for flipchip semiconductor die |
| USRE44524E1 (en) | 2003-11-10 | 2013-10-08 | Stats Chippac, Ltd. | Bump-on-lead flip chip interconnection |
| US9865556B2 (en) | 2003-11-10 | 2018-01-09 | STATS ChipPAC Pte Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| USRE44579E1 (en) | 2003-11-10 | 2013-11-05 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| USRE47600E1 (en) | 2003-11-10 | 2019-09-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
| US9373573B2 (en) | 2003-11-10 | 2016-06-21 | STATS ChipPAC Pte. Ltd. | Solder joint flip chip interconnection |
| US9219045B2 (en) | 2003-11-10 | 2015-12-22 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| US9064858B2 (en) | 2003-11-10 | 2015-06-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming bump-on-lead interconnection |
| USRE44562E1 (en) | 2003-11-10 | 2013-10-29 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
| US9029196B2 (en) | 2003-11-10 | 2015-05-12 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| US9922915B2 (en) | 2003-11-10 | 2018-03-20 | STATS ChipPAC Pte. Ltd. | Bump-on-lead flip chip interconnection |
| US9899286B2 (en) | 2003-11-10 | 2018-02-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| USRE44608E1 (en) | 2003-11-10 | 2013-11-26 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
| US9773685B2 (en) | 2003-11-10 | 2017-09-26 | STATS ChipPAC Pte. Ltd. | Solder joint flip chip interconnection having relief structure |
| USRE44355E1 (en) | 2003-11-10 | 2013-07-09 | Stats Chippac, Ltd. | Method of forming a bump-on-lead flip chip interconnection having higher escape routing density |
| USRE44377E1 (en) | 2003-11-10 | 2013-07-16 | Stats Chippac, Ltd. | Bump-on-lead flip chip interconnection |
| US9385101B2 (en) | 2003-11-10 | 2016-07-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming bump-on-lead interconnection |
| US8810029B2 (en) | 2003-11-10 | 2014-08-19 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
| USRE44500E1 (en) | 2003-11-10 | 2013-09-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
| US9379084B2 (en) | 2003-11-10 | 2016-06-28 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
| US8558378B2 (en) | 2003-11-10 | 2013-10-15 | Stats Chippac, Ltd. | Bump-on-lead flip chip interconnection |
| US8759972B2 (en) | 2003-11-10 | 2014-06-24 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
| US8188598B2 (en) | 2003-11-10 | 2012-05-29 | Stats Chippac, Ltd. | Bump-on-lead flip chip interconnection |
| USRE44761E1 (en) | 2003-11-10 | 2014-02-11 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
| US10580749B2 (en) | 2005-03-25 | 2020-03-03 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming high routing density interconnect sites on substrate |
| US8318537B2 (en) | 2005-03-25 | 2012-11-27 | Stats Chippac, Ltd. | Flip chip interconnection having narrow interconnection sites on the substrate |
| US9159665B2 (en) | 2005-03-25 | 2015-10-13 | Stats Chippac, Ltd. | Flip chip interconnection having narrow interconnection sites on the substrate |
| JP2008535225A (en) * | 2005-03-25 | 2008-08-28 | スタッツ チップパック リミテッド | Flip chip wiring having a narrow wiring portion on a substrate |
| US8841779B2 (en) | 2005-03-25 | 2014-09-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate |
| US9545014B2 (en) | 2005-05-16 | 2017-01-10 | STATS ChipPAC Pte. Ltd. | Flip chip interconnect solder mask |
| US9545013B2 (en) | 2005-05-16 | 2017-01-10 | STATS ChipPAC Pte. Ltd. | Flip chip interconnect solder mask |
| US9258904B2 (en) | 2005-05-16 | 2016-02-09 | Stats Chippac, Ltd. | Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings |
| US8278144B2 (en) | 2005-05-16 | 2012-10-02 | Stats Chippac, Ltd. | Flip chip interconnect solder mask |
| US8525350B2 (en) | 2006-09-22 | 2013-09-03 | Stats Chippac, Ltd. | Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud bumps |
| US8193035B2 (en) | 2006-09-22 | 2012-06-05 | Stats Chippac, Ltd. | Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud bumps |
| US9847309B2 (en) | 2006-09-22 | 2017-12-19 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate |
| US8129841B2 (en) | 2006-12-14 | 2012-03-06 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
| US8216930B2 (en) | 2006-12-14 | 2012-07-10 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
| JP2009016633A (en) * | 2007-07-06 | 2009-01-22 | Panasonic Corp | Conductive bump, its manufacturing method, electronic component mounting structure using same, and its manufacturing method |
| US9418913B2 (en) | 2008-03-19 | 2016-08-16 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding |
| US8349721B2 (en) | 2008-03-19 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding |
| US9125332B2 (en) | 2008-03-25 | 2015-09-01 | Stats Chippac, Ltd. | Filp chip interconnection structure with bump on partial pad and method thereof |
| US9345148B2 (en) | 2008-03-25 | 2016-05-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad |
| US8742566B2 (en) | 2008-09-10 | 2014-06-03 | Stats Chippac, Ltd. | Semiconductor device having vertically offset bond on trace interconnects on recessed and raised bond fingers |
| US8389398B2 (en) | 2008-09-10 | 2013-03-05 | Stats Chippac, Ltd. | Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers |
| US8169071B2 (en) | 2008-09-10 | 2012-05-01 | Stats Chippac, Ltd. | Semiconductor device having vertically offset bond on trace interconnects on recessed and raised bond fingers |
| US8884430B2 (en) | 2008-12-31 | 2014-11-11 | Stats Chippac, Ltd. | Semiconductor device and method of confining conductive bump material during reflow with solder mask patch |
| US8741766B2 (en) | 2008-12-31 | 2014-06-03 | Stats Chippac, Ltd. | Semiconductor device and method of confining conductive bump material during reflow with solder mask patch |
| US8659172B2 (en) | 2008-12-31 | 2014-02-25 | Stats Chippac, Ltd. | Semiconductor device and method of confining conductive bump material with solder mask patch |
| US9679811B2 (en) | 2008-12-31 | 2017-06-13 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of confining conductive bump material with solder mask patch |
| US8198186B2 (en) | 2008-12-31 | 2012-06-12 | Stats Chippac, Ltd. | Semiconductor device and method of confining conductive bump material during reflow with solder mask patch |
| US8476761B2 (en) | 2008-12-31 | 2013-07-02 | Stats Chippac, Ltd. | Semiconductor device and method of confining conductive bump material during reflow with solder mask patch |
| US8350384B2 (en) | 2009-11-24 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
| US8563418B2 (en) | 2010-03-09 | 2013-10-22 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces |
| US8409978B2 (en) | 2010-06-24 | 2013-04-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe |
| US8492197B2 (en) | 2010-08-17 | 2013-07-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate |
| US8896133B2 (en) | 2010-08-17 | 2014-11-25 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate |
| US8435834B2 (en) | 2010-09-13 | 2013-05-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP |
| US9679824B2 (en) | 2010-09-13 | 2017-06-13 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in Fo-WLCSP |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2000031204A (en) | Manufacture of semiconductor package | |
| US6796025B2 (en) | Method for mounting electronic part and paste material | |
| JP3829325B2 (en) | Semiconductor element, manufacturing method thereof, and manufacturing method of semiconductor device | |
| US6164523A (en) | Electronic component and method of manufacture | |
| JP3565047B2 (en) | Solder bump forming method and solder bump mounting method | |
| KR101328551B1 (en) | Semiconductor devices | |
| US20140113411A1 (en) | Semiconductor device and method for manufacturing thereof | |
| JPH1050708A (en) | Metal bump, manufacture thereof and connection structure | |
| US20140312513A1 (en) | Semiconductor device, substrate and semiconductor device manufacturing method | |
| JPH10163213A (en) | Manufacture of semiconductor device and mounting method of semiconductor device | |
| JP2001085470A (en) | Semiconductor device and manufacturing method therefor | |
| KR20020044577A (en) | Advanced flip-chip join package | |
| JP3356649B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2001060760A (en) | Circuit electrode and formation process thereof | |
| KR100715410B1 (en) | Hybrid integrated circuit | |
| JPH07288255A (en) | Formation of solder bump | |
| US20080212301A1 (en) | Electronic part mounting board and method of mounting the same | |
| JP3417281B2 (en) | How to mount electronic components with bumps | |
| JP3024506B2 (en) | Connection method between Si chip and package | |
| JPH09148693A (en) | Flip chip mounting board and manufacture thereof | |
| JPH07273146A (en) | Mounting method for semiconductor device | |
| JP3078781B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
| JP2002164473A (en) | Semiconductor device and method for manufacturing the same | |
| KR101046377B1 (en) | Printed circuit board for semiconductor package and manufacturing method thereof | |
| JPH11224886A (en) | Semiconductor device mounting structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20051004 |