JP2000022286A - 電子回路装置 - Google Patents
電子回路装置Info
- Publication number
- JP2000022286A JP2000022286A JP10185058A JP18505898A JP2000022286A JP 2000022286 A JP2000022286 A JP 2000022286A JP 10185058 A JP10185058 A JP 10185058A JP 18505898 A JP18505898 A JP 18505898A JP 2000022286 A JP2000022286 A JP 2000022286A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- electronic circuit
- circuit device
- circuit board
- underfill
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 230000002787 reinforcement Effects 0.000 claims description 7
- 229920001721 polyimide Polymers 0.000 abstract description 11
- 239000004642 Polyimide Substances 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 230000003014 reinforcing effect Effects 0.000 abstract description 4
- 230000008859 change Effects 0.000 abstract description 2
- 230000007613 environmental effect Effects 0.000 abstract 1
- 230000035699 permeability Effects 0.000 abstract 1
- 239000000853 adhesive Substances 0.000 description 10
- 230000001070 adhesive effect Effects 0.000 description 10
- 239000011230 binding agent Substances 0.000 description 9
- 238000007747 plating Methods 0.000 description 8
- 229910015363 Au—Sn Inorganic materials 0.000 description 3
- 239000003054 catalyst Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
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- H—ELECTRICITY
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- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01033—Arsenic [As]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/0105—Tin [Sn]
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- H01L2924/01078—Platinum [Pt]
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- H01L2924/01079—Gold [Au]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/11—Device type
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Wire Bonding (AREA)
- Structure Of Printed Boards (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
頼性の高い半導体装置を得る。 【解決手段】 ポリイミドフイルム等の絶縁基板上にパ
ターンが形成してある回路基板のIC接続用端子と隣接
して接着補強を目的としたパターンを配置し、ICと回
路基板の接着力が向上することで温度変化による信頼性
が向上する。また、ポリイミドなど透湿性の高い基板に
対しては耐湿による信頼性が向上する。
Description
帳に使用されている液晶を駆動するためのドライバーI
Cやメモリーやコントローラ等のベアチップ実装してい
る電子回路装置に関する。
回路基板と半導体素子を接着を用いて接続する場合、I
CのパットにAuからなるバンプをメッキで形成したメ
ッキバンプやワイヤーボンディングを応用したスタッド
バンプを用いて、回路基板に異方性導電膜で圧着する
か、または銀ペーストをバンプに転写して基板と接続
し、その間にアンダーフィルを充填し接続していた。
合、ICのバンプに半田を用い、基板の電極に半田付け
しアンダーフィルを充填する工法とICのバンプにAu
を用い基板側の電極にSnメッキを行ない、Au−Sn
拡散接続を行いアンダーフィルを充填していた。
性は、どの接続方式においてもアンダーフィルまたは、
異方性導電膜のバインダーの特性が非常に重要である。
アンダーフィルや異方性導電膜のバインダーは、ICと
回路基板の線膨張係数の違いによる長期信頼性を得るた
めに、硬化時の拘束力や線膨張係数,ヤング率などの特
性が重要である。
に、実装したICのバンプより中央側の絶縁基板とアン
ダーフィルまたは異方性導電膜のバインダーの剥がれに
よって接続がオープンになる。特にポリイミドフイルム
にCuを蒸着及びメッキにより形成したフイルム基板に
半導体ICを実装したCOFの場合、ポリイミドとの接
着性が非常に悪いため、信頼性が向上しなかった。
る。
に、少なくとも回路基板にICがフェイスダウン実装し
ている電子回路装置において、 ICと回路基板の接続
は、電極の接続部以外のエリアに接着剤からなるアンダ
ーフィルや異方性導電膜ではバインダーによりICの回
路面と回路基板を接着補強する。
ーンが形成されており、そのパターンに隣接してダミー
もしくは一部の電気信号端子と接続したパターンを形成
して、ポリイミド等よりなる絶縁基板との接着エリアを
少なくし、ポリイミド等より接着力の高いパターンとの
接着エリアを大きくすることで、信頼性を向上した。上
記のように構成した電子回路装置は、温度変化等による
基板とICの熱ストレスによる信頼性が向上し、安定し
た品質の電子回路装置が得られる。
例に示す。
基づいて説明する。図1は本発明の電子回路装置の実施
例1の断面図である。25ミクロンのポリイミドからな
る絶縁基板1に8ミクロンのCuに無電界Niメッキを
し更に置換金メッキをしたパターン2からなる回路基板
であって、信頼性を向上するための接着補強用パターン
3が形成してある。実装はメッキバンプを形成したIC
4を異方性導電膜5で熱圧着して接続した構造である。
接続ピッチは70ミクロンである。接着補強用パターン
3は、ICと接続してあるパターンと全面100ミクロ
ンのスペースをあけて配置した。この構造では異方性導
電膜のバインダーと絶縁基板との接着エリアが大幅に削
減できる。この構造では、接着補強用パターン3を配置
する事で、回路基板の線膨張係数がポリイミドだけの場
合7.2×10-6であるがパターンを配置する事で、
9.9×10-6と大きくなるが、基板との接着力が大幅
に向上するため信頼性が向上した。
より接着力が高い。パターン3は、1つにする必要はな
く、分割して配置しても良しストライプ状に形成して配
置しても良い。 (実施例2)図2は本発明の電子回路装置の実施例2の
断面図である。25ミクロンのポリイミドからなる絶縁
基板1に8ミクロンのCuに無電界Snメッキをした回
路基板であって、接着補強用のパターン3が形成してあ
る。ICにはメッキバンプを形成したIC4を熱圧着で
Au−Sn接続を行なった。
ン3のエリアを充填できるアンダーフィル1を塗布して
おき、ICを位置合わせし仮置きする。この時パターン
3とIC4の間にアンダーフィル1が充填できる。次に
Au−Sn接続する温度と圧力で熱圧着する。この時同
時にアンダーフィル1は硬化する。このアンダーフィル
1はポリイミドよりSnメッキへの接着力が高い。
化型のアンダーフィル2を塗布し紫外線で硬化する。ア
ンダーフィル2は、基本的にはUV硬化であるが、嫌気
性を触媒として硬化が進む特性の接着剤を用いる事でU
Vが当たらない部分も最終的には硬化することが出来
る。
化が進む特性の接着剤でも熱硬化性接着剤でも良い。上
記の様にアンダーフィルを2つの工程に分けて充填する
必要はなく、接続後にICの側面に塗布し、毛細管現象
で充填し硬化しても良い。
フィルや異方性導電膜のバインダーと絶縁基板の接着力
が弱い接着剤でも接着補強用パターンを配置する事でI
Cの接続信頼性を向上する事が出来る。また、COFの
場合ポリイミドは耐湿性が悪いが、この接着補強用パタ
ーンが防湿バリアとなり一層信頼性を向上する事ができ
た。また、異方性導電膜の場合、ICのバンプと回路基
板のパターンを粒子で接続するがバインダーはこの粒子
を押え込む拘束力が必要である。この拘束力は温度によ
ってバインダーが緩むことで低下する。この緩みは線膨
張係数に依存するが、本発明のパターンによってバイン
ダーの層を薄く出来るので、緩む量が減り一層信頼性が
向上できた。
ン上面図
Claims (2)
- 【請求項1】 少なくとも絶縁基板にパターンが形成し
てある回路基板に、ICがフェイスダウン実装してある
電子回路装置において、 回路基板は、ICと接続するパターンが形成しており、
そのパターンに隣接してダミーもしくは一部の電気信号
端子と接続した接着補強用のパターンを形成してある事
を特徴とする電子回路装置。 - 【請求項2】 絶縁基板にパターン有する回路基板に、
ICがフェイスダウン実装された電子回路装置におい
て、 前記回路基板は、前記ICと電気的に接続する複数のパ
ターンを有し、前記複数のパターンに離間して配置した
ダミーまたは一部の電気信号端子と接続した接着補強用
のパターンを有する事を特徴とする電子回路装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18505898A JP3278055B2 (ja) | 1998-06-30 | 1998-06-30 | 電子回路装置 |
TW088110204A TW451605B (en) | 1998-06-30 | 1999-06-17 | Electronic circuit device |
EP99305052A EP0969503A3 (en) | 1998-06-30 | 1999-06-28 | Electronic circuit device |
US09/342,424 US6528889B1 (en) | 1998-06-30 | 1999-06-29 | Electronic circuit device having adhesion-reinforcing pattern on a circuit board for flip-chip mounting an IC chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18505898A JP3278055B2 (ja) | 1998-06-30 | 1998-06-30 | 電子回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2000022286A true JP2000022286A (ja) | 2000-01-21 |
JP3278055B2 JP3278055B2 (ja) | 2002-04-30 |
Family
ID=16164077
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18505898A Expired - Lifetime JP3278055B2 (ja) | 1998-06-30 | 1998-06-30 | 電子回路装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US6528889B1 (ja) |
EP (1) | EP0969503A3 (ja) |
JP (1) | JP3278055B2 (ja) |
TW (1) | TW451605B (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2007281172A (ja) * | 2006-04-06 | 2007-10-25 | Alps Electric Co Ltd | 電子部品実装構造及びその製造方法 |
KR100919985B1 (ko) * | 2002-10-22 | 2009-10-05 | 삼성테크윈 주식회사 | 반도체 팩키지용 필름 기판 및 이를 이용한 반도체 팩키지 |
JP2012033590A (ja) * | 2010-07-29 | 2012-02-16 | Casio Comput Co Ltd | 基板の接着方法、基板の実装構造、電子機器、及び基板 |
JP2016092400A (ja) * | 2014-11-04 | 2016-05-23 | 株式会社リコー | 配線部材の保持構造、液体吐出ヘッド及び液体を吐出する装置 |
Families Citing this family (12)
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CN1143373C (zh) * | 1998-07-01 | 2004-03-24 | 精工爱普生株式会社 | 半导体装置及其制造方法、电路基板和电子装置 |
US20030038356A1 (en) * | 2001-08-24 | 2003-02-27 | Derderian James M | Semiconductor devices including stacking spacers thereon, assemblies including the semiconductor devices, and methods |
JP3914732B2 (ja) * | 2001-10-02 | 2007-05-16 | 鹿児島日本電気株式会社 | 回路基板の接続構造及び該接続構造を備えた液晶表示装置並びに液晶表示装置の実装方法 |
CN100403778C (zh) * | 2003-04-22 | 2008-07-16 | 柯尼卡美能达精密光学株式会社 | 成像装置和安装该成像装置的便携式终端设备 |
US20050110126A1 (en) * | 2003-11-25 | 2005-05-26 | Kai-Chiang Wu | Chip adhesive |
JP3833669B2 (ja) * | 2004-04-08 | 2006-10-18 | シャープ株式会社 | 半導体装置および半導体装置の製造方法 |
TWI305390B (en) * | 2005-09-07 | 2009-01-11 | Ind Tech Res Inst | Chip structure, chip package structure and manufacturing thereof |
JP5147678B2 (ja) * | 2008-12-24 | 2013-02-20 | 新光電気工業株式会社 | 微細配線パッケージの製造方法 |
TWI384603B (zh) * | 2009-02-17 | 2013-02-01 | Advanced Semiconductor Eng | 基板結構及應用其之封裝結構 |
US9373559B2 (en) * | 2014-03-05 | 2016-06-21 | International Business Machines Corporation | Low-stress dual underfill packaging |
JP6430843B2 (ja) * | 2015-01-30 | 2018-11-28 | 株式会社ジェイデバイス | 半導体装置 |
WO2018159023A1 (ja) * | 2017-03-01 | 2018-09-07 | 住友電気工業株式会社 | フレキシブルプリント配線板、接続体の製造方法及び接続体 |
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US3871015A (en) * | 1969-08-14 | 1975-03-11 | Ibm | Flip chip module with non-uniform connector joints |
JPS57176738A (en) * | 1981-04-23 | 1982-10-30 | Seiko Epson Corp | Connecting structure for flip chip |
US4937653A (en) * | 1988-07-21 | 1990-06-26 | American Telephone And Telegraph Company | Semiconductor integrated circuit chip-to-chip interconnection scheme |
JPH02185050A (ja) * | 1989-01-12 | 1990-07-19 | Matsushita Electric Ind Co Ltd | 半導体装置の実装方法 |
JP2833111B2 (ja) * | 1989-03-09 | 1998-12-09 | 日立化成工業株式会社 | 回路の接続方法及びそれに用いる接着剤フィルム |
JPH0379063A (ja) * | 1989-08-22 | 1991-04-04 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2956199B2 (ja) * | 1990-11-06 | 1999-10-04 | セイコーエプソン株式会社 | 半導体装置の構造 |
JPH0637143A (ja) * | 1992-07-15 | 1994-02-10 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
JP3194553B2 (ja) * | 1993-08-13 | 2001-07-30 | 富士通株式会社 | 半導体装置の製造方法 |
US5400950A (en) * | 1994-02-22 | 1995-03-28 | Delco Electronics Corporation | Method for controlling solder bump height for flip chip integrated circuit devices |
KR100194130B1 (ko) * | 1994-03-30 | 1999-06-15 | 니시무로 타이죠 | 반도체 패키지 |
JP2571024B2 (ja) * | 1994-09-28 | 1997-01-16 | 日本電気株式会社 | マルチチップモジュール |
DE69618458T2 (de) * | 1995-05-22 | 2002-11-07 | Hitachi Chemical Co Ltd | Halbleiterteil mit einem zu einem verdrahtungsträger elektrisch verbundenem chip |
JPH09306954A (ja) * | 1996-05-20 | 1997-11-28 | Hitachi Ltd | 半導体装置及びその実装方法並びに実装構造体 |
JPH10144727A (ja) * | 1996-11-14 | 1998-05-29 | Matsushita Electric Ind Co Ltd | 半導体素子の実装方法および半導体素子を実装した電子装置 |
JPH10163608A (ja) * | 1996-11-29 | 1998-06-19 | Nec Corp | プリント配線板及びその製造方法 |
US5953814A (en) * | 1998-02-27 | 1999-09-21 | Delco Electronics Corp. | Process for producing flip chip circuit board assembly exhibiting enhanced reliability |
-
1998
- 1998-06-30 JP JP18505898A patent/JP3278055B2/ja not_active Expired - Lifetime
-
1999
- 1999-06-17 TW TW088110204A patent/TW451605B/zh not_active IP Right Cessation
- 1999-06-28 EP EP99305052A patent/EP0969503A3/en not_active Ceased
- 1999-06-29 US US09/342,424 patent/US6528889B1/en not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100919985B1 (ko) * | 2002-10-22 | 2009-10-05 | 삼성테크윈 주식회사 | 반도체 팩키지용 필름 기판 및 이를 이용한 반도체 팩키지 |
JP2007281172A (ja) * | 2006-04-06 | 2007-10-25 | Alps Electric Co Ltd | 電子部品実装構造及びその製造方法 |
JP2012033590A (ja) * | 2010-07-29 | 2012-02-16 | Casio Comput Co Ltd | 基板の接着方法、基板の実装構造、電子機器、及び基板 |
JP2016092400A (ja) * | 2014-11-04 | 2016-05-23 | 株式会社リコー | 配線部材の保持構造、液体吐出ヘッド及び液体を吐出する装置 |
Also Published As
Publication number | Publication date |
---|---|
TW451605B (en) | 2001-08-21 |
EP0969503A3 (en) | 2002-03-20 |
US6528889B1 (en) | 2003-03-04 |
JP3278055B2 (ja) | 2002-04-30 |
EP0969503A2 (en) | 2000-01-05 |
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