ITMI20050799A1 - Metodo e sistema di configurazione dei parametri per una memoria flash - Google Patents

Metodo e sistema di configurazione dei parametri per una memoria flash

Info

Publication number
ITMI20050799A1
ITMI20050799A1 IT000799A ITMI20050799A ITMI20050799A1 IT MI20050799 A1 ITMI20050799 A1 IT MI20050799A1 IT 000799 A IT000799 A IT 000799A IT MI20050799 A ITMI20050799 A IT MI20050799A IT MI20050799 A1 ITMI20050799 A1 IT MI20050799A1
Authority
IT
Italy
Prior art keywords
parameters
flash memory
configuration system
configuration
flash
Prior art date
Application number
IT000799A
Other languages
English (en)
Inventor
Simone Bartoli
Giorgio Bosisio
Mirella Marsella
Stefano Surico
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Priority to IT000799A priority Critical patent/ITMI20050799A1/it
Priority to US11/272,206 priority patent/US7181565B2/en
Priority to TW095115688A priority patent/TW200707441A/zh
Priority to PCT/US2006/017096 priority patent/WO2006119404A2/en
Publication of ITMI20050799A1 publication Critical patent/ITMI20050799A1/it
Priority to US11/635,315 priority patent/US7249215B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/20—Initialising; Data preset; Chip identification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
IT000799A 2005-05-03 2005-05-03 Metodo e sistema di configurazione dei parametri per una memoria flash ITMI20050799A1 (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT000799A ITMI20050799A1 (it) 2005-05-03 2005-05-03 Metodo e sistema di configurazione dei parametri per una memoria flash
US11/272,206 US7181565B2 (en) 2005-05-03 2005-11-10 Method and system for configuring parameters for flash memory
TW095115688A TW200707441A (en) 2005-05-03 2006-05-03 Method and system for configuring parameters for a flash memory
PCT/US2006/017096 WO2006119404A2 (en) 2005-05-03 2006-05-03 Method and system for configuring parameters for a flash memory
US11/635,315 US7249215B2 (en) 2005-05-03 2006-12-07 System for configuring parameters for a flash memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT000799A ITMI20050799A1 (it) 2005-05-03 2005-05-03 Metodo e sistema di configurazione dei parametri per una memoria flash

Publications (1)

Publication Number Publication Date
ITMI20050799A1 true ITMI20050799A1 (it) 2006-11-04

Family

ID=37395307

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000799A ITMI20050799A1 (it) 2005-05-03 2005-05-03 Metodo e sistema di configurazione dei parametri per una memoria flash

Country Status (4)

Country Link
US (2) US7181565B2 (it)
IT (1) ITMI20050799A1 (it)
TW (1) TW200707441A (it)
WO (1) WO2006119404A2 (it)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7720556B2 (en) * 2005-12-21 2010-05-18 Lsi Corporation Web-enabled solutions for memory compilation to support pre-sales estimation of memory size, performance and power data for memory components
KR100936149B1 (ko) * 2006-12-29 2010-01-12 삼성전자주식회사 복수의 비휘발성 메모리를 갖는 메모리 시스템 그것의 메모리 억세스 방법
US7414891B2 (en) 2007-01-04 2008-08-19 Atmel Corporation Erase verify method for NAND-type flash memories
US8002332B2 (en) 2007-01-30 2011-08-23 Zephyros, Inc. Structural mounting insert
US7882405B2 (en) * 2007-02-16 2011-02-01 Atmel Corporation Embedded architecture with serial interface for testing flash memories
US20080232169A1 (en) * 2007-03-20 2008-09-25 Atmel Corporation Nand-like memory array employing high-density nor-like memory devices
US8181327B2 (en) 2008-02-08 2012-05-22 Zephyros, Inc Mechanical method for improving bond joint strength
US9194408B2 (en) 2008-02-08 2015-11-24 Zephyros, Inc. Mechanical method for improving bond joint strength
US7957187B2 (en) * 2008-05-09 2011-06-07 Sandisk Corporation Dynamic and adaptive optimization of read compare levels based on memory cell threshold voltage distribution
US20100112968A1 (en) * 2008-10-30 2010-05-06 Motorola, Inc. Method and apparatus for cloning contents of a source radio into a target radio
US7984919B2 (en) 2009-05-18 2011-07-26 Zephyros, Inc. Structural mounting insert having a non-conductive isolator
US9311102B2 (en) * 2010-07-13 2016-04-12 Advanced Micro Devices, Inc. Dynamic control of SIMDs
WO2012125995A1 (en) 2011-03-17 2012-09-20 Zephyros, Inc. Bonding assembly
JP2012203951A (ja) * 2011-03-24 2012-10-22 Toshiba Corp 半導体記憶装置
US10481992B1 (en) * 2011-03-31 2019-11-19 EMC IP Holding Company LLC Optimization of flash storage
US9257162B2 (en) 2012-06-18 2016-02-09 Intel Corporation Alternate control settings
US8938597B2 (en) 2012-10-23 2015-01-20 Seagate Technology Llc Restoring virtualized GCU state information
US9076545B2 (en) 2013-01-17 2015-07-07 Sandisk Tecnologies Inc. Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution
US9251053B2 (en) * 2013-03-14 2016-02-02 SanDisk Technologies, Inc. Managing configuration parameters for a non-volatile medium
US8766707B1 (en) 2013-03-15 2014-07-01 Seagate Technology Llc Integrated always on power island for low power mode operation
US9335809B2 (en) 2013-03-15 2016-05-10 Seagate Technology Llc Volatile memory storing system data during low power mode operation and monitoring the voltage supplied to the memory during low power mode
US9411394B2 (en) 2013-03-15 2016-08-09 Seagate Technology Llc PHY based wake up from low power mode operation
GB201318595D0 (en) 2013-10-21 2013-12-04 Zephyros Inc Improvements in or relating to laminates
WO2015095325A1 (en) 2013-12-17 2015-06-25 Zephyros, Inc. Carrier with localized fibrous insert and methods
US10713392B2 (en) * 2017-09-29 2020-07-14 Xilinx, Inc. Network interface device and method
US10721072B2 (en) * 2017-09-29 2020-07-21 Xilinx, Inc. Network interface device and method

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW261687B (it) * 1991-11-26 1995-11-01 Hitachi Seisakusyo Kk
US6347051B2 (en) * 1991-11-26 2002-02-12 Hitachi, Ltd. Storage device employing a flash memory
US20010011318A1 (en) * 1997-02-27 2001-08-02 Vishram P. Dalvi Status indicators for flash memory
US7346479B2 (en) * 1998-09-04 2008-03-18 Intel Corporation Selecting design points on parameter functions having first sum of constraint set and second sum of optimizing set to improve second sum within design constraints
US6278633B1 (en) * 1999-11-05 2001-08-21 Multi Level Memory Technology High bandwidth flash memory that selects programming parameters according to measurements of previous programming operations
JP4475709B2 (ja) * 1999-11-15 2010-06-09 株式会社ルネサステクノロジ マイクロコンピュータ
US6327552B2 (en) * 1999-12-28 2001-12-04 Intel Corporation Method and system for determining optimal delay allocation to datapath blocks based on area-delay and power-delay curves
US6396744B1 (en) * 2000-04-25 2002-05-28 Multi Level Memory Technology Flash memory with dynamic refresh
US6721843B1 (en) * 2000-07-07 2004-04-13 Lexar Media, Inc. Flash memory architecture implementing simultaneously programmable multiple flash memory banks that are host compatible
JP2002050703A (ja) 2000-08-01 2002-02-15 Hitachi Ltd 多値不揮発性半導体記憶装置
US6549482B2 (en) * 2001-03-23 2003-04-15 Intel Corporation Method and apparatus to provide real-time access to flash memory features
US6925558B2 (en) * 2001-03-29 2005-08-02 Intel Corporation System and method for selecting and loading configuration data into a register through the use of a first and second reset signal
ITRM20010556A1 (it) * 2001-09-12 2003-03-12 Micron Technology Inc Decodificatore per decodificare i comandi di commutazione a modo di test di circuiti integrati.
AU2003223746A1 (en) * 2002-04-25 2003-11-10 Arc International Apparatus and method for managing integrated circuit designs
US6907496B2 (en) * 2002-05-02 2005-06-14 International Business Machines Corporation Method and apparatus for auto-detection of a configuration of a flash memory
US20040049628A1 (en) 2002-09-10 2004-03-11 Fong-Long Lin Multi-tasking non-volatile memory subsystem
US20050086456A1 (en) * 2003-09-29 2005-04-21 Yaron Elboim Addressing scheme to load configuration registers

Also Published As

Publication number Publication date
WO2006119404A3 (en) 2007-04-05
US20070083699A1 (en) 2007-04-12
TW200707441A (en) 2007-02-16
US7181565B2 (en) 2007-02-20
US20060253644A1 (en) 2006-11-09
US7249215B2 (en) 2007-07-24
WO2006119404A2 (en) 2006-11-09

Similar Documents

Publication Publication Date Title
ITMI20050799A1 (it) Metodo e sistema di configurazione dei parametri per una memoria flash
ITMI20050063A1 (it) Metodo e sistema per la gestione di una richiesta di sospensione in una memoria flash
DE602006010481D1 (de) Speichersteuerung und Steuerverfahren dafür
GB2432444B (en) Flash memory device and word line enable method thereof
ITMO20060087A1 (it) Apparato e metodo di elettrostimolazione
ITVA20050061A1 (it) Metodo di gestione di un dispositivo di memoria non volatile e relativa memoria
TWI316207B (en) Memory system and method of writing into nonvolatile semiconductor memory
DE602007000219D1 (de) Nichtflüchtige Speichervorrichtung und Betriebsverfahren dafür
DE602006021036D1 (de) Substituierte benzimidazole und herstellungsverfahren dafür
EP2040292A4 (en) NON-VOLATILE SEMICONDUCTOR MEMORY AND DRIVING METHOD THEREOF
ITBO20070836A1 (it) Sistema e metodo per il controllo di una macchina utensile
FI20061090A (fi) Kunnonvalvontamenetelmä
GB2437447B (en) Memory device having trapezoidal bitlines and method of fabricating same
DE602007013327D1 (de) Halbleiterspeicher und -system
DE602005018561D1 (de) Halbleiterspeicherbauelement und dessen Herstellungsverfahren
EP1993781A4 (en) METHOD FOR MANUFACTURING MEMORY ELEMENT, LASER IRRADIATION APPARATUS, AND LASER IRRADIATION METHOD
ITRM20060417A1 (it) Dispositivo idraulico di agiustamento per il controllo dei flussi e metodo
DE602007009007D1 (de) Halbleiterspeicher und -system
DE602004013816D1 (de) Phasenwechselspeicher und Herstellungsmethode dafür
EP2043145A4 (en) NON-VOLATILE SEMICONDUCTOR MEMORY AND CORRESPONDING DRIVE METHOD
ITMI20041957A1 (it) Dispositivo di memoria
ITMI20051806A1 (it) Sistema e metodo di trattamento di dispostivi contenenti piombo
TWI341531B (en) Recovery method of nand flash memory device
DE602006017777D1 (de) Halbleiterspeicher und dessen Betriebsverfahren
TWI318459B (en) Flash memory device and method of manufacturing the same