IT8025981A0 - Dispositivo di suddivisione di un sotto-sistema centrale di un sistema di trattamento di informazioni, in piu' sotto-sistemi indipendenti. - Google Patents

Dispositivo di suddivisione di un sotto-sistema centrale di un sistema di trattamento di informazioni, in piu' sotto-sistemi indipendenti.

Info

Publication number
IT8025981A0
IT8025981A0 IT8025981A IT2598180A IT8025981A0 IT 8025981 A0 IT8025981 A0 IT 8025981A0 IT 8025981 A IT8025981 A IT 8025981A IT 2598180 A IT2598180 A IT 2598180A IT 8025981 A0 IT8025981 A0 IT 8025981A0
Authority
IT
Italy
Prior art keywords
sub
subdivision
systems
information processing
several independent
Prior art date
Application number
IT8025981A
Other languages
English (en)
Other versions
IT1134273B (it
Inventor
Jacques Michel Jean Bienvenu
Pierre Gabriel Antoine
Robert Jules Adolphe Bavoux
Daniel Rene Vinot
Original Assignee
Cii Honeywell Bull
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cii Honeywell Bull filed Critical Cii Honeywell Bull
Publication of IT8025981A0 publication Critical patent/IT8025981A0/it
Application granted granted Critical
Publication of IT1134273B publication Critical patent/IT1134273B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Hardware Redundancy (AREA)
IT25981/80A 1979-11-14 1980-11-14 Dispositivo di suddivisione di un sotto-sistema centrale di un sistema di trattamento di informazioni,in piu' sotto-sistemi indipendenti IT1134273B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7928076A FR2469752B1 (fr) 1979-11-14 1979-11-14 Dispositif de partage d'un sous-systeme central d'un systeme de traitement de l'information en plusieurs sous-systemes independants

Publications (2)

Publication Number Publication Date
IT8025981A0 true IT8025981A0 (it) 1980-11-14
IT1134273B IT1134273B (it) 1986-08-13

Family

ID=9231670

Family Applications (1)

Application Number Title Priority Date Filing Date
IT25981/80A IT1134273B (it) 1979-11-14 1980-11-14 Dispositivo di suddivisione di un sotto-sistema centrale di un sistema di trattamento di informazioni,in piu' sotto-sistemi indipendenti

Country Status (5)

Country Link
US (1) US4472771A (it)
JP (1) JPS56124955A (it)
DE (1) DE3043012A1 (it)
FR (1) FR2469752B1 (it)
IT (1) IT1134273B (it)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4591975A (en) * 1983-07-18 1986-05-27 Data General Corporation Data processing system having dual processors
US4628463A (en) * 1984-03-05 1986-12-09 Georgia Tech. Research Institute Rapid-sweep electrochemical detector for chemical analysis of flow streams
US4870704A (en) * 1984-10-31 1989-09-26 Flexible Computer Corporation Multicomputer digital processing system
US4972338A (en) * 1985-06-13 1990-11-20 Intel Corporation Memory management for microprocessor system
GB2189061A (en) * 1986-03-10 1987-10-14 Hitachi Ltd Management of system configuration data
US4807184A (en) * 1986-08-11 1989-02-21 Ltv Aerospace Modular multiple processor architecture using distributed cross-point switch
JPH02151926A (ja) * 1988-12-02 1990-06-11 Fujitsu Ltd 端末装置切替方式
US5317707A (en) * 1989-10-20 1994-05-31 Texas Instruments Incorporated Expanded memory interface for supporting expanded, conventional or extended memory for communication between an application processor and an external processor
US5708784A (en) * 1991-11-27 1998-01-13 Emc Corporation Dual bus computer architecture utilizing distributed arbitrators and method of using same
US5471609A (en) * 1992-09-22 1995-11-28 International Business Machines Corporation Method for identifying a system holding a `Reserve`
FR2724243B1 (fr) * 1994-09-06 1997-08-14 Sgs Thomson Microelectronics Systeme de traitement multitaches
US5848231A (en) * 1996-02-12 1998-12-08 Teitelbaum; Neil System configuration contingent upon secure input
DE112005001869A5 (de) * 2004-08-11 2007-07-12 Netchilli Gmbh Vorrichtung und Verfahren zum Konfigurieren einer Datenverarbeitungsanlage

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1054725A (it) * 1964-04-06
US3480914A (en) * 1967-01-03 1969-11-25 Ibm Control mechanism for a multi-processor computing system
US3544973A (en) * 1968-03-13 1970-12-01 Westinghouse Electric Corp Variable structure computer
US3573852A (en) * 1968-08-30 1971-04-06 Texas Instruments Inc Variable time slot assignment of virtual processors
US3581291A (en) * 1968-10-31 1971-05-25 Hitachi Ltd Memory control system in multiprocessing system
US3812468A (en) * 1972-05-12 1974-05-21 Burroughs Corp Multiprocessing system having means for dynamic redesignation of unit functions
JPS5420299B2 (it) * 1974-06-03 1979-07-21
FR2286439A1 (fr) * 1974-09-25 1976-04-23 Data General Corp Appareil de traitement de donnees a recouvrement et imbrication des operations de transfert de donnees
US4014005A (en) * 1976-01-05 1977-03-22 International Business Machines Corporation Configuration and control unit for a heterogeneous multi-system
US4171536A (en) * 1976-05-03 1979-10-16 International Business Machines Corporation Microprocessor system
US4070704A (en) * 1976-05-17 1978-01-24 Honeywell Information Systems Inc. Automatic reconfiguration apparatus for input/output processor
US4096571A (en) * 1976-09-08 1978-06-20 Codex Corporation System for resolving memory access conflicts among processors and minimizing processor waiting times for access to memory by comparing waiting times and breaking ties by an arbitrary priority ranking

Also Published As

Publication number Publication date
FR2469752A1 (fr) 1981-05-22
JPS6133225B2 (it) 1986-08-01
IT1134273B (it) 1986-08-13
DE3043012A1 (de) 1981-06-25
FR2469752B1 (fr) 1986-05-16
US4472771A (en) 1984-09-18
JPS56124955A (en) 1981-09-30
DE3043012C2 (it) 1988-06-23

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971103