IT1319937B1 - Dispositivo integrato con verifica di funzionalita'. - Google Patents

Dispositivo integrato con verifica di funzionalita'.

Info

Publication number
IT1319937B1
IT1319937B1 IT2000TO000207A ITTO20000207A IT1319937B1 IT 1319937 B1 IT1319937 B1 IT 1319937B1 IT 2000TO000207 A IT2000TO000207 A IT 2000TO000207A IT TO20000207 A ITTO20000207 A IT TO20000207A IT 1319937 B1 IT1319937 B1 IT 1319937B1
Authority
IT
Italy
Prior art keywords
integrated device
functionality verification
verification
functionality
integrated
Prior art date
Application number
IT2000TO000207A
Other languages
English (en)
Inventor
Stefano Zanardi
Maurizio Branchetti
Jacopo Mulatti
Massimiliano Picca
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT2000TO000207A priority Critical patent/IT1319937B1/it
Publication of ITTO20000207A0 publication Critical patent/ITTO20000207A0/it
Priority to US09/798,347 priority patent/US6898745B2/en
Publication of ITTO20000207A1 publication Critical patent/ITTO20000207A1/it
Application granted granted Critical
Publication of IT1319937B1 publication Critical patent/IT1319937B1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Inspection Of Paper Currency And Valuable Securities (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Debugging And Monitoring (AREA)
IT2000TO000207A 2000-03-03 2000-03-03 Dispositivo integrato con verifica di funzionalita'. IT1319937B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT2000TO000207A IT1319937B1 (it) 2000-03-03 2000-03-03 Dispositivo integrato con verifica di funzionalita'.
US09/798,347 US6898745B2 (en) 2000-03-03 2001-03-02 Integrated device with operativity testing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2000TO000207A IT1319937B1 (it) 2000-03-03 2000-03-03 Dispositivo integrato con verifica di funzionalita'.

Publications (3)

Publication Number Publication Date
ITTO20000207A0 ITTO20000207A0 (it) 2000-03-03
ITTO20000207A1 ITTO20000207A1 (it) 2001-09-03
IT1319937B1 true IT1319937B1 (it) 2003-11-12

Family

ID=11457531

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2000TO000207A IT1319937B1 (it) 2000-03-03 2000-03-03 Dispositivo integrato con verifica di funzionalita'.

Country Status (2)

Country Link
US (1) US6898745B2 (it)
IT (1) IT1319937B1 (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7103861B2 (en) * 2004-06-10 2006-09-05 Chartered Semiconductor Manufacturing Ltd. Test structure for automatic dynamic negative-bias temperature instability testing
KR101068568B1 (ko) * 2009-03-30 2011-09-30 주식회사 하이닉스반도체 반도체 장치의 테스트용 인터페이스 보드

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5057715A (en) * 1988-10-11 1991-10-15 Intel Corporation CMOS output circuit using a low threshold device
US5789951A (en) * 1997-01-31 1998-08-04 Motorola, Inc. Monolithic clamping circuit and method of preventing transistor avalanche breakdown
US6157224A (en) * 1998-12-23 2000-12-05 Raytheon Company High speed pin driver integrated circuit architecture for commercial automatic test equipment applications

Also Published As

Publication number Publication date
ITTO20000207A0 (it) 2000-03-03
ITTO20000207A1 (it) 2001-09-03
US6898745B2 (en) 2005-05-24
US20010030568A1 (en) 2001-10-18

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