IT1275781B1 - Apparato di trasferimento dati capace di elaborazione pipeline - Google Patents

Apparato di trasferimento dati capace di elaborazione pipeline

Info

Publication number
IT1275781B1
IT1275781B1 IT95MI002002A ITMI952002A IT1275781B1 IT 1275781 B1 IT1275781 B1 IT 1275781B1 IT 95MI002002 A IT95MI002002 A IT 95MI002002A IT MI952002 A ITMI952002 A IT MI952002A IT 1275781 B1 IT1275781 B1 IT 1275781B1
Authority
IT
Italy
Prior art keywords
data transfer
apparatus capable
transfer apparatus
pipeline processing
pipeline
Prior art date
Application number
IT95MI002002A
Other languages
English (en)
Inventor
Eiichi Nagai
Yoshihiro Takemae
Hirohiko Mochizuki
Yukihiro Nomura
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ITMI952002A0 publication Critical patent/ITMI952002A0/it
Publication of ITMI952002A1 publication Critical patent/ITMI952002A1/it
Application granted granted Critical
Publication of IT1275781B1 publication Critical patent/IT1275781B1/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Advance Control (AREA)
  • Information Transfer Systems (AREA)
  • Memory System (AREA)
IT95MI002002A 1994-10-06 1995-09-29 Apparato di trasferimento dati capace di elaborazione pipeline IT1275781B1 (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6242658A JPH08106413A (ja) 1994-10-06 1994-10-06 データ処理装置，データ転送方法及びメモリ装置

Publications (3)

Publication Number Publication Date
ITMI952002A0 ITMI952002A0 (it) 1995-09-29
ITMI952002A1 ITMI952002A1 (it) 1997-03-29
IT1275781B1 true IT1275781B1 (it) 1997-10-17

Family

ID=17092321

Family Applications (1)

Application Number Title Priority Date Filing Date
IT95MI002002A IT1275781B1 (it) 1994-10-06 1995-09-29 Apparato di trasferimento dati capace di elaborazione pipeline

Country Status (4)

Country Link
US (1) US5835790A (it)
JP (1) JPH08106413A (it)
KR (1) KR100216113B1 (it)
IT (1) IT1275781B1 (it)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5964866A (en) * 1996-10-24 1999-10-12 International Business Machines Corporation Elastic self-timed interface for data flow elements embodied as selective bypass of stages in an asynchronous microprocessor pipeline
JPH10188556A (ja) * 1996-12-20 1998-07-21 Fujitsu Ltd 半導体記憶装置
US5901086A (en) * 1996-12-26 1999-05-04 Motorola, Inc. Pipelined fast-access floating gate memory architecture and method of operation
KR100279874B1 (ko) * 1998-02-18 2001-03-02 구자홍 브라운관용편향요크
KR100351889B1 (ko) * 1998-11-13 2002-11-18 주식회사 하이닉스반도체 카스(cas)레이턴시(latency) 제어 회로
JP4467727B2 (ja) * 2000-07-24 2010-05-26 キヤノン株式会社 電子機器の接続方法およびその電子機器およびその動作処理プログラムを記憶した記憶媒体
TW201012130A (en) * 2008-09-08 2010-03-16 Brainchild Electronic Co Ltd Remote communication method of a network and system thereof
KR101100228B1 (ko) * 2011-05-25 2011-12-28 엘지전자 주식회사 조명 시스템 및 조명 시스템에서의 주소 설정, 관리 및 제어 방법

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4058773A (en) * 1976-03-15 1977-11-15 Burroughs Corporation Asynchronous self timed queue
JPH0373495A (ja) * 1989-02-15 1991-03-28 Ricoh Co Ltd 半導体メモリ装置
US5121003A (en) * 1990-10-10 1992-06-09 Hal Computer Systems, Inc. Zero overhead self-timed iterative logic
JP3100622B2 (ja) * 1990-11-20 2000-10-16 沖電気工業株式会社 同期型ダイナミックｒａｍ
US5208490A (en) * 1991-04-12 1993-05-04 Hewlett-Packard Company Functionally complete family of self-timed dynamic logic circuits
US5329176A (en) * 1991-04-12 1994-07-12 Hewlett-Packard Company Self-timed clocking system and method for self-timed dynamic logic circuits
US5386585A (en) * 1993-02-03 1995-01-31 Intel Corporation Self-timed data pipeline apparatus using asynchronous stages having toggle flip-flops

Also Published As

Publication number Publication date
ITMI952002A1 (it) 1997-03-29
KR960015269A (ko) 1996-05-22
US5835790A (en) 1998-11-10
JPH08106413A (ja) 1996-04-23
KR100216113B1 (ko) 1999-08-16
ITMI952002A0 (it) 1995-09-29

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Legal Events

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0001 Granted