IT1098670B - Procedimento per la fabbricazione di elementi semiconduttori - Google Patents

Procedimento per la fabbricazione di elementi semiconduttori

Info

Publication number
IT1098670B
IT1098670B IT25515/78A IT2551578A IT1098670B IT 1098670 B IT1098670 B IT 1098670B IT 25515/78 A IT25515/78 A IT 25515/78A IT 2551578 A IT2551578 A IT 2551578A IT 1098670 B IT1098670 B IT 1098670B
Authority
IT
Italy
Prior art keywords
procedure
manufacture
semiconductive elements
semiconductive
elements
Prior art date
Application number
IT25515/78A
Other languages
English (en)
Other versions
IT7825515A0 (it
Original Assignee
Semikron Gleichrichterbau
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semikron Gleichrichterbau filed Critical Semikron Gleichrichterbau
Publication of IT7825515A0 publication Critical patent/IT7825515A0/it
Application granted granted Critical
Publication of IT1098670B publication Critical patent/IT1098670B/it

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Formation Of Insulating Films (AREA)
  • Dicing (AREA)
  • Die Bonding (AREA)
IT25515/78A 1977-07-11 1978-07-10 Procedimento per la fabbricazione di elementi semiconduttori IT1098670B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19772731221 DE2731221A1 (de) 1977-07-11 1977-07-11 Verfahren zum herstellen von halbleiterkoerpern

Publications (2)

Publication Number Publication Date
IT7825515A0 IT7825515A0 (it) 1978-07-10
IT1098670B true IT1098670B (it) 1985-09-07

Family

ID=6013631

Family Applications (1)

Application Number Title Priority Date Filing Date
IT25515/78A IT1098670B (it) 1977-07-11 1978-07-10 Procedimento per la fabbricazione di elementi semiconduttori

Country Status (7)

Country Link
JP (1) JPS5419358A (it)
BR (1) BR7804249A (it)
CH (1) CH629336A5 (it)
DE (1) DE2731221A1 (it)
FR (1) FR2397717A1 (it)
GB (1) GB1604308A (it)
IT (1) IT1098670B (it)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57184597U (it) * 1981-05-20 1982-11-24
DE3211391A1 (de) * 1982-03-27 1983-09-29 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum herstellen einer halbleiteranordnung
DE3435138A1 (de) * 1984-09-25 1986-04-03 Siemens AG, 1000 Berlin und 8000 München Verbesserung zu einem verfahren zum vereinzeln von halbleiter-bauelementen, die durch brechen aus halbleiter-wafern gewonnen sind
DE3524301A1 (de) * 1985-07-06 1987-01-15 Semikron Gleichrichterbau Verfahren zum herstellen von halbleiterelementen
JPS63108706A (ja) * 1986-10-27 1988-05-13 Toshiba Corp 半導体装置の製造方法
JP5903287B2 (ja) * 2012-01-31 2016-04-13 新電元工業株式会社 半導体素子の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4860871A (it) * 1971-11-30 1973-08-25
JPS4976469A (it) * 1972-11-27 1974-07-23
US3972113A (en) * 1973-05-14 1976-08-03 Mitsubishi Denki Kabushiki Kaisha Process of producing semiconductor devices

Also Published As

Publication number Publication date
FR2397717A1 (fr) 1979-02-09
GB1604308A (en) 1981-12-09
DE2731221A1 (de) 1979-02-01
IT7825515A0 (it) 1978-07-10
BR7804249A (pt) 1979-04-10
CH629336A5 (en) 1982-04-15
JPS5419358A (en) 1979-02-14

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