IT1052771B - Dispositivo di indirizzamento di una memoria - Google Patents
Dispositivo di indirizzamento di una memoriaInfo
- Publication number
- IT1052771B IT1052771B IT70231/75A IT7023175A IT1052771B IT 1052771 B IT1052771 B IT 1052771B IT 70231/75 A IT70231/75 A IT 70231/75A IT 7023175 A IT7023175 A IT 7023175A IT 1052771 B IT1052771 B IT 1052771B
- Authority
- IT
- Italy
- Prior art keywords
- memory addressing
- addressing device
- memory
- addressing
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
- G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Memory System (AREA)
- Static Random-Access Memory (AREA)
- Read Only Memory (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT70231/75A IT1052771B (it) | 1975-12-31 | 1975-12-31 | Dispositivo di indirizzamento di una memoria |
US05/717,954 US4156290A (en) | 1975-12-31 | 1976-08-26 | Speedup addressing device by detecting repetitive addressing |
JP51160791A JPS5953630B2 (ja) | 1975-12-31 | 1976-12-29 | メモリ−のアドレス指定装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT70231/75A IT1052771B (it) | 1975-12-31 | 1975-12-31 | Dispositivo di indirizzamento di una memoria |
Publications (1)
Publication Number | Publication Date |
---|---|
IT1052771B true IT1052771B (it) | 1981-07-20 |
Family
ID=11313657
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT70231/75A IT1052771B (it) | 1975-12-31 | 1975-12-31 | Dispositivo di indirizzamento di una memoria |
Country Status (3)
Country | Link |
---|---|
US (1) | US4156290A (it) |
JP (1) | JPS5953630B2 (it) |
IT (1) | IT1052771B (it) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5943786B2 (ja) * | 1979-03-30 | 1984-10-24 | パナフアコム株式会社 | 記憶装置のアクセス方式 |
JPS5658195A (en) * | 1979-10-17 | 1981-05-21 | Seiko Epson Corp | 2-level rom integrated circuit |
JPS5740800A (en) * | 1980-08-22 | 1982-03-06 | Mitsubishi Electric Corp | High-speed readout circuit of sequential storage device |
US4472772A (en) * | 1981-08-03 | 1984-09-18 | Burroughs Corporation | High speed microinstruction execution apparatus |
JPS5919367A (ja) * | 1982-07-26 | 1984-01-31 | Toshiba Corp | メモリ付ゲ−トアレイ |
US4566082A (en) * | 1983-03-23 | 1986-01-21 | Tektronix, Inc. | Memory pack addressing system |
US4688191A (en) * | 1983-11-03 | 1987-08-18 | Amca International Corporation | Single bit storage and retrieval with transition intelligence |
US4747070A (en) * | 1984-01-09 | 1988-05-24 | Wang Laboratories, Inc. | Reconfigurable memory system |
JPS61100848A (ja) * | 1984-10-22 | 1986-05-19 | Fuji Xerox Co Ltd | マイクロコンピユ−タの主記憶装置 |
US4803621A (en) * | 1986-07-24 | 1989-02-07 | Sun Microsystems, Inc. | Memory access system |
US6504550B1 (en) | 1998-05-21 | 2003-01-07 | Mitsubishi Electric & Electronics Usa, Inc. | System for graphics processing employing semiconductor device |
US6559851B1 (en) | 1998-05-21 | 2003-05-06 | Mitsubishi Electric & Electronics Usa, Inc. | Methods for semiconductor systems for graphics processing |
US6535218B1 (en) | 1998-05-21 | 2003-03-18 | Mitsubishi Electric & Electronics Usa, Inc. | Frame buffer memory for graphic processing |
US6661421B1 (en) | 1998-05-21 | 2003-12-09 | Mitsubishi Electric & Electronics Usa, Inc. | Methods for operation of semiconductor memory |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3618040A (en) * | 1968-09-18 | 1971-11-02 | Hitachi Ltd | Memory control apparatus in multiprocessor system |
US3618041A (en) * | 1968-10-31 | 1971-11-02 | Hitachi Ltd | Memory control system |
US3691538A (en) * | 1971-06-01 | 1972-09-12 | Ncr Co | Serial read-out memory system |
-
1975
- 1975-12-31 IT IT70231/75A patent/IT1052771B/it active
-
1976
- 1976-08-26 US US05/717,954 patent/US4156290A/en not_active Expired - Lifetime
- 1976-12-29 JP JP51160791A patent/JPS5953630B2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
US4156290A (en) | 1979-05-22 |
JPS5953630B2 (ja) | 1984-12-26 |
JPS52100941A (en) | 1977-08-24 |
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