IN2014MN01027A - - Google Patents

Info

Publication number
IN2014MN01027A
IN2014MN01027A IN1027MUN2014A IN2014MN01027A IN 2014MN01027 A IN2014MN01027 A IN 2014MN01027A IN 1027MUN2014 A IN1027MUN2014 A IN 1027MUN2014A IN 2014MN01027 A IN2014MN01027 A IN 2014MN01027A
Authority
IN
India
Prior art keywords
substrate layer
layer
wafer
sheet
circuit
Prior art date
Application number
Inventor
Chengjie Zuo
Changhan Yun
Sang June Park
Chi Shun Lo
Mario F Velez
Jonghae Kim
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of IN2014MN01027A publication Critical patent/IN2014MN01027A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Abstract

A chipset (100) includes a sheet (102) of glass quartz or sapphire and a first wafer (104) having at least one first circuit layer (112) on a first side (108) of a first substrate layer (106). The first wafer (104) is connected to the sheet (102) such that the at least one first circuit layer (112) is located between the first substrate layer (106) and the sheet (102). A second wafer (126) having at least one second circuit layer (126) on a first side (122) of a second substrate layer (120) is connected to the first substrate layer (106) such that the at least one second circuit layer (126) is located between the second substrate layer (120) and the first substrate layer (106). A method of forming a chipset is also disclosed.
IN1027MUN2014 2011-11-16 2012-11-16 IN2014MN01027A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201161560471P 2011-11-16 2011-11-16
US13/356,717 US9496255B2 (en) 2011-11-16 2012-01-24 Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same
PCT/US2012/065644 WO2013075007A1 (en) 2011-11-16 2012-11-16 Stacked chipset having an insulating layer and a secondary layer and method of forming same

Publications (1)

Publication Number Publication Date
IN2014MN01027A true IN2014MN01027A (en) 2015-05-01

Family

ID=48280458

Family Applications (1)

Application Number Title Priority Date Filing Date
IN1027MUN2014 IN2014MN01027A (en) 2011-11-16 2012-11-16

Country Status (7)

Country Link
US (1) US9496255B2 (en)
EP (1) EP2780942A1 (en)
JP (2) JP5937225B2 (en)
KR (2) KR101759689B1 (en)
CN (1) CN104054175B (en)
IN (1) IN2014MN01027A (en)
WO (1) WO2013075007A1 (en)

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US10573550B2 (en) 2016-03-07 2020-02-25 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof
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Also Published As

Publication number Publication date
US9496255B2 (en) 2016-11-15
WO2013075007A1 (en) 2013-05-23
EP2780942A1 (en) 2014-09-24
CN104054175A (en) 2014-09-17
KR20160044591A (en) 2016-04-25
US20130120951A1 (en) 2013-05-16
JP2016174170A (en) 2016-09-29
KR20140100526A (en) 2014-08-14
CN104054175B (en) 2018-03-06
JP5937225B2 (en) 2016-06-22
JP2015503228A (en) 2015-01-29
KR101759689B1 (en) 2017-07-19
JP6099794B2 (en) 2017-03-22

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