IN2014DN11168A - - Google Patents

Info

Publication number
IN2014DN11168A
IN2014DN11168A IN11168DEN2014A IN2014DN11168A IN 2014DN11168 A IN2014DN11168 A IN 2014DN11168A IN 11168DEN2014 A IN11168DEN2014 A IN 11168DEN2014A IN 2014DN11168 A IN2014DN11168 A IN 2014DN11168A
Authority
IN
India
Prior art keywords
bit
bits
data streams
writing
cycle
Prior art date
Application number
Inventor
Arnaud Dupas
Roger Boislaigue
Original Assignee
Alcatel Lucent
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Lucent filed Critical Alcatel Lucent
Publication of IN2014DN11168A publication Critical patent/IN2014DN11168A/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/0001Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005Switch and router aspects
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056Systems characterized by the type of code used
    • H04L1/0071Use of interleaving
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/275Interleaver wherein the permutation pattern is obtained using a congruential operation of the type y=ax+b modulo c
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2757Interleaver with an interleaving rule not provided for in the subgroups H03M13/2703 - H03M13/2753
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2771Internal interleaver for turbo codes
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2778Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2782Interleaver implementations, which reduce the amount of required interleaving memory
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65Purpose and implementation aspects
    • H03M13/6561Parallelized implementations
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/0001Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0003Details

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mathematical Physics (AREA)
  • Error Detection And Correction (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Small-Scale Networks (AREA)
  • Optical Communication System (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

Proposed is a bit interleaver for an optical line terminal of an optical access network. The bit interleaver contains a memory reader that provides data streams at bit level to a space time switch. The space time switch reads within one input cycle up to N bit sets from the data streams. The switch switches within one writing cycle up to N bits onto up to its output ports which provide respective output vectors. A number of N OR function elements determine within the writing cycle respective single output bits. A number of N memory elements write within the one writing cycle a respective one of the output bits into a respective one of their bit sub elements. A control unit that controls the reading of the data streams and also the switching of the bits by the switch. The control unit controls a choice of the writing addresses.
IN11168DEN2014 2012-08-01 2013-07-23 IN2014DN11168A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP12305947.9A EP2693673A1 (en) 2012-08-01 2012-08-01 Bit-interleaver for an optical line terminal
PCT/EP2013/065455 WO2014019881A1 (en) 2012-08-01 2013-07-23 Bit-interleaver for an optical line terminal

Publications (1)

Publication Number Publication Date
IN2014DN11168A true IN2014DN11168A (en) 2015-10-02

Family

ID=46785336

Family Applications (1)

Application Number Title Priority Date Filing Date
IN11168DEN2014 IN2014DN11168A (en) 2012-08-01 2013-07-23

Country Status (8)

Country Link
US (1) US9706272B2 (en)
EP (1) EP2693673A1 (en)
JP (1) JP5953435B2 (en)
KR (1) KR101739267B1 (en)
CN (1) CN104488208A (en)
IN (1) IN2014DN11168A (en)
TW (1) TWI500287B (en)
WO (1) WO2014019881A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2693673A1 (en) * 2012-08-01 2014-02-05 Alcatel Lucent Bit-interleaver for an optical line terminal
EP2899991A1 (en) * 2014-01-24 2015-07-29 Alcatel Lucent Space time switch and bit interleaver
CN106375243B (en) * 2015-07-22 2019-09-03 华为技术有限公司 Data processing equipment and optical transport network interchanger
EP3263743A1 (en) 2016-06-29 2018-01-03 Sandvik Intellectual Property AB Cvd coated cutting tool
CN110392997B (en) 2017-09-08 2023-04-18 Lg电子株式会社 Method and apparatus for transmitting and receiving wireless signal in wireless communication system

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9325697D0 (en) 1993-12-15 1994-02-16 British Telecomm Communications system
US6023783A (en) 1996-05-15 2000-02-08 California Institute Of Technology Hybrid concatenated codes and iterative decoding
US5928371A (en) * 1997-07-25 1999-07-27 Motorola, Inc. Systems for programmably interleaving and de-interleaving data and method thereof
US6625234B1 (en) * 1998-12-10 2003-09-23 Nortel Networks Limited Efficient implementations of proposed turbo code interleavers for third generation code division multiple access
EP1085660A1 (en) * 1999-09-15 2001-03-21 TELEFONAKTIEBOLAGET L M ERICSSON (publ) Parallel turbo coder implementation
EP1089439A1 (en) * 1999-09-28 2001-04-04 TELEFONAKTIEBOLAGET L M ERICSSON (publ) Interleaver and method for interleaving an input data bit sequence using a coded storing of symbol and additional information
US6625763B1 (en) * 2000-07-05 2003-09-23 3G.Com, Inc. Block interleaver and de-interleaver with buffer to reduce power consumption
US6854077B2 (en) * 2000-08-05 2005-02-08 Motorola, Inc. Apparatus and method for providing turbo code interleaving in a communications system
US6701482B2 (en) * 2001-09-20 2004-03-02 Qualcomm Incorporated Method and apparatus for coding bits of data in parallel
US6954885B2 (en) * 2001-12-14 2005-10-11 Qualcomm Incorporated Method and apparatus for coding bits of data in parallel
US6954832B2 (en) * 2002-05-31 2005-10-11 Broadcom Corporation Interleaver for iterative decoder
TWI220342B (en) * 2002-06-28 2004-08-11 Ind Tech Res Inst Optical interlaced wavelength division router
US7283753B2 (en) 2003-04-30 2007-10-16 Lucent Technologies Inc. System and method for WDM communication with interleaving of optical signals for efficient wavelength utilization
US20040268207A1 (en) * 2003-05-21 2004-12-30 Engim, Inc. Systems and methods for implementing a rate converting, low-latency, low-power block interleaver
JP4220365B2 (en) 2003-12-08 2009-02-04 株式会社ケンウッド Transmitting apparatus, receiving apparatus, data transmitting method, and data receiving method
WO2005091625A1 (en) * 2004-03-17 2005-09-29 Koninklijke Philips Electronics N.V. De-interlacing
US20060153285A1 (en) * 2005-01-12 2006-07-13 Texas Instruments Incorporaated Dynamic interleaver depth change for a general convolutional interleaver
US7839885B2 (en) 2005-04-25 2010-11-23 Lsi Corporation Connection memory for tributary time-space switches
US7409606B2 (en) * 2005-08-31 2008-08-05 Motorola, Inc. Method and system for interleaving in a parallel turbo decoder
US20070110180A1 (en) * 2005-11-11 2007-05-17 Broadcom Corporation, A California Corporation Configurable bit interleaving
US7783936B1 (en) * 2006-09-28 2010-08-24 L-3 Communications, Corp. Memory arbitration technique for turbo decoding
US7886203B2 (en) * 2007-09-05 2011-02-08 Mindtree Consulting Ltd Method and apparatus for bit interleaving and deinterleaving in wireless communication systems
US20090245423A1 (en) * 2008-03-28 2009-10-01 Qualcomm Incorporated De-Interlever That Simultaneously Generates Multiple Reorder Indices
US8982832B2 (en) 2008-04-28 2015-03-17 Qualcomm Incorporated Wireless communication of turbo coded data with time diversity
CN101520529B (en) * 2009-02-13 2011-01-19 上海大学 Method for designing arbitrary duty ratio unequal band width optical interleaver
US9130728B2 (en) * 2009-06-16 2015-09-08 Intel Mobile Communications GmbH Reduced contention storage for channel coding
US8370706B2 (en) * 2009-10-02 2013-02-05 Infinera Corporation Interleaved correction code transmission
US8352834B2 (en) * 2009-11-12 2013-01-08 Broadlogic Network Technologies Inc. High throughput interleaver / deinterleaver
US8402324B2 (en) * 2010-09-27 2013-03-19 Lsi Corporation Communications system employing local and global interleaving/de-interleaving
US9369207B2 (en) 2010-11-15 2016-06-14 Alcatel Lucent Apparatus and method for two-stage optical network
EP2693673A1 (en) * 2012-08-01 2014-02-05 Alcatel Lucent Bit-interleaver for an optical line terminal

Also Published As

Publication number Publication date
US20150172793A1 (en) 2015-06-18
EP2693673A1 (en) 2014-02-05
KR101739267B1 (en) 2017-05-24
TW201409964A (en) 2014-03-01
JP2015531196A (en) 2015-10-29
CN104488208A (en) 2015-04-01
TWI500287B (en) 2015-09-11
US9706272B2 (en) 2017-07-11
JP5953435B2 (en) 2016-07-20
KR20150028334A (en) 2015-03-13
WO2014019881A1 (en) 2014-02-06

Similar Documents

Publication Publication Date Title
IN2014DN11168A (en)
GB2511248A (en) Enhanced data retention mode for dynamic memories
WO2010101608A3 (en) Memory block selection
SG11202102794UA (en) Controlling access to multi-granularity data
EP2156301A4 (en) Data access tracing
TW200742042A (en) Multi-state resistive memory element, multi-bit resistive memory cell, operating method thereof, and data processing system using the memory element
GB2495873A (en) Wear-Leveling of Cells/Pages/Sub-Pages/Blocks of a Memory
TW200643424A (en) Interface and semiconductor testing apparatus using same
MX2019010418A (en) Predictive image coding device, predictive image coding method, predictive image coding program, predictive image decoding device, predictive image decoding method, and predictive image decoding program.
TW200629030A (en) Semiconductor integrated circuit
GB2571218A (en) Memory cell structure
GB2513749A (en) Read/write operations in solid-state storage devices
EP2519882A4 (en) Virtualization of chip enables
WO2008149407A1 (en) Jitter controller
WO2010093657A3 (en) Microcontroller with linear memory in a banked memory
WO2012064463A8 (en) Memory controller and system for storing blocks of data in non-volatile memory devices for high speed sequential reading
TW200733136A (en) Memory with spatially encoded data storage
TW201614645A (en) Page buffer
TW201614661A (en) Data writing method, memory storage device and memory control circuit unit
TW200704044A (en) Cellular data communication core
US8964499B2 (en) Row decoding circuit
GB201105029D0 (en) Method and system to lower the minimum operating voltage of register files
WO2010036056A3 (en) Apparatus and method for inputting english characters
CN204741444U (en) Switch plate system
KR20150073487A (en) Semiconductor Memory Apparatus