IN2014CN04649A - - Google Patents

Info

Publication number
IN2014CN04649A
IN2014CN04649A IN4649CHN2014A IN2014CN04649A IN 2014CN04649 A IN2014CN04649 A IN 2014CN04649A IN 4649CHN2014 A IN4649CHN2014 A IN 4649CHN2014A IN 2014CN04649 A IN2014CN04649 A IN 2014CN04649A
Authority
IN
India
Prior art keywords
cache
miss
virtual
detector
aliased
Prior art date
Application number
Inventor
James Norris Dieffenderfer
Robert D Clancy
Thomas Philip Speier
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of IN2014CN04649A publication Critical patent/IN2014CN04649A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache

Abstract

Apparatuses and related systems and methods for determining cache hit/miss of aliased addresses in virtually tagged cache(s) are disclosed. In one embodiment a virtual aliasing cache hit/miss detector for a VIVT cache is provided. The detector comprises a TLB configured to receive a first virtual address and a second virtual address from the VIVT cache resulting from an indexed read into the VIVT cache based on the first virtual address. The TLB is further configured to generate first and second physical addresses translated from the first and second virtual addresses respectively. The detector further comprises a comparator configured to receive the first and second physical addresses and effectuate a generation of an aliased cache hit/miss indicator based on a comparison of the first and second physical addresses. In this manner the virtual aliasing cache hit/miss detector correctly generates cache hits and cache misses even in the presence of aliased addressing.
IN4649CHN2014 2012-01-18 2013-01-17 IN2014CN04649A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201261587756P 2012-01-18 2012-01-18
US13/478,149 US9110830B2 (en) 2012-01-18 2012-05-23 Determining cache hit/miss of aliased addresses in virtually-tagged cache(s), and related systems and methods
PCT/US2013/021849 WO2013109696A2 (en) 2012-01-18 2013-01-17 Determining cache hit/miss of aliased addresses in virtually-tagged cache(s), and related systems and methods

Publications (1)

Publication Number Publication Date
IN2014CN04649A true IN2014CN04649A (en) 2015-09-18

Family

ID=48780825

Family Applications (1)

Application Number Title Priority Date Filing Date
IN4649CHN2014 IN2014CN04649A (en) 2012-01-18 2013-01-17

Country Status (9)

Country Link
US (1) US9110830B2 (en)
EP (1) EP2805245B1 (en)
JP (1) JP6019136B2 (en)
KR (1) KR101570155B1 (en)
CN (1) CN104040509B (en)
BR (1) BR112014017659A8 (en)
IN (1) IN2014CN04649A (en)
TW (1) TWI502349B (en)
WO (1) WO2013109696A2 (en)

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Also Published As

Publication number Publication date
CN104040509B (en) 2018-01-30
BR112014017659A8 (en) 2017-07-11
KR101570155B1 (en) 2015-11-19
CN104040509A (en) 2014-09-10
US9110830B2 (en) 2015-08-18
TW201346557A (en) 2013-11-16
BR112014017659A2 (en) 2017-06-20
JP6019136B2 (en) 2016-11-02
TWI502349B (en) 2015-10-01
US20130185520A1 (en) 2013-07-18
WO2013109696A2 (en) 2013-07-25
EP2805245B1 (en) 2019-10-09
JP2015507810A (en) 2015-03-12
EP2805245A2 (en) 2014-11-26
WO2013109696A3 (en) 2013-10-03
KR20140116935A (en) 2014-10-06

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