IN2014CN03081A - - Google Patents

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Publication number
IN2014CN03081A
IN2014CN03081A IN3081CHN2014A IN2014CN03081A IN 2014CN03081 A IN2014CN03081 A IN 2014CN03081A IN 3081CHN2014 A IN3081CHN2014 A IN 3081CHN2014A IN 2014CN03081 A IN2014CN03081 A IN 2014CN03081A
Authority
IN
India
Prior art keywords
low
via opening
value dielectric
value
substrate
Prior art date
Application number
Inventor
Vidhya Ramachandra
Shiqun Gu
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of IN2014CN03081A publication Critical patent/IN2014CN03081A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A low K value dielectric protection spacer for patterning through substrate vias (TSVs) through a low K value wiring layer (130). A method for forming a low K value dielectric protection spacer (820) includes etching a via opening through a low K value dielectric interconnect layer (130). A protective layer is deposited in the via opening and on the low K value dielectric interconnect layer. At least a portion of the protective layer is etched from the bottom of the via opening and from a horizontal surface of the low K value dielectric interconnect layer. The etching leaving a protective sidewall spacer (820) on a sidewall of the via opening. A through substrate via is etched through the bottom of the via opening and through the semiconductor substrate. The through substrate via is filled with a conductive material (890).
IN3081CHN2014 2011-11-09 2012-11-09 IN2014CN03081A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201161557842P 2011-11-09 2011-11-09
US13/588,438 US9059263B2 (en) 2011-11-09 2012-08-17 Low-K dielectric protection spacer for patterning through substrate vias through a low-K wiring layer
PCT/US2012/064531 WO2013071171A1 (en) 2011-11-09 2012-11-09 Low-k dielectric protection spacer for patterning through substrate vias through a low-k wiring layer

Publications (1)

Publication Number Publication Date
IN2014CN03081A true IN2014CN03081A (en) 2015-07-03

Family

ID=48223131

Family Applications (1)

Application Number Title Priority Date Filing Date
IN3081CHN2014 IN2014CN03081A (en) 2011-11-09 2012-11-09

Country Status (7)

Country Link
US (1) US9059263B2 (en)
EP (1) EP2777071B1 (en)
JP (1) JP6068492B2 (en)
KR (1) KR101610323B1 (en)
CN (1) CN103918068B (en)
IN (1) IN2014CN03081A (en)
WO (1) WO2013071171A1 (en)

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Publication number Priority date Publication date Assignee Title
US9245790B2 (en) * 2013-01-23 2016-01-26 GlobalFoundries, Inc. Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via
US10170396B2 (en) * 2014-02-14 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Through via structure extending to metallization layer
US9343403B2 (en) 2014-04-04 2016-05-17 Qualcomm Incorporated Stress mitigation structure for wafer warpage reduction
CN105225976A (en) * 2014-06-25 2016-01-06 中芯国际集成电路制造(上海)有限公司 The manufacture method of pad and semiconductor device
US9620454B2 (en) 2014-09-12 2017-04-11 Qualcomm Incorporated Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods
KR102652854B1 (en) * 2016-08-17 2024-04-02 삼성전자주식회사 Semiconductor device and method for fabricating the same
US10269559B2 (en) * 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer
US10535636B2 (en) * 2017-11-15 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrating passive devices in package structures
US10734234B2 (en) 2017-12-18 2020-08-04 International Business Machines Corporation Metal cut patterning and etching to minimize interlayer dielectric layer loss
US10734278B2 (en) * 2018-06-15 2020-08-04 Tokyo Electron Limited Method of protecting low-K layers
US10784143B2 (en) 2019-01-31 2020-09-22 Globalfoundries Inc. Trench isolation preservation during transistor fabrication
US10832950B2 (en) 2019-02-07 2020-11-10 International Business Machines Corporation Interconnect with high quality ultra-low-k dielectric
US11532579B2 (en) 2020-07-13 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Passivation structure with increased thickness for metal pads
KR20220010852A (en) 2020-07-20 2022-01-27 삼성전자주식회사 Semiconductor device and method of manufacturing the semiconductor device
US11769736B2 (en) 2021-04-14 2023-09-26 Micron Technology, Inc. Scribe structure for memory device
US11715704B2 (en) * 2021-04-14 2023-08-01 Micron Technology, Inc. Scribe structure for memory device
US11600578B2 (en) 2021-04-22 2023-03-07 Micron Technology, Inc. Scribe structure for memory device
US20230064183A1 (en) * 2021-09-02 2023-03-02 Applied Materials, Inc. Self-aligned wide backside power rail contacts to multiple transistor sources
CN115000005A (en) * 2022-05-27 2022-09-02 华进半导体封装先导技术研发中心有限公司 Manufacturing method of active chip silicon through hole for protecting low-k medium

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US6509267B1 (en) * 2001-06-20 2003-01-21 Advanced Micro Devices, Inc. Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer
JP3696208B2 (en) * 2003-01-22 2005-09-14 株式会社東芝 Semiconductor device
JP3891299B2 (en) * 2003-05-06 2007-03-14 セイコーエプソン株式会社 Semiconductor device manufacturing method, semiconductor device, semiconductor device, electronic device
US7081407B2 (en) 2003-12-16 2006-07-25 Lam Research Corporation Method of preventing damage to porous low-k materials during resist stripping
US7169698B2 (en) 2004-01-14 2007-01-30 International Business Machines Corporation Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner
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US7205226B1 (en) 2005-02-24 2007-04-17 Lam Research Corporation Sacrificial layer for protection during trench etch
US7345343B2 (en) 2005-08-02 2008-03-18 Texas Instruments Incorporated Integrated circuit having a top side wafer contact and a method of manufacture therefor
US7262134B2 (en) * 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
KR100830581B1 (en) 2006-11-06 2008-05-22 삼성전자주식회사 Semiconductor device having through via and method for manufacturing the same
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Also Published As

Publication number Publication date
CN103918068A (en) 2014-07-09
CN103918068B (en) 2016-11-09
EP2777071B1 (en) 2017-01-04
US20130113068A1 (en) 2013-05-09
US9059263B2 (en) 2015-06-16
JP6068492B2 (en) 2017-01-25
JP2014533000A (en) 2014-12-08
KR101610323B1 (en) 2016-04-08
KR20140093980A (en) 2014-07-29
EP2777071A1 (en) 2014-09-17
WO2013071171A1 (en) 2013-05-16

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