IN2013CH05121A - - Google Patents

Info

Publication number
IN2013CH05121A
IN2013CH05121A IN5121CH2013A IN2013CH05121A IN 2013CH05121 A IN2013CH05121 A IN 2013CH05121A IN 5121CH2013 A IN5121CH2013 A IN 5121CH2013A IN 2013CH05121 A IN2013CH05121 A IN 2013CH05121A
Authority
IN
India
Application number
Inventor
Somaiya Vikram
Original Assignee
Sandisk Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandisk Technologies Inc filed Critical Sandisk Technologies Inc
Priority to IN5121CH2013 priority Critical patent/IN2013CH05121A/en
Priority to US14/191,097 priority patent/US9684474B2/en
Priority to PCT/US2014/064064 priority patent/WO2015073276A1/en
Priority to TW103139293A priority patent/TWI613586B/en
Publication of IN2013CH05121A publication Critical patent/IN2013CH05121A/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659Command handling arrangements, e.g. command buffers, queues, command scheduling
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604Improving or facilitating administration, e.g. storage management
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/24Bit-line control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10Aspects relating to interfaces of memory device to external buses
    • G11C2207/105Aspects related to pads, pins or terminals
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
IN5121CH2013 2013-11-12 2013-11-12 IN2013CH05121A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IN5121CH2013 IN2013CH05121A (en) 2013-11-12 2013-11-12
US14/191,097 US9684474B2 (en) 2013-11-12 2014-02-26 Single input/output cell with multiple bond pads and/or transmitters
PCT/US2014/064064 WO2015073276A1 (en) 2013-11-12 2014-11-05 Memory controller selectively transmitting signals to memory dies via selected bond pads
TW103139293A TWI613586B (en) 2013-11-12 2014-11-12 Single input/output cell with multiple bond pads and/or transmitters

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IN5121CH2013 IN2013CH05121A (en) 2013-11-12 2013-11-12

Publications (1)

Publication Number Publication Date
IN2013CH05121A true IN2013CH05121A (en) 2015-05-29

Family

ID=53044839

Family Applications (1)

Application Number Title Priority Date Filing Date
IN5121CH2013 IN2013CH05121A (en) 2013-11-12 2013-11-12

Country Status (4)

Country Link
US (1) US9684474B2 (en)
IN (1) IN2013CH05121A (en)
TW (1) TWI613586B (en)
WO (1) WO2015073276A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9846192B2 (en) * 2015-02-25 2017-12-19 Nxp B.V. Switched probe contact
CN112655088A (en) * 2018-09-12 2021-04-13 华为技术有限公司 IC die-to-IC die interconnect using error correction code and data path interleaving
US20220102333A1 (en) * 2020-09-29 2022-03-31 Alibaba Group Holding Limited Configurable computer memory architecture

Family Cites Families (26)

* Cited by examiner, † Cited by third party
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US5506499A (en) 1995-06-05 1996-04-09 Neomagic Corp. Multiple probing of an auxilary test pad which allows for reliable bonding to a primary bonding pad
JP3588529B2 (en) 1997-01-28 2004-11-10 株式会社東芝 Semiconductor device and its application system device
JP3737333B2 (en) 2000-03-17 2006-01-18 沖電気工業株式会社 Semiconductor device
US6320757B1 (en) 2000-07-12 2001-11-20 Advanced Semiconductor Engineering, Inc. Electronic package
US6812726B1 (en) 2002-11-27 2004-11-02 Inapac Technology, Inc. Entering test mode and accessing of a packaged semiconductor device
US6472747B2 (en) 2001-03-02 2002-10-29 Qualcomm Incorporated Mixed analog and digital integrated circuits
JP2003059288A (en) 2001-08-09 2003-02-28 Mitsubishi Electric Corp Semiconductor device
JP2003060151A (en) 2001-08-10 2003-02-28 Fujitsu Ltd Semiconductor device
US6807109B2 (en) 2001-12-05 2004-10-19 Renesas Technology Corp. Semiconductor device suitable for system in package
JP2003319412A (en) 2002-04-19 2003-11-07 Matsushita Electric Ind Co Ltd Image processing back-up system, image processor, and image display device
US6891275B2 (en) 2002-07-26 2005-05-10 Qualcomm Incorporated Method for accommodating small minimum die in wire bonded area array packages
US6960836B2 (en) * 2003-09-30 2005-11-01 Agere Systems, Inc. Reinforced bond pad
US7680966B1 (en) 2004-06-29 2010-03-16 National Semiconductor Corporation Memory interface including generation of timing signals for memory operation
US7598606B2 (en) 2005-02-22 2009-10-06 Stats Chippac Ltd. Integrated circuit package system with die and package combination
DE102005009163B4 (en) 2005-02-25 2013-08-14 Infineon Technologies Ag Semiconductor device having a semiconductor chip having signal contact surfaces and supply contact surfaces, and method for producing the semiconductor device
JP4703300B2 (en) 2005-07-20 2011-06-15 富士通セミコンダクター株式会社 Relay board and semiconductor device including the relay board
JP4595730B2 (en) 2005-07-28 2010-12-08 セイコーエプソン株式会社 Semiconductor device and electronic equipment
KR100690922B1 (en) 2005-08-26 2007-03-09 삼성전자주식회사 Semiconductor device package
US7643371B2 (en) 2006-12-28 2010-01-05 Spansion Llc Address/data multiplexed device
EP2329494A2 (en) 2008-09-09 2011-06-08 Vl C.V. Memory controller
WO2011049710A2 (en) * 2009-10-23 2011-04-28 Rambus Inc. Stacked semiconductor device
US8681546B2 (en) 2011-02-22 2014-03-25 Apple Inc. Variable impedance control for memory devices
KR20130036555A (en) 2011-10-04 2013-04-12 에스케이하이닉스 주식회사 Voltage supplying circuit, semiconductor memory device and operating method thereof
US8873282B2 (en) * 2011-10-18 2014-10-28 Micron Technology, Inc. Interfaces and die packages, and appartuses including the same
US8780600B2 (en) * 2011-12-07 2014-07-15 Apple Inc. Systems and methods for stacked semiconductor memory devices
JP2013187594A (en) 2012-03-06 2013-09-19 Toshiba Corp Interface circuit

Also Published As

Publication number Publication date
US9684474B2 (en) 2017-06-20
US20150134918A1 (en) 2015-05-14
TW201531928A (en) 2015-08-16
WO2015073276A1 (en) 2015-05-21
TWI613586B (en) 2018-02-01

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