IES980712A2 - An ATM cell processor - Google Patents

Abstract

An ATM cell processor (10) has a backplane interface (11), a line interface (15), and various processing functions between the interfaces. Cells directed to the line interface (15) are controlled by a queueing function (12) which uses external cell memory via a controller (13) and external control memory via a controller (14). Cells from the backplane are identified and routed by a mapping function (16).

Description

The invention relates to a processor for handling asynchronous transfer mode (ATM) cells. An object of the invention is to provide for efficient handling of cells by a processor. Another object is that the processor has flexibility in the manner in which it operates so that it may be used in different environments with relatively simple I configuration, A still further object is to provide a cell processor which may be controlled in a 10 comprehensive manner with relatively simple control circuits.

According to the invention, there is provided an ATM cell processor comprising at least two interfaces, and a queueing function between the interfaces for controlling transfer of cells. The queueing function allows cell traffic management in a very effective manner.

The interfaces are preferably bi-directional.

Preferably, the queueing function uses a cell memory for storage of cell queues, and a control memory for storing queueing control settings. This is a very effective way of achieving the necessary control in a flexible manner.

In one embodiment, the memory is at least partly external to the processor and is accessed via a controller. This allows easy expansion and flexibility for different applications generally.

In another embodiment, the processor further comprises a mapping function for mapping received cells from a line according to the VPI/VCI. This allows integration of the processor into a system having multiple internal destinations for received cells.

Preferably, the mapping function comprises means for adding an additional header for internal control signalling. This further enhan ^e^f^ctivenes^of internal J^ting.of sicnals.

J.\iT i? UNDER 2g AND RULE 23 ! IB IE 980712 -2 In one embodiment, the processor further comprises a policing function tor monitoring traffic characteristics of cells received from the line. This is very important for connection of a system with multiple client systems and is particularly useful for monitoring contracts. ΐ In one embodiment, the processor further comprises a segmentation and reassembly (SAR) interface for handling ATM cell control signals. This allows connection of the cell processor to a control processor in an efficient manner using ATM cells for control signalling. Thus the cell processor may be easily configured for a wide range of applications - the control processor performing initialisation and on-line control and monitoring functions.

In one embodiment, the SAR interface is connected to the queueing function. This allows flexible management of control signal flow according to suitable priority- queuing schemes.

In another embodiment, the cell processor comprises a control processor interface connected to a memory controller to allow initial setup configuration and on-going monitoring.

The invention will be more clearly understood from the following description of some embodiments thereof, given by way of example only with reference to the accompanying drawings in which:Fig. I is a schematic representation of a cell processor of the invention: Fig. 2 is a diagram illustrating operation of a queue server matrix; and Fig. 3 is a diagram illustrating a UTOPIA interface.

IE 980712 • 3Referring to Fig. I. there is shown a cell processor 10 of the invention. The processor 10 is an application specific integrated circuit (ASIC), the application being processing of ATM cells.

The main components of the processor 10 are now briefly described briefly with reference to general signal flows through the processor. The cell rate handled is 373 K 1 cells per second, which represents a bit rate of greater than 155 Mpps. The processor 10 has a backplane interface 11 for interfacing according to the CUBIT™ protocol via a backplane. The backplane interface 11 may thus be used for interfacing where the cell rate is not well controlled. This problem is overcome with traffic management performed by a queueing function 12. The queueing function 12 is very important as it performs extensive buffering operations using DRAM or SRAM external to the processor 10 and accessed via a controller 13. It also uses an SRAM controller 14 for access to additional off-chip SRAM. The off-chip memory is used in general for such things as manipulating link lists, and storing cells awaiting transfer. More specifically, the SRAM accessed by the controller 14 is used effectively as an external register and to store data including the queue sizes. On the other hand, the DRAM or SRAM accessed via the controller 13 (Cell RAM) is used for storing actual cells. When dequeueing from the Cell RAM. the SRAM is used to track the cells using pointer information.

Continuing on the path A indicated in Fig. 1, the cells are then transferred to a multi-PHY line interface 15. This is a master interface which supports many ports, in this embodiment eight. Again, the UTOPIA protocol is used.

Thus, in the path A, the processor 10 does not change the cells, but does manage output to the line by using queueing mechanisms.

In the opposite direction, cells are received as indicated by the arrow B at the line interface 15 and are transferred to a mapping function 16. The mapping function 16 changes the VCI/VPI headers according to the destination of the cells and by doing this, it re-directs them to the correct destination. The cells are passed to a policing function 17 ,fc 980712 -4 which operates according to algorithms to evaluate certain policing parameters such as the cell rate for a particular contract. Various parameters are taken into account such as the temporary nature of any usage of excessive bandwidth lor a particular contract. The SRAM accessed via the controller 14 is used for some of these functions. After the policing functions, the cells are transferred to the backplane interface 11.

I The processor 10 also comprises a processor interface 20 and a configuration and status function 21, which are connected to the queueing function 12 and the SRAM controller 14. This allows a microprocessor to access the processor 10 and perform a limited set of functions including initial setup and configuration and subsequent status monitoring. An important initial setup function is configuration of the SRAM 14. Subsequently, the processor can access the SRAM locations via the controller 14 and the interlace 20 to monitor parameters such as the count of dropped cells.

An important aspect of the processor 10 is that it can use control signals communicated in the ATM format. To do this, it uses a segmentation and reassembly (SAR) interface 25 which performs AAL5 segmentation and reassembly of ATM messages. This interface is used for communication of ATM messages with a SAR device. The SAR device interfaces with another device such as a microprocessor (possibly the same microprocessor as is connected to the interface 20) for comprehensive control communication. The ATM nature of the communication is transparent to the microprocessor because of operation of the SAR device. Thus, a single microprocessor may have access to the processor 10 in two different manners, one being a direct access for initial setup and monitoring of parameters, the other being for comprehensive control communication.

In more detail, the cells which are received at the backplane interface 11 are queued in one of the multiple queues depending on their VPI/VCI. The queues are serviced on a pre-programmed basis to implement a priority queueing system. Queues that grow too large may have cells discarded on a configured basis. Statistics are kept on the number of IE 980712 -5 cells received, the number of cells transmitted, the number of bad cells, and the number of cells dropped due to congestion.

Queueing is initialised by a microprocessor using the configuration and status function 21. This function has registers, in which there is a notional split of registers related to queueing and those related.to dequeueing. The queueing function 12 uses a significant i number of tables to control the buffering and congestion management functions. One such table is a path descriptor, the start address of which is provided b> a configuration register. The VPI of an incoming cell is used to form an offset into this table. In addition there are special path descriptors for mapping, the SAR. and the processor, the addresses again being provided by configuration registers.

Another table is a queue descriptor, which contains information about an individual queue. All queues are identical, however, they may appear to have different priorities depending on programming of a queue server matrix. Queues are irrevocably tied io target output ports and each of the eight line ports has eight queues associated with it. In addition, a single queue is maintained for each of the processor, SAR, and mapping entities. Mapping between queues and targets is specified in tw'o tables, one for each of aggregate and tributary modes. Each queue has a four-word descriptor, and the offset from the value of the configuration register holding the start location is simply the queue number multiplied by four.

The queue server matrix controls the order in which queues are serviced. Its location and maximum size (l024 elements) are indicated by configuration registers. Each element of the matrix holds three words. The three words are to be interpreted as shown in Fig. 2. The twelfth byte is not used. The queues are checked in ascending order, i.e. the first queue checked is the most significant byte of the first word. Within each byte, only the least significant seven bits are meaningful, i.e. bits 6 to 0.

Storage pools of the queues are referred to as heaps, and consist of stacks of DRAM addresses. There are twenty heaps maintained. The heap structure is implemented as a IE 980712 -6set of pointers kept internally and also the DRAM addresses which arc stored in the SRAM. Initialisation of the heap involves programming up the pointers into SRAM for the top-of-stack and start-of-stack for each used heap, and then initialisation of the SRAM location between those two pointer values with a unique and valid set of DRAM locations. Configuration registers are used for programming the heap pointers.

As shown in Fig. 1, the output cells of the queueing function are transferred to the line interface 15 or the SAR interface 25.

In the opposite direction, cells received at the line interface 15 are passed to the mapping and policing functions 16 and 17. The cells are passed to the backplane interlace 11. to the queueing function 12, or are dropped. Again, the configuration registers store the initialisation information. SRAM tables are maintained by the functions 16 and 17. There are five tables associated with the mapping function 16 as follows; - per port statistics table, - VCC connection table, dequeue connection table, and - secondary mapping descriptor table.

Storage of these tables is set by the configuration registers. The per port statistics table stores information including the numbers of cells w ith invalid and disabled VPI/VCIs and with unsupported PTIs. It also includes the VPI/VCIs of the last disabled and invalid cells.

The VCC connection table contains the following information on a per connection basis:mapping descriptor.

IE 980712 -7received cell count. dropped cell count, and GCRA words l - 4. i The VPC connection table is identical, except that VPIs arc used in place of VCls.

The dequeue connection table has a maximum of 1024 entries and consists of 1024 32 bit mapping descriptors.

The secondary mapping descriptor table consists of 40% 32 bit entries. Each secondary mapping descriptor is 14 bits long, as set out below.

Field Name Size Bit Position Reserved 18 14-31 map_vpi 1 13 cellrouting 3 10-12 vci_map 10 0-9 Referring now' to the three UTOPIA interfaces. Fig. 3 shows an overview. All of the interfaces use the appropriate Start-of-Cell (SOC) signal to initialise cell reception from an external source. Each interface counts octets and an error indication is given when a SOC is activated at an unexpected time. This gives a warning of malformed cells entering the ASIC whilst providing a mechanism to recover at the next cell boundary. Short cells are discarded, whilst long cells are truncated and passed on. Both cause an error indication.

The invention is not limited to the embodiments described, but may be varied in construction and detail within the scope of the claims.

Claims (5)

Claims

1. An ATM cell processor comprising at least two interfaces, and a queuing function between the interfaces for controlling transfer of cells.

2. A cell processor as claimed in claim l. wherein the interfaces are bi-directional, and wherein the queuing function uses a cell memory for storage of cell queues, and a control memory for storing queueing control settings, and wherein the memory is at least partly external to the processor and is accessed via a controller, and wherein the processor further comprises a mapping function for mapping received cells from a line according to the VPLYCl. and wherein the mapping function comprises means for adding an additional header for internal control signalling.

3. A cell processor as claimed in claims l or 2, further comprising a policing function for monitoring traffic characteristics of cells receiv ed from the line.

4. A cell processor as claimed in any preceding claim, further comprising a segmentation and reassembly (SAR) interface for handling ATM cell control signals, and wherein the SAR interface is connected to the queueing function, and wherein the processor further comprises a control processor interface connected to a memory controller to allow initial setup configuration and on-going monitoring.

5. A cell processor substantially as described with reference to the drawings.