IES950209A2 - Communication apparatus for communicating two microprocessors - Google Patents

Communication apparatus for communicating two microprocessors

Info

Publication number
IES950209A2
IES950209A2 IES950209A IES950209A2 IE S950209 A2 IES950209 A2 IE S950209A2 IE S950209 A IES950209 A IE S950209A IE S950209 A2 IES950209 A2 IE S950209A2
Authority
IE
Ireland
Prior art keywords
microprocessor
microprocessors
latch
appropriate
data
Prior art date
Application number
Inventor
Peter Brady
Brian Keogh
Martin Walsh
Original Assignee
Lake Res Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lake Res Ltd filed Critical Lake Res Ltd
Priority to IES950209 priority Critical patent/IES950209A2/en
Publication of IES65387B2 publication Critical patent/IES65387B2/en
Publication of IES950209A2 publication Critical patent/IES950209A2/en
Priority to IE960234A priority patent/IE960234A1/en
Priority to GB9606211A priority patent/GB2299188B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

First and second microporcessors (1,2) communicate through a parallel data bus (5) through apparatus (3). The apparatus (3) comprises a first latch (7) and a first buffer (8) located in the data bus (5) for transferring data in individual eight bit data words from the first to the second microprocessors (1,2) and a second latch (9) and a second buffer (10) for transferring data in individual eight bit data words from the second microprocessor to the first microprocessor (2,1). First and second interrupt lines (14,16) transmit an interrupt signal from the appropriate first and second microprocessor (1,2) after a data word has been written to the appropriate first and second latch by the first or second microprocessor (1,2), and interrupt acknowledge lines (15,17) transmit an interrupt acknowledge signal from the microprocessor of the first and second microprocessors (1,2) after a data word has been read from the appropriate latch (7,9) through the appropriate buffer (8,10).
IES950209 1995-03-24 1995-03-24 Communication apparatus for communicating two microprocessors IES950209A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IES950209 IES950209A2 (en) 1995-03-24 1995-03-24 Communication apparatus for communicating two microprocessors
IE960234A IE960234A1 (en) 1995-03-24 1996-03-21 Communication apparatus for communicating two¹microprocessors
GB9606211A GB2299188B (en) 1995-03-24 1996-03-25 Communication apparatus for communicating two microprocessors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IES950209 IES950209A2 (en) 1995-03-24 1995-03-24 Communication apparatus for communicating two microprocessors

Publications (2)

Publication Number Publication Date
IES65387B2 IES65387B2 (en) 1995-10-18
IES950209A2 true IES950209A2 (en) 1995-10-18

Family

ID=11040691

Family Applications (1)

Application Number Title Priority Date Filing Date
IES950209 IES950209A2 (en) 1995-03-24 1995-03-24 Communication apparatus for communicating two microprocessors

Country Status (2)

Country Link
GB (1) GB2299188B (en)
IE (1) IES950209A2 (en)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE399773B (en) * 1977-03-01 1978-02-27 Ellemtel Utvecklings Ab ADDRESS AND INTERRUPTION SIGNAL GENERATOR
US4698746A (en) * 1983-05-25 1987-10-06 Ramtek Corporation Multiprocessor communication method and apparatus
US4669044A (en) * 1984-07-02 1987-05-26 Ncr Corporation High speed data transmission system
FR2568035B1 (en) * 1984-07-17 1989-06-02 Sagem METHOD FOR INTERCONNECTING MICROPROCESSORS
DE3501194C2 (en) * 1985-01-16 1997-06-19 Bosch Gmbh Robert Method and device for data exchange between microprocessors
US4831520A (en) * 1987-02-24 1989-05-16 Digital Equipment Corporation Bus interface circuit for digital data processor
US4995056A (en) * 1989-01-13 1991-02-19 International Business Machines Corporation System and method for data communications
JP3360856B2 (en) * 1992-12-18 2003-01-07 富士通株式会社 Processor

Also Published As

Publication number Publication date
IES65387B2 (en) 1995-10-18
GB2299188A (en) 1996-09-25
GB2299188B (en) 2000-03-22
GB9606211D0 (en) 1996-05-29

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Legal Events

Date Code Title Description
MM4A Patent lapsed